diff --git a/rtl/eth/taxi_axis_gmii_rx.sv b/rtl/eth/taxi_axis_gmii_rx.sv new file mode 100644 index 0000000..83fc604 --- /dev/null +++ b/rtl/eth/taxi_axis_gmii_rx.sv @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2015-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4-Stream GMII frame receiver (GMII in, AXI out) + */ +module taxi_axis_gmii_rx # +( + parameter DATA_W = 8, + parameter logic PTP_TS_EN = 1'b0, + parameter PTP_TS_W = 96 +) +( + input wire logic clk, + input wire logic rst, + + /* + * GMII input + */ + input wire logic [DATA_W-1:0] gmii_rxd, + input wire logic gmii_rx_dv, + input wire logic gmii_rx_er, + + /* + * Receive interface (AXI stream) + */ + taxi_axis_if.src m_axis_rx, + + /* + * PTP + */ + input wire logic [PTP_TS_W-1:0] ptp_ts, + + /* + * Control + */ + input wire logic clk_enable, + input wire logic mii_select, + + /* + * Configuration + */ + input wire logic cfg_rx_enable, + + /* + * Status + */ + output wire logic start_packet, + output wire logic error_bad_frame, + output wire logic error_bad_fcs +); + +localparam USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1; + +// check configuration +if (DATA_W != 8) + $fatal(0, "Error: Interface width must be 8 (instance %m)"); + +if (m_axis_rx.DATA_W != DATA_W) + $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)"); + +if (m_axis_rx.USER_W != USER_W) + $fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)"); + +localparam [7:0] + ETH_PRE = 8'h55, + ETH_SFD = 8'hD5; + +localparam [2:0] + STATE_IDLE = 3'd0, + STATE_PAYLOAD = 3'd1, + STATE_WAIT_LAST = 3'd2; + +logic [2:0] state_reg = STATE_IDLE, state_next; + +// datapath control signals +logic reset_crc; +logic update_crc; + +logic mii_odd = 1'b0; +logic in_frame = 1'b0; + +logic [DATA_W-1:0] gmii_rxd_d0 = '0; +logic [DATA_W-1:0] gmii_rxd_d1 = '0; +logic [DATA_W-1:0] gmii_rxd_d2 = '0; +logic [DATA_W-1:0] gmii_rxd_d3 = '0; +logic [DATA_W-1:0] gmii_rxd_d4 = '0; + +logic gmii_rx_dv_d0 = 1'b0; +logic gmii_rx_dv_d1 = 1'b0; +logic gmii_rx_dv_d2 = 1'b0; +logic gmii_rx_dv_d3 = 1'b0; +logic gmii_rx_dv_d4 = 1'b0; + +logic gmii_rx_er_d0 = 1'b0; +logic gmii_rx_er_d1 = 1'b0; +logic gmii_rx_er_d2 = 1'b0; +logic gmii_rx_er_d3 = 1'b0; +logic gmii_rx_er_d4 = 1'b0; + +logic [DATA_W-1:0] m_axis_rx_tdata_reg = '0, m_axis_rx_tdata_next; +logic m_axis_rx_tvalid_reg = 1'b0, m_axis_rx_tvalid_next; +logic m_axis_rx_tlast_reg = 1'b0, m_axis_rx_tlast_next; +logic m_axis_rx_tuser_reg = 1'b0, m_axis_rx_tuser_next; + +logic start_packet_int_reg = 1'b0; +logic start_packet_reg = 1'b0; +logic error_bad_frame_reg = 1'b0, error_bad_frame_next; +logic error_bad_fcs_reg = 1'b0, error_bad_fcs_next; + +logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0; + +logic [31:0] crc_state = '1; +wire [31:0] crc_next; + +assign m_axis_rx.tdata = m_axis_rx_tdata_reg; +assign m_axis_rx.tkeep = 1'b1; +assign m_axis_rx.tstrb = m_axis_rx.tkeep; +assign m_axis_rx.tvalid = m_axis_rx_tvalid_reg; +assign m_axis_rx.tlast = m_axis_rx_tlast_reg; +assign m_axis_rx.tid = '0; +assign m_axis_rx.tdest = '0; +assign m_axis_rx.tuser[0] = m_axis_rx_tuser_reg; +if (PTP_TS_EN) begin + assign m_axis_rx.tuser[1 +: PTP_TS_W] = ptp_ts_out_reg; +end + +assign start_packet = start_packet_reg; +assign error_bad_frame = error_bad_frame_reg; +assign error_bad_fcs = error_bad_fcs_reg; + +taxi_lfsr #( + .LFSR_W(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_GALOIS(1), + .LFSR_FEED_FORWARD(0), + .REVERSE(1), + .DATA_W(8) +) +eth_crc_8 ( + .data_in(gmii_rxd_d4), + .state_in(crc_state), + .data_out(), + .state_out(crc_next) +); + +always_comb begin + state_next = STATE_IDLE; + + reset_crc = 1'b0; + update_crc = 1'b0; + + m_axis_rx_tdata_next = '0; + m_axis_rx_tvalid_next = 1'b0; + m_axis_rx_tlast_next = 1'b0; + m_axis_rx_tuser_next = 1'b0; + + error_bad_frame_next = 1'b0; + error_bad_fcs_next = 1'b0; + + if (!clk_enable) begin + // clock disabled - hold state + state_next = state_reg; + end else if (mii_select && !mii_odd) begin + // MII even cycle - hold state + state_next = state_reg; + end else begin + case (state_reg) + STATE_IDLE: begin + // idle state - wait for packet + reset_crc = 1'b1; + + if (gmii_rx_dv_d4 && !gmii_rx_er_d4 && gmii_rxd_d4 == ETH_SFD && cfg_rx_enable) begin + state_next = STATE_PAYLOAD; + end else begin + state_next = STATE_IDLE; + end + end + STATE_PAYLOAD: begin + // read payload + update_crc = 1'b1; + + m_axis_rx_tdata_next = gmii_rxd_d4; + m_axis_rx_tvalid_next = 1'b1; + + if (gmii_rx_dv_d4 && gmii_rx_er_d4) begin + // error + m_axis_rx_tlast_next = 1'b1; + m_axis_rx_tuser_next = 1'b1; + error_bad_frame_next = 1'b1; + state_next = STATE_WAIT_LAST; + end else if (!gmii_rx_dv) begin + // end of packet + m_axis_rx_tlast_next = 1'b1; + if (gmii_rx_er_d0 || gmii_rx_er_d1 || gmii_rx_er_d2 || gmii_rx_er_d3) begin + // error received in FCS bytes + m_axis_rx_tuser_next = 1'b1; + error_bad_frame_next = 1'b1; + end else if ({gmii_rxd_d0, gmii_rxd_d1, gmii_rxd_d2, gmii_rxd_d3} == ~crc_next) begin + // FCS good + m_axis_rx_tuser_next = 1'b0; + end else begin + // FCS bad + m_axis_rx_tuser_next = 1'b1; + error_bad_frame_next = 1'b1; + error_bad_fcs_next = 1'b1; + end + state_next = STATE_IDLE; + end else begin + state_next = STATE_PAYLOAD; + end + end + STATE_WAIT_LAST: begin + // wait for end of packet + + if (~gmii_rx_dv) begin + state_next = STATE_IDLE; + end else begin + state_next = STATE_WAIT_LAST; + end + end + default: begin + // invalid state, return to idle + state_next = STATE_IDLE; + end + endcase + end +end + +always_ff @(posedge clk) begin + state_reg <= state_next; + + m_axis_rx_tdata_reg <= m_axis_rx_tdata_next; + m_axis_rx_tvalid_reg <= m_axis_rx_tvalid_next; + m_axis_rx_tlast_reg <= m_axis_rx_tlast_next; + m_axis_rx_tuser_reg <= m_axis_rx_tuser_next; + + start_packet_int_reg <= 1'b0; + start_packet_reg <= 1'b0; + + if (start_packet_int_reg) begin + ptp_ts_out_reg <= ptp_ts; + start_packet_reg <= 1'b1; + end + + if (clk_enable) begin + if (mii_select) begin + mii_odd <= !mii_odd; + + if (in_frame) begin + in_frame <= gmii_rx_dv; + end else if (gmii_rx_dv && {gmii_rxd[3:0], gmii_rxd_d0[7:4]} == ETH_SFD) begin + in_frame <= 1'b1; + start_packet_int_reg <= 1'b1; + mii_odd <= 1'b1; + end + + gmii_rxd_d0 <= {gmii_rxd[3:0], gmii_rxd_d0[7:4]}; + + if (mii_odd) begin + gmii_rxd_d1 <= gmii_rxd_d0; + gmii_rxd_d2 <= gmii_rxd_d1; + gmii_rxd_d3 <= gmii_rxd_d2; + gmii_rxd_d4 <= gmii_rxd_d3; + + gmii_rx_dv_d0 <= gmii_rx_dv & gmii_rx_dv_d0; + gmii_rx_dv_d1 <= gmii_rx_dv_d0 & gmii_rx_dv; + gmii_rx_dv_d2 <= gmii_rx_dv_d1 & gmii_rx_dv; + gmii_rx_dv_d3 <= gmii_rx_dv_d2 & gmii_rx_dv; + gmii_rx_dv_d4 <= gmii_rx_dv_d3 & gmii_rx_dv; + + gmii_rx_er_d0 <= gmii_rx_er | gmii_rx_er_d0; + gmii_rx_er_d1 <= gmii_rx_er_d0; + gmii_rx_er_d2 <= gmii_rx_er_d1; + gmii_rx_er_d3 <= gmii_rx_er_d2; + gmii_rx_er_d4 <= gmii_rx_er_d3; + end else begin + gmii_rx_dv_d0 <= gmii_rx_dv; + gmii_rx_er_d0 <= gmii_rx_er; + end + end else begin + if (in_frame) begin + in_frame <= gmii_rx_dv; + end else if (gmii_rx_dv && gmii_rxd == ETH_SFD) begin + in_frame <= 1'b1; + start_packet_int_reg <= 1'b1; + end + + gmii_rxd_d0 <= gmii_rxd; + gmii_rxd_d1 <= gmii_rxd_d0; + gmii_rxd_d2 <= gmii_rxd_d1; + gmii_rxd_d3 <= gmii_rxd_d2; + gmii_rxd_d4 <= gmii_rxd_d3; + + gmii_rx_dv_d0 <= gmii_rx_dv; + gmii_rx_dv_d1 <= gmii_rx_dv_d0 & gmii_rx_dv; + gmii_rx_dv_d2 <= gmii_rx_dv_d1 & gmii_rx_dv; + gmii_rx_dv_d3 <= gmii_rx_dv_d2 & gmii_rx_dv; + gmii_rx_dv_d4 <= gmii_rx_dv_d3 & gmii_rx_dv; + + gmii_rx_er_d0 <= gmii_rx_er; + gmii_rx_er_d1 <= gmii_rx_er_d0; + gmii_rx_er_d2 <= gmii_rx_er_d1; + gmii_rx_er_d3 <= gmii_rx_er_d2; + gmii_rx_er_d4 <= gmii_rx_er_d3; + end + end + + if (reset_crc) begin + crc_state <= '1; + end else if (update_crc) begin + crc_state <= crc_next; + end + + error_bad_frame_reg <= error_bad_frame_next; + error_bad_fcs_reg <= error_bad_fcs_next; + + if (rst) begin + state_reg <= STATE_IDLE; + + m_axis_rx_tvalid_reg <= 1'b0; + + start_packet_int_reg <= 1'b0; + start_packet_reg <= 1'b0; + error_bad_frame_reg <= 1'b0; + error_bad_fcs_reg <= 1'b0; + + in_frame <= 1'b0; + mii_odd <= 1'b0; + + gmii_rx_dv_d0 <= 1'b0; + gmii_rx_dv_d1 <= 1'b0; + gmii_rx_dv_d2 <= 1'b0; + gmii_rx_dv_d3 <= 1'b0; + gmii_rx_dv_d4 <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/tb/eth/taxi_axis_gmii_rx/Makefile b/tb/eth/taxi_axis_gmii_rx/Makefile new file mode 100644 index 0000000..fc1c7d2 --- /dev/null +++ b/tb/eth/taxi_axis_gmii_rx/Makefile @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = taxi_axis_gmii_rx +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv +VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv +VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_DATA_W := 8 +export PARAM_PTP_TS_EN := 1 +export PARAM_PTP_TS_W := 96 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/tb/eth/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.py b/tb/eth/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.py new file mode 100644 index 0000000..25c129c --- /dev/null +++ b/tb/eth/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.py @@ -0,0 +1,200 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os + +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotb.utils import get_time_from_sim_steps +from cocotb.regression import TestFactory + +from cocotbext.eth import GmiiFrame, GmiiSource, PtpClockSimTime +from cocotbext.axi import AxiStreamBus, AxiStreamSink + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + self._enable_generator = None + self._enable_cr = None + + cocotb.start_soon(Clock(dut.clk, 8, units="ns").start()) + + self.source = GmiiSource(dut.gmii_rxd, dut.gmii_rx_er, dut.gmii_rx_dv, + dut.clk, dut.rst, dut.clk_enable, dut.mii_select) + self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.clk, dut.rst) + + self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk) + + dut.clk_enable.setimmediatevalue(1) + dut.mii_select.setimmediatevalue(0) + dut.cfg_rx_enable.setimmediatevalue(0) + + async def reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + def set_enable_generator(self, generator=None): + if self._enable_cr is not None: + self._enable_cr.kill() + self._enable_cr = None + + self._enable_generator = generator + + if self._enable_generator is not None: + self._enable_cr = cocotb.start_soon(self._run_enable()) + + def clear_enable_generator(self): + self.set_enable_generator(None) + + async def _run_enable(self): + for val in self._enable_generator: + self.dut.clk_enable.value = val + await RisingEdge(self.dut.clk) + + +async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None, mii_sel=False): + + tb = TB(dut) + + tb.source.ifg = ifg + tb.dut.mii_select.value = mii_sel + tb.dut.cfg_rx_enable.value = 1 + + if enable_gen is not None: + tb.set_enable_generator(enable_gen()) + + await tb.reset() + + test_frames = [payload_data(x) for x in payload_lengths()] + tx_frames = [] + + for test_data in test_frames: + test_frame = GmiiFrame.from_payload(test_data, tx_complete=tx_frames.append) + await tb.source.send(test_frame) + + for test_data in test_frames: + rx_frame = await tb.sink.recv() + tx_frame = tx_frames.pop(0) + + frame_error = rx_frame.tuser & 1 + ptp_ts = rx_frame.tuser >> 1 + ptp_ts_ns = ptp_ts / 2**16 + + tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns") + + tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns) + tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns)) + + assert rx_frame.tdata == test_data + assert frame_error == 0 + assert abs(ptp_ts_ns - tx_frame_sfd_ns - (32 if enable_gen else 8)) < 0.01 + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def size_list(): + return list(range(60, 128)) + [512, 1514] + [60]*10 + + +def incrementing_payload(length): + return bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + +def cycle_en(): + return itertools.cycle([0, 0, 0, 1]) + + +if cocotb.SIM_NAME: + + factory = TestFactory(run_test) + factory.add_option("payload_lengths", [size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("ifg", [12, 0]) + factory.add_option("enable_gen", [None, cycle_en]) + factory.add_option("mii_sel", [False, True]) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +def test_axis_gmii_rx(request): + dut = "taxi_axis_gmii_rx" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, "eth", f"{dut}.sv"), + os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"), + os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['DATA_W'] = 8 + parameters['PTP_TS_EN'] = 1 + parameters['PTP_TS_W'] = 96 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/tb/eth/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.sv b/tb/eth/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.sv new file mode 100644 index 0000000..1eedcd8 --- /dev/null +++ b/tb/eth/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.sv @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4-Stream GMII frame receiver testbench + */ +module test_taxi_axis_gmii_rx # +( + /* verilator lint_off WIDTHTRUNC */ + parameter DATA_W = 8, + parameter logic PTP_TS_EN = 1'b0, + parameter PTP_TS_W = 96 + /* verilator lint_on WIDTHTRUNC */ +) +(); + +localparam USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1; + +logic clk; +logic rst; + +logic [DATA_W-1:0] gmii_rxd; +logic gmii_rx_dv; +logic gmii_rx_er; + +taxi_axis_if #(.DATA_W(DATA_W), .USER_W(USER_W)) m_axis_rx(); + +logic [PTP_TS_W-1:0] ptp_ts; + +logic clk_enable; +logic mii_select; + +logic cfg_rx_enable; + +logic start_packet; +logic error_bad_frame; +logic error_bad_fcs; + +taxi_axis_gmii_rx #( + .DATA_W(DATA_W), + .PTP_TS_EN(PTP_TS_EN), + .PTP_TS_W(PTP_TS_W) +) +uut ( + .clk(clk), + .rst(rst), + + /* + * GMII input + */ + .gmii_rxd(gmii_rxd), + .gmii_rx_dv(gmii_rx_dv), + .gmii_rx_er(gmii_rx_er), + + /* + * AXI4-Stream output (source) + */ + .m_axis_rx(m_axis_rx), + + /* + * PTP + */ + .ptp_ts(ptp_ts), + + /* + * Control + */ + .clk_enable(clk_enable), + .mii_select(mii_select), + + /* + * Configuration + */ + .cfg_rx_enable(cfg_rx_enable), + + /* + * Status + */ + .start_packet(start_packet), + .error_bad_frame(error_bad_frame), + .error_bad_fcs(error_bad_fcs) +); + +endmodule + +`resetall