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eth: Add AXI stream GMII Ethernet frame receiver module and testbench

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-07 16:12:58 -08:00
parent 6da97807a7
commit 3f501aaac9
4 changed files with 699 additions and 0 deletions
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rtl/eth/taxi_axis_gmii_rx.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2015-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream GMII frame receiver (GMII in, AXI out)
*/
module taxi_axis_gmii_rx #
(
parameter DATA_W = 8,
parameter logic PTP_TS_EN = 1'b0,
parameter PTP_TS_W = 96
)
(
input wire logic clk,
input wire logic rst,
/*
* GMII input
*/
input wire logic [DATA_W-1:0] gmii_rxd,
input wire logic gmii_rx_dv,
input wire logic gmii_rx_er,
/*
* Receive interface (AXI stream)
*/
taxi_axis_if.src m_axis_rx,
/*
* PTP
*/
input wire logic [PTP_TS_W-1:0] ptp_ts,
/*
* Control
*/
input wire logic clk_enable,
input wire logic mii_select,
/*
* Configuration
*/
input wire logic cfg_rx_enable,
/*
* Status
*/
output wire logic start_packet,
output wire logic error_bad_frame,
output wire logic error_bad_fcs
);
localparam USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
// check configuration
if (DATA_W != 8)
$fatal(0, "Error: Interface width must be 8 (instance %m)");
if (m_axis_rx.DATA_W != DATA_W)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
if (m_axis_rx.USER_W != USER_W)
$fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)");
localparam [7:0]
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_PAYLOAD = 3'd1,
STATE_WAIT_LAST = 3'd2;
logic [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
logic reset_crc;
logic update_crc;
logic mii_odd = 1'b0;
logic in_frame = 1'b0;
logic [DATA_W-1:0] gmii_rxd_d0 = '0;
logic [DATA_W-1:0] gmii_rxd_d1 = '0;
logic [DATA_W-1:0] gmii_rxd_d2 = '0;
logic [DATA_W-1:0] gmii_rxd_d3 = '0;
logic [DATA_W-1:0] gmii_rxd_d4 = '0;
logic gmii_rx_dv_d0 = 1'b0;
logic gmii_rx_dv_d1 = 1'b0;
logic gmii_rx_dv_d2 = 1'b0;
logic gmii_rx_dv_d3 = 1'b0;
logic gmii_rx_dv_d4 = 1'b0;
logic gmii_rx_er_d0 = 1'b0;
logic gmii_rx_er_d1 = 1'b0;
logic gmii_rx_er_d2 = 1'b0;
logic gmii_rx_er_d3 = 1'b0;
logic gmii_rx_er_d4 = 1'b0;
logic [DATA_W-1:0] m_axis_rx_tdata_reg = '0, m_axis_rx_tdata_next;
logic m_axis_rx_tvalid_reg = 1'b0, m_axis_rx_tvalid_next;
logic m_axis_rx_tlast_reg = 1'b0, m_axis_rx_tlast_next;
logic m_axis_rx_tuser_reg = 1'b0, m_axis_rx_tuser_next;
logic start_packet_int_reg = 1'b0;
logic start_packet_reg = 1'b0;
logic error_bad_frame_reg = 1'b0, error_bad_frame_next;
logic error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0;
logic [31:0] crc_state = '1;
wire [31:0] crc_next;
assign m_axis_rx.tdata = m_axis_rx_tdata_reg;
assign m_axis_rx.tkeep = 1'b1;
assign m_axis_rx.tstrb = m_axis_rx.tkeep;
assign m_axis_rx.tvalid = m_axis_rx_tvalid_reg;
assign m_axis_rx.tlast = m_axis_rx_tlast_reg;
assign m_axis_rx.tid = '0;
assign m_axis_rx.tdest = '0;
assign m_axis_rx.tuser[0] = m_axis_rx_tuser_reg;
if (PTP_TS_EN) begin
assign m_axis_rx.tuser[1 +: PTP_TS_W] = ptp_ts_out_reg;
end
assign start_packet = start_packet_reg;
assign error_bad_frame = error_bad_frame_reg;
assign error_bad_fcs = error_bad_fcs_reg;
taxi_lfsr #(
.LFSR_W(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_GALOIS(1),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_W(8)
)
eth_crc_8 (
.data_in(gmii_rxd_d4),
.state_in(crc_state),
.data_out(),
.state_out(crc_next)
);
always_comb begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
m_axis_rx_tdata_next = '0;
m_axis_rx_tvalid_next = 1'b0;
m_axis_rx_tlast_next = 1'b0;
m_axis_rx_tuser_next = 1'b0;
error_bad_frame_next = 1'b0;
error_bad_fcs_next = 1'b0;
if (!clk_enable) begin
// clock disabled - hold state
state_next = state_reg;
end else if (mii_select && !mii_odd) begin
// MII even cycle - hold state
state_next = state_reg;
end else begin
case (state_reg)
STATE_IDLE: begin
// idle state - wait for packet
reset_crc = 1'b1;
if (gmii_rx_dv_d4 && !gmii_rx_er_d4 && gmii_rxd_d4 == ETH_SFD && cfg_rx_enable) begin
state_next = STATE_PAYLOAD;
end else begin
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// read payload
update_crc = 1'b1;
m_axis_rx_tdata_next = gmii_rxd_d4;
m_axis_rx_tvalid_next = 1'b1;
if (gmii_rx_dv_d4 && gmii_rx_er_d4) begin
// error
m_axis_rx_tlast_next = 1'b1;
m_axis_rx_tuser_next = 1'b1;
error_bad_frame_next = 1'b1;
state_next = STATE_WAIT_LAST;
end else if (!gmii_rx_dv) begin
// end of packet
m_axis_rx_tlast_next = 1'b1;
if (gmii_rx_er_d0 || gmii_rx_er_d1 || gmii_rx_er_d2 || gmii_rx_er_d3) begin
// error received in FCS bytes
m_axis_rx_tuser_next = 1'b1;
error_bad_frame_next = 1'b1;
end else if ({gmii_rxd_d0, gmii_rxd_d1, gmii_rxd_d2, gmii_rxd_d3} == ~crc_next) begin
// FCS good
m_axis_rx_tuser_next = 1'b0;
end else begin
// FCS bad
m_axis_rx_tuser_next = 1'b1;
error_bad_frame_next = 1'b1;
error_bad_fcs_next = 1'b1;
end
state_next = STATE_IDLE;
end else begin
state_next = STATE_PAYLOAD;
end
end
STATE_WAIT_LAST: begin
// wait for end of packet
if (~gmii_rx_dv) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end
default: begin
// invalid state, return to idle
state_next = STATE_IDLE;
end
endcase
end
end
always_ff @(posedge clk) begin
state_reg <= state_next;
m_axis_rx_tdata_reg <= m_axis_rx_tdata_next;
m_axis_rx_tvalid_reg <= m_axis_rx_tvalid_next;
m_axis_rx_tlast_reg <= m_axis_rx_tlast_next;
m_axis_rx_tuser_reg <= m_axis_rx_tuser_next;
start_packet_int_reg <= 1'b0;
start_packet_reg <= 1'b0;
if (start_packet_int_reg) begin
ptp_ts_out_reg <= ptp_ts;
start_packet_reg <= 1'b1;
end
if (clk_enable) begin
if (mii_select) begin
mii_odd <= !mii_odd;
if (in_frame) begin
in_frame <= gmii_rx_dv;
end else if (gmii_rx_dv && {gmii_rxd[3:0], gmii_rxd_d0[7:4]} == ETH_SFD) begin
in_frame <= 1'b1;
start_packet_int_reg <= 1'b1;
mii_odd <= 1'b1;
end
gmii_rxd_d0 <= {gmii_rxd[3:0], gmii_rxd_d0[7:4]};
if (mii_odd) begin
gmii_rxd_d1 <= gmii_rxd_d0;
gmii_rxd_d2 <= gmii_rxd_d1;
gmii_rxd_d3 <= gmii_rxd_d2;
gmii_rxd_d4 <= gmii_rxd_d3;
gmii_rx_dv_d0 <= gmii_rx_dv & gmii_rx_dv_d0;
gmii_rx_dv_d1 <= gmii_rx_dv_d0 & gmii_rx_dv;
gmii_rx_dv_d2 <= gmii_rx_dv_d1 & gmii_rx_dv;
gmii_rx_dv_d3 <= gmii_rx_dv_d2 & gmii_rx_dv;
gmii_rx_dv_d4 <= gmii_rx_dv_d3 & gmii_rx_dv;
gmii_rx_er_d0 <= gmii_rx_er | gmii_rx_er_d0;
gmii_rx_er_d1 <= gmii_rx_er_d0;
gmii_rx_er_d2 <= gmii_rx_er_d1;
gmii_rx_er_d3 <= gmii_rx_er_d2;
gmii_rx_er_d4 <= gmii_rx_er_d3;
end else begin
gmii_rx_dv_d0 <= gmii_rx_dv;
gmii_rx_er_d0 <= gmii_rx_er;
end
end else begin
if (in_frame) begin
in_frame <= gmii_rx_dv;
end else if (gmii_rx_dv && gmii_rxd == ETH_SFD) begin
in_frame <= 1'b1;
start_packet_int_reg <= 1'b1;
end
gmii_rxd_d0 <= gmii_rxd;
gmii_rxd_d1 <= gmii_rxd_d0;
gmii_rxd_d2 <= gmii_rxd_d1;
gmii_rxd_d3 <= gmii_rxd_d2;
gmii_rxd_d4 <= gmii_rxd_d3;
gmii_rx_dv_d0 <= gmii_rx_dv;
gmii_rx_dv_d1 <= gmii_rx_dv_d0 & gmii_rx_dv;
gmii_rx_dv_d2 <= gmii_rx_dv_d1 & gmii_rx_dv;
gmii_rx_dv_d3 <= gmii_rx_dv_d2 & gmii_rx_dv;
gmii_rx_dv_d4 <= gmii_rx_dv_d3 & gmii_rx_dv;
gmii_rx_er_d0 <= gmii_rx_er;
gmii_rx_er_d1 <= gmii_rx_er_d0;
gmii_rx_er_d2 <= gmii_rx_er_d1;
gmii_rx_er_d3 <= gmii_rx_er_d2;
gmii_rx_er_d4 <= gmii_rx_er_d3;
end
end
if (reset_crc) begin
crc_state <= '1;
end else if (update_crc) begin
crc_state <= crc_next;
end
error_bad_frame_reg <= error_bad_frame_next;
error_bad_fcs_reg <= error_bad_fcs_next;
if (rst) begin
state_reg <= STATE_IDLE;
m_axis_rx_tvalid_reg <= 1'b0;
start_packet_int_reg <= 1'b0;
start_packet_reg <= 1'b0;
error_bad_frame_reg <= 1'b0;
error_bad_fcs_reg <= 1'b0;
in_frame <= 1'b0;
mii_odd <= 1'b0;
gmii_rx_dv_d0 <= 1'b0;
gmii_rx_dv_d1 <= 1'b0;
gmii_rx_dv_d2 <= 1'b0;
gmii_rx_dv_d3 <= 1'b0;
gmii_rx_dv_d4 <= 1'b0;
end
end
endmodule
`resetall