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cndm: Add missing testbench connections

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-02-24 17:49:26 -08:00
parent 37393ca112
commit 3fc54f0384
4 changed files with 12 additions and 12 deletions
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6
src/cndm/board/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -160,8 +160,8 @@ class TB:
# cfg_phy_link_status # cfg_phy_link_status
# cfg_negotiated_width # cfg_negotiated_width
# cfg_current_speed # cfg_current_speed
# cfg_max_payload=dut.cfg_max_payload, cfg_max_payload=dut.cfg_max_payload,
# cfg_max_read_req=dut.cfg_max_read_req, cfg_max_read_req=dut.cfg_max_read_req,
# cfg_function_status # cfg_function_status
# cfg_vf_status # cfg_vf_status
# cfg_function_power_state # cfg_function_power_state
@@ -175,7 +175,7 @@ class TB:
# cfg_rx_pm_state # cfg_rx_pm_state
# cfg_tx_pm_state # cfg_tx_pm_state
# cfg_ltssm_state # cfg_ltssm_state
# cfg_rcb_status=dut.cfg_rcb_status, cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable # cfg_obff_enable
# cfg_pl_status_change # cfg_pl_status_change
# cfg_tph_requester_enable # cfg_tph_requester_enable

6
src/cndm/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -160,8 +160,8 @@ class TB:
# cfg_phy_link_status # cfg_phy_link_status
# cfg_negotiated_width # cfg_negotiated_width
# cfg_current_speed # cfg_current_speed
# cfg_max_payload=dut.cfg_max_payload, cfg_max_payload=dut.cfg_max_payload,
# cfg_max_read_req=dut.cfg_max_read_req, cfg_max_read_req=dut.cfg_max_read_req,
# cfg_function_status # cfg_function_status
# cfg_vf_status # cfg_vf_status
# cfg_function_power_state # cfg_function_power_state
@@ -175,7 +175,7 @@ class TB:
# cfg_rx_pm_state # cfg_rx_pm_state
# cfg_tx_pm_state # cfg_tx_pm_state
# cfg_ltssm_state # cfg_ltssm_state
# cfg_rcb_status=dut.cfg_rcb_status, cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable # cfg_obff_enable
# cfg_pl_status_change # cfg_pl_status_change
# cfg_tph_requester_enable # cfg_tph_requester_enable

6
src/cndm/board/Alveo/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -161,8 +161,8 @@ class TB:
# cfg_phy_link_status # cfg_phy_link_status
# cfg_negotiated_width # cfg_negotiated_width
# cfg_current_speed # cfg_current_speed
# cfg_max_payload=dut.cfg_max_payload, cfg_max_payload=dut.cfg_max_payload,
# cfg_max_read_req=dut.cfg_max_read_req, cfg_max_read_req=dut.cfg_max_read_req,
# cfg_function_status # cfg_function_status
# cfg_vf_status # cfg_vf_status
# cfg_function_power_state # cfg_function_power_state
@@ -176,7 +176,7 @@ class TB:
# cfg_rx_pm_state # cfg_rx_pm_state
# cfg_tx_pm_state # cfg_tx_pm_state
# cfg_ltssm_state # cfg_ltssm_state
# cfg_rcb_status=dut.cfg_rcb_status, cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable # cfg_obff_enable
# cfg_pl_status_change # cfg_pl_status_change
# cfg_tph_requester_enable # cfg_tph_requester_enable

6
src/cndm/board/RK_XCKU5P_F/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -160,8 +160,8 @@ class TB:
# cfg_phy_link_status # cfg_phy_link_status
# cfg_negotiated_width # cfg_negotiated_width
# cfg_current_speed # cfg_current_speed
# cfg_max_payload=dut.cfg_max_payload, cfg_max_payload=dut.cfg_max_payload,
# cfg_max_read_req=dut.cfg_max_read_req, cfg_max_read_req=dut.cfg_max_read_req,
# cfg_function_status # cfg_function_status
# cfg_vf_status # cfg_vf_status
# cfg_function_power_state # cfg_function_power_state
@@ -175,7 +175,7 @@ class TB:
# cfg_rx_pm_state # cfg_rx_pm_state
# cfg_tx_pm_state # cfg_tx_pm_state
# cfg_ltssm_state # cfg_ltssm_state
# cfg_rcb_status=dut.cfg_rcb_status, cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable # cfg_obff_enable
# cfg_pl_status_change # cfg_pl_status_change
# cfg_tph_requester_enable # cfg_tph_requester_enable