From 3fcb32f2323ce2d24cf872a3a660dbdf51d52fa7 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 31 Dec 2025 17:40:42 -0800 Subject: [PATCH] cndm_proto: Add corundum-proto design for AS02MC04 Signed-off-by: Alex Forencich --- src/cndm_proto/board/AS02MC04/fpga/README.md | 32 + .../board/AS02MC04/fpga/common/vivado.mk | 153 +++++ src/cndm_proto/board/AS02MC04/fpga/fpga.xdc | 141 +++++ .../board/AS02MC04/fpga/fpga/Makefile | 89 +++ .../board/AS02MC04/fpga/fpga/config.tcl | 22 + .../board/AS02MC04/fpga/fpga_10g/Makefile | 89 +++ .../board/AS02MC04/fpga/fpga_10g/config.tcl | 22 + .../AS02MC04/fpga/ip/pcie4_uscale_plus_0.tcl | 28 + src/cndm_proto/board/AS02MC04/fpga/lib/taxi | 1 + .../board/AS02MC04/fpga/rtl/fpga.sv | 598 ++++++++++++++++++ .../board/AS02MC04/fpga/rtl/fpga_core.sv | 515 +++++++++++++++ .../board/AS02MC04/fpga/tb/fpga_core/Makefile | 61 ++ .../board/AS02MC04/fpga/tb/fpga_core/baser.py | 1 + .../AS02MC04/fpga/tb/fpga_core/cndm_proto.py | 1 + .../fpga/tb/fpga_core/test_fpga_core.py | 508 +++++++++++++++ .../fpga/tb/fpga_core/test_fpga_core.sv | 232 +++++++ 16 files changed, 2493 insertions(+) create mode 100644 src/cndm_proto/board/AS02MC04/fpga/README.md create mode 100644 src/cndm_proto/board/AS02MC04/fpga/common/vivado.mk create mode 100644 src/cndm_proto/board/AS02MC04/fpga/fpga.xdc create mode 100644 src/cndm_proto/board/AS02MC04/fpga/fpga/Makefile create mode 100644 src/cndm_proto/board/AS02MC04/fpga/fpga/config.tcl create mode 100644 src/cndm_proto/board/AS02MC04/fpga/fpga_10g/Makefile create mode 100644 src/cndm_proto/board/AS02MC04/fpga/fpga_10g/config.tcl create mode 100644 src/cndm_proto/board/AS02MC04/fpga/ip/pcie4_uscale_plus_0.tcl create mode 120000 src/cndm_proto/board/AS02MC04/fpga/lib/taxi create mode 100644 src/cndm_proto/board/AS02MC04/fpga/rtl/fpga.sv create mode 100644 src/cndm_proto/board/AS02MC04/fpga/rtl/fpga_core.sv create mode 100644 src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/Makefile create mode 120000 src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/baser.py create mode 120000 src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/cndm_proto.py create mode 100644 src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.py create mode 100644 src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.sv diff --git a/src/cndm_proto/board/AS02MC04/fpga/README.md b/src/cndm_proto/board/AS02MC04/fpga/README.md new file mode 100644 index 0000000..3cb73f7 --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/README.md @@ -0,0 +1,32 @@ +# Corundum-proto for Alibaba AS02MC04 + +## Introduction + +This design targets the Alibaba AS02MC04 FPGA board. + +* SFP+ cages + * Looped-back 10GBASE-R or 25GBASE-R MAC via GTY transceiver + +## Board details + +* FPGA: xcku3p-ffvb676-1-e +* PCIe: gen 3 x8 (~64 Gbps) +* Reference oscillator: Fixed 156.25 MHz +* 25GBASE-R PHY: Soft PCS with GTY transceiver + +## Licensing + +* Toolchain + * Vivado Standard (enterprise license not required) +* IP + * No licensed vendor IP or 3rd party IP + +## How to build + +Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. + +On the host system, run `make` in `modules/cndm_proto` to build the driver. Ensure that the headers for the running kernel are installed, otherwise the driver cannot be compiled. + +## How to test + +Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod cndm_proto.ko`. Check `dmesg` for output from driver initialization. Run `cndm_proto_ddcmd.sh =p` to enable all debug messages. diff --git a/src/cndm_proto/board/AS02MC04/fpga/common/vivado.mk b/src/cndm_proto/board/AS02MC04/fpga/common/vivado.mk new file mode 100644 index 0000000..07c56e2 --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/common/vivado.mk @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: MIT +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016-2025 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - list of source files +# INC_FILES - list of include files +# XDC_FILES - list of timing constraint files +# XCI_FILES - list of IP XCI files +# IP_TCL_FILES - list of IP TCL files (sourced during project creation) +# CONFIG_TCL_FILES - list of config TCL files (sourced before each build) +# +# Note: both SYN_FILES and INC_FILES support file list files. File list +# files are files with a .f extension that contain a list of additional +# files to include, one path relative to the .f file location per line. +# The .f files are processed recursively, and then the complete file list +# is de-duplicated, with later files in the list taking precedence. +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include $(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) +XDC_FILES ?= $(PROJECT).xdc + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES))) +INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES))) + +################################################################### +# Main Targets +# +# all: build everything (fpga) +# fpga: build FPGA config +# vivado: open project in Vivado +# tmpclean: remove intermediate files +# clean: remove output files and project files +# distclean: remove archived output files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file + +# create fresh project if Makefile or IP files have changed +create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@ + for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done + +# source config TCL scripts if any source file has changed +update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# output files (including potentially bit, bin, ltx, and xsa) +$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \ + if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi diff --git a/src/cndm_proto/board/AS02MC04/fpga/fpga.xdc b/src/cndm_proto/board/AS02MC04/fpga/fpga.xdc new file mode 100644 index 0000000..f36d4c7 --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/fpga.xdc @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# XDC constraints for the Alibaba AS02MC04 +# part: xcku3p-ffvb676-1-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 72.9 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +# 100 MHz system clock (Y2) +set_property -dict {LOC E18 IOSTANDARD LVDS} [get_ports {clk_100mhz_p}] +set_property -dict {LOC D18 IOSTANDARD LVDS} [get_ports {clk_100mhz_n}] +create_clock -period 10 -name clk_100mhz [get_ports {clk_100mhz_p}] + +# LEDs +set_property -dict {LOC B12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0]}] ;# DS3 +set_property -dict {LOC C12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1]}] ;# DS2 +set_property -dict {LOC B11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[0]}] ;# DS6 +set_property -dict {LOC C11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[1]}] ;# DS7 +set_property -dict {LOC A10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[2]}] ;# DS8 +set_property -dict {LOC B10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[3]}] ;# DS9 +set_property -dict {LOC A13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led_r}] ;# C1 +set_property -dict {LOC A12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led_g}] ;# C1 +set_property -dict {LOC B9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led_hb}] ;# DS5 + +set_false_path -to [get_ports {sfp_led[*] led[*] led_r led_g led_hb}] +set_output_delay 0 [get_ports {sfp_led[*] led[*] led_r led_g led_hb}] + +# Reset button +set_property -dict {LOC F12 IOSTANDARD LVCMOS33} [get_ports reset] ;# SW1 + +set_false_path -from [get_ports {reset}] +set_input_delay 0 [get_ports {reset}] + +# GPIO +#set_property -dict {LOC A14 IOSTANDARD LVCMOS33} [get_ports {gpio[0]}] ;# J5.3,4 +#set_property -dict {LOC E12 IOSTANDARD LVCMOS33} [get_ports {gpio[1]}] ;# J5.5,6 +#set_property -dict {LOC E13 IOSTANDARD LVCMOS33} [get_ports {gpio[2]}] ;# J5.7,8 +#set_property -dict {LOC F10 IOSTANDARD LVCMOS33} [get_ports {gpio[3]}] ;# J5.9,10 +#set_property -dict {LOC C9 IOSTANDARD LVCMOS33} [get_ports {gpio[4]}] ;# J5.11,12 +#set_property -dict {LOC D9 IOSTANDARD LVCMOS33} [get_ports {gpio[5]}] ;# J5.13,14 + +# SFP28 Interfaces +set_property -dict {LOC A4 } [get_ports {sfp_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC A3 } [get_ports {sfp_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC B2 } [get_ports {sfp_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC B1 } [get_ports {sfp_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC B7 } [get_ports {sfp_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC B6 } [get_ports {sfp_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC D7 } [get_ports {sfp_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC D6 } [get_ports {sfp_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC K7 } [get_ports {sfp_mgt_refclk_p}] ;# MGTREFCLK0P_227 from Y1 +set_property -dict {LOC K6 } [get_ports {sfp_mgt_refclk_n}] ;# MGTREFCLK0N_227 from Y1 +set_property -dict {LOC D14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {sfp_npres[0]}] +set_property -dict {LOC E11 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {sfp_npres[1]}] +set_property -dict {LOC B14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {sfp_tx_fault[0]}] +set_property -dict {LOC F9 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {sfp_tx_fault[1]}] +set_property -dict {LOC D13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {sfp_los[0]}] +set_property -dict {LOC E10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {sfp_los[1]}] +#set_property -dict {LOC C13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_scl[0]}] +#set_property -dict {LOC D10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_scl[1]}] +#set_property -dict {LOC C14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[0]}] +#set_property -dict {LOC D11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[1]}] + +# 156.25 MHz MGT reference clock +create_clock -period 6.4 -name sfp_mgt_refclk [get_ports {sfp_mgt_refclk_p}] + +set_false_path -from [get_ports {sfp_npres[*] sfp_tx_fault[*] sfp_los[*]}] +set_input_delay 0 [get_ports {sfp_npres[*] sfp_tx_fault[*] sfp_los[*]}] + +#set_false_path -to [get_ports {sfp_i2c_sda[*] sfp_i2c_scl[*]}] +#set_output_delay 0 [get_ports {sfp_i2c_sda[*] sfp_i2c_scl[*]}] +#set_false_path -from [get_ports {sfp_i2c_sda[*] sfp_i2c_scl[*]}] +#set_input_delay 0 [get_ports {sfp_i2c_sda[*] sfp_i2c_scl[*]}] + +# I2C interface +#set_property -dict {LOC G9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {i2c_scl[0]}] +#set_property -dict {LOC G10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {i2c_sda[0]}] +#set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {i2c_scl[1]}] +#set_property -dict {LOC J15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {i2c_sda[1]}] + +#set_false_path -to [get_ports {i2c_sda[*] i2c_scl[*]}] +#set_output_delay 0 [get_ports {i2c_sda[*] i2c_scl[*]}] +#set_false_path -from [get_ports {i2c_sda[*] i2c_scl[*]}] +#set_input_delay 0 [get_ports {i2c_sda[*] i2c_scl[*]}] + +# PCIe Interface +set_property -dict {LOC P2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC P1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC R5 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC R4 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC T2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC T1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC U5 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC U4 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC V2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC V1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC W5 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC W4 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC Y2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC Y1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AA5 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AA4 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC AC5 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC AC4 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC AE9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC AE8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 +set_property -dict {LOC T7 } [get_ports pcie_refclk_p] ;# MGTREFCLK1P_225 +set_property -dict {LOC T6 } [get_ports pcie_refclk_n] ;# MGTREFCLK1N_225 +set_property -dict {LOC A9 IOSTANDARD LVCMOS33 PULLUP true} [get_ports pcie_reset_n] + +set_false_path -from [get_ports {pcie_reset_n}] +set_input_delay 0 [get_ports {pcie_reset_n}] + +# 100 MHz MGT reference clock +create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p] diff --git a/src/cndm_proto/board/AS02MC04/fpga/fpga/Makefile b/src/cndm_proto/board/AS02MC04/fpga/fpga/Makefile new file mode 100644 index 0000000..745bec1 --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/fpga/Makefile @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcku3p-ffvb676-1-e +FPGA_TOP = fpga +FPGA_ARCH = kintexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/cndm_proto/rtl/cndm_proto_pcie_us.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl +IP_TCL_FILES += ../ip/pcie4_uscale_plus_0.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(PROJECT).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit + echo "write_cfgmem -force -format mcs -size 32 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(PROJECT).mcs $(PROJECT).prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu256-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/cndm_proto/board/AS02MC04/fpga/fpga/config.tcl b/src/cndm_proto/board/AS02MC04/fpga/fpga/config.tcl new file mode 100644 index 0000000..d3508a4 --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/fpga/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/cndm_proto/board/AS02MC04/fpga/fpga_10g/Makefile b/src/cndm_proto/board/AS02MC04/fpga/fpga_10g/Makefile new file mode 100644 index 0000000..0d9141c --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/fpga_10g/Makefile @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcku3p-ffvb676-1-e +FPGA_TOP = fpga +FPGA_ARCH = kintexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/cndm_proto/rtl/cndm_proto_pcie_us.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl +IP_TCL_FILES += ../ip/pcie4_uscale_plus_0.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(PROJECT).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit + echo "write_cfgmem -force -format mcs -size 32 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(PROJECT).mcs $(PROJECT).prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu256-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/cndm_proto/board/AS02MC04/fpga/fpga_10g/config.tcl b/src/cndm_proto/board/AS02MC04/fpga/fpga_10g/config.tcl new file mode 100644 index 0000000..cd72d45 --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/fpga_10g/config.tcl @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/cndm_proto/board/AS02MC04/fpga/ip/pcie4_uscale_plus_0.tcl b/src/cndm_proto/board/AS02MC04/fpga/ip/pcie4_uscale_plus_0.tcl new file mode 100644 index 0000000..4acd55c --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/ip/pcie4_uscale_plus_0.tcl @@ -0,0 +1,28 @@ + +create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 + +set_property -dict [list \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ + CONFIG.AXISTEN_IF_RC_STRADDLE {false} \ + CONFIG.axisten_if_enable_client_tag {true} \ + CONFIG.axisten_if_width {256_bit} \ + CONFIG.extended_tag_field {true} \ + CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ + CONFIG.axisten_freq {250} \ + CONFIG.PF0_CLASS_CODE {058000} \ + CONFIG.PF0_DEVICE_ID {C070} \ + CONFIG.PF0_SUBSYSTEM_ID {0009} \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1ded} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ + CONFIG.pf0_bar0_scale {Megabytes} \ + CONFIG.pf0_bar0_size {16} \ + CONFIG.pf0_msi_enabled {true} \ + CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ + CONFIG.en_msi_per_vec_masking {true} \ + CONFIG.vendor_id {1234} \ + CONFIG.mode_selection {Advanced} \ + CONFIG.en_gt_selection {true} \ + CONFIG.select_quad {GTY_Quad_225} \ +] [get_ips pcie4_uscale_plus_0] diff --git a/src/cndm_proto/board/AS02MC04/fpga/lib/taxi b/src/cndm_proto/board/AS02MC04/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/src/cndm_proto/board/AS02MC04/fpga/rtl/fpga.sv b/src/cndm_proto/board/AS02MC04/fpga/rtl/fpga.sv new file mode 100644 index 0000000..c18d1e8 --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/rtl/fpga.sv @@ -0,0 +1,598 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2014-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga # +( + // simulation (set to avoid vendor primitives) + parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") + parameter string VENDOR = "XILINX", + // device family + parameter string FAMILY = "kintexuplus", + // 10G/25G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 +) +( + /* + * Clock: 100MHz LVDS + * Reset: Push button, active high + */ + input wire logic clk_100mhz_p, + input wire logic clk_100mhz_n, + input wire logic reset, + + /* + * GPIO + */ + output wire logic sfp_led[2], + output wire logic [3:0] led, + output wire logic led_r, + output wire logic led_g, + output wire logic led_hb, + + /* + * Ethernet: SFP+ + */ + input wire logic sfp_rx_p[2], + input wire logic sfp_rx_n[2], + output wire logic sfp_tx_p[2], + output wire logic sfp_tx_n[2], + input wire logic sfp_mgt_refclk_p, + input wire logic sfp_mgt_refclk_n, + input wire logic [1:0] sfp_npres, + input wire logic [1:0] sfp_tx_fault, + input wire logic [1:0] sfp_los, + + /* + * PCIe + */ + input wire logic [7:0] pcie_rx_p, + input wire logic [7:0] pcie_rx_n, + output wire logic [7:0] pcie_tx_p, + output wire logic [7:0] pcie_tx_n, + input wire logic pcie_refclk_p, + input wire logic pcie_refclk_n, + input wire logic pcie_reset_n +); + +// Clock and reset + +wire clk_100mhz_ibufg; + +// Internal 125 MHz clock +wire clk_125mhz_mmcm_out; +wire clk_125mhz_int; +wire rst_125mhz_int; + +wire mmcm_rst = !reset; +wire mmcm_locked; +wire mmcm_clkfb; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_100mhz_ibufg_inst ( + .O (clk_100mhz_ibufg), + .I (clk_100mhz_p), + .IB (clk_100mhz_n) +); + +// MMCM instance +MMCME4_BASE #( + // 100 MHz input + .CLKIN1_PERIOD(10.0), + .REF_JITTER1(0.010), + // 100 MHz input / 1 = 100 MHz PFD (range 10 MHz to 500 MHz) + .DIVCLK_DIVIDE(1), + // 100 MHz PFD * 10 = 1000 MHz VCO (range 800 MHz to 1600 MHz) + .CLKFBOUT_MULT_F(10), + .CLKFBOUT_PHASE(0), + // 1250 MHz / 8 = 125 MHz, 0 degrees + .CLKOUT0_DIVIDE_F(8), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + // Not used + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + // Not used + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + // Not used + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + // Not used + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT4_CASCADE("FALSE"), + // Not used + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + // Not used + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + + // optimized bandwidth + .BANDWIDTH("OPTIMIZED"), + // don't wait for lock during startup + .STARTUP_WAIT("FALSE") +) +clk_mmcm_inst ( + // 100 MHz input + .CLKIN1(clk_100mhz_ibufg), + // direct clkfb feeback + .CLKFBIN(mmcm_clkfb), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + // 125 MHz, 0 degrees + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + // Not used + .CLKOUT1(), + .CLKOUT1B(), + // Not used + .CLKOUT2(), + .CLKOUT2B(), + // Not used + .CLKOUT3(), + .CLKOUT3B(), + // Not used + .CLKOUT4(), + // Not used + .CLKOUT5(), + // Not used + .CLKOUT6(), + // reset input + .RST(mmcm_rst), + // don't power down + .PWRDWN(1'b0), + // locked output + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +taxi_sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +// PCIe +localparam AXIS_PCIE_DATA_W = 256; +localparam AXIS_PCIE_KEEP_W = (AXIS_PCIE_DATA_W/32); +localparam AXIS_PCIE_RC_USER_W = 75; +localparam AXIS_PCIE_RQ_USER_W = 62; +localparam AXIS_PCIE_CQ_USER_W = 85; +localparam AXIS_PCIE_CC_USER_W = 33; +localparam RC_STRADDLE = 1'b0; // AXIS_PCIE_DATA_W >= 256; + +localparam RQ_SEQ_NUM_W = AXIS_PCIE_RQ_USER_W == 60 ? 4 : 6; +localparam RQ_SEQ_NUM_EN = 1; + +localparam PCIE_TAG_CNT = 64; +localparam BAR0_APERTURE = 24; + +logic pcie_user_clk; +logic pcie_user_rst; + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_CQ_USER_W) +) axis_pcie_cq(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_CC_USER_W) +) axis_pcie_cc(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_RQ_USER_W) +) axis_pcie_rq(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_RC_USER_W) +) axis_pcie_rc(); + +wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0; +wire pcie_rq_seq_num_vld0; +wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1; +wire pcie_rq_seq_num_vld1; + +wire [2:0] cfg_max_payload; +wire [2:0] cfg_max_read_req; +wire [3:0] cfg_rcb_status; + +wire [9:0] cfg_mgmt_addr; +wire [7:0] cfg_mgmt_function_number; +wire cfg_mgmt_write; +wire [31:0] cfg_mgmt_write_data; +wire [3:0] cfg_mgmt_byte_enable; +wire cfg_mgmt_read; +wire [31:0] cfg_mgmt_read_data; +wire cfg_mgmt_read_write_done; + +wire [7:0] cfg_fc_ph; +wire [11:0] cfg_fc_pd; +wire [7:0] cfg_fc_nph; +wire [11:0] cfg_fc_npd; +wire [7:0] cfg_fc_cplh; +wire [11:0] cfg_fc_cpld; +wire [2:0] cfg_fc_sel; + +// wire [3:0] cfg_interrupt_msix_enable; +// wire [3:0] cfg_interrupt_msix_mask; +// wire [251:0] cfg_interrupt_msix_vf_enable; +// wire [251:0] cfg_interrupt_msix_vf_mask; +// wire [63:0] cfg_interrupt_msix_address; +// wire [31:0] cfg_interrupt_msix_data; +// wire cfg_interrupt_msix_int; +// wire [1:0] cfg_interrupt_msix_vec_pending; +// wire cfg_interrupt_msix_vec_pending_status; +// wire cfg_interrupt_msix_sent; +// wire cfg_interrupt_msix_fail; +// wire [7:0] cfg_interrupt_msi_function_number; + +wire [3:0] cfg_interrupt_msi_enable; +wire [11:0] cfg_interrupt_msi_mmenable; +wire cfg_interrupt_msi_mask_update; +wire [31:0] cfg_interrupt_msi_data; +wire [1:0] cfg_interrupt_msi_select; +wire [31:0] cfg_interrupt_msi_int; +wire [31:0] cfg_interrupt_msi_pending_status; +wire cfg_interrupt_msi_pending_status_data_enable; +wire [1:0] cfg_interrupt_msi_pending_status_function_num; +wire cfg_interrupt_msi_sent; +wire cfg_interrupt_msi_fail; +wire [2:0] cfg_interrupt_msi_attr; +wire cfg_interrupt_msi_tph_present; +wire [1:0] cfg_interrupt_msi_tph_type; +wire [7:0] cfg_interrupt_msi_tph_st_tag; +wire [7:0] cfg_interrupt_msi_function_number; + +wire stat_err_cor; +wire stat_err_uncor; + +wire pcie_sys_clk; +wire pcie_sys_clk_gt; + +IBUFDS_GTE4 #( + .REFCLK_HROW_CK_SEL(2'b00) +) +ibufds_gte4_pcie_refclk_inst ( + .I (pcie_refclk_p), + .IB (pcie_refclk_n), + .CEB (1'b0), + .O (pcie_sys_clk_gt), + .ODIV2 (pcie_sys_clk) +); + +pcie4_uscale_plus_0 +pcie4_uscale_plus_inst ( + .pci_exp_txn(pcie_tx_n), + .pci_exp_txp(pcie_tx_p), + .pci_exp_rxn(pcie_rx_n), + .pci_exp_rxp(pcie_rx_p), + .user_clk(pcie_user_clk), + .user_reset(pcie_user_rst), + .user_lnk_up(), + + .s_axis_rq_tdata(axis_pcie_rq.tdata), + .s_axis_rq_tkeep(axis_pcie_rq.tkeep), + .s_axis_rq_tlast(axis_pcie_rq.tlast), + .s_axis_rq_tready(axis_pcie_rq.tready), + .s_axis_rq_tuser(axis_pcie_rq.tuser), + .s_axis_rq_tvalid(axis_pcie_rq.tvalid), + + .m_axis_rc_tdata(axis_pcie_rc.tdata), + .m_axis_rc_tkeep(axis_pcie_rc.tkeep), + .m_axis_rc_tlast(axis_pcie_rc.tlast), + .m_axis_rc_tready(axis_pcie_rc.tready), + .m_axis_rc_tuser(axis_pcie_rc.tuser), + .m_axis_rc_tvalid(axis_pcie_rc.tvalid), + + .m_axis_cq_tdata(axis_pcie_cq.tdata), + .m_axis_cq_tkeep(axis_pcie_cq.tkeep), + .m_axis_cq_tlast(axis_pcie_cq.tlast), + .m_axis_cq_tready(axis_pcie_cq.tready), + .m_axis_cq_tuser(axis_pcie_cq.tuser), + .m_axis_cq_tvalid(axis_pcie_cq.tvalid), + + .s_axis_cc_tdata(axis_pcie_cc.tdata), + .s_axis_cc_tkeep(axis_pcie_cc.tkeep), + .s_axis_cc_tlast(axis_pcie_cc.tlast), + .s_axis_cc_tready(axis_pcie_cc.tready), + .s_axis_cc_tuser(axis_pcie_cc.tuser), + .s_axis_cc_tvalid(axis_pcie_cc.tvalid), + + .pcie_rq_seq_num0(pcie_rq_seq_num0), + .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), + .pcie_rq_seq_num1(pcie_rq_seq_num1), + .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), + .pcie_rq_tag0(), + .pcie_rq_tag1(), + .pcie_rq_tag_av(), + .pcie_rq_tag_vld0(), + .pcie_rq_tag_vld1(), + + .pcie_tfc_nph_av(), + .pcie_tfc_npd_av(), + + .pcie_cq_np_req(1'b1), + .pcie_cq_np_req_count(), + + .cfg_phy_link_down(), + .cfg_phy_link_status(), + .cfg_negotiated_width(), + .cfg_current_speed(), + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_function_status(), + .cfg_function_power_state(), + .cfg_vf_status(), + .cfg_vf_power_state(), + .cfg_link_power_state(), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + .cfg_mgmt_debug_access(1'b0), + + .cfg_err_cor_out(), + .cfg_err_nonfatal_out(), + .cfg_err_fatal_out(), + .cfg_local_error_valid(), + .cfg_local_error_out(), + .cfg_ltssm_state(), + .cfg_rx_pm_state(), + .cfg_tx_pm_state(), + .cfg_rcb_status(cfg_rcb_status), + .cfg_obff_enable(), + .cfg_pl_status_change(), + .cfg_tph_requester_enable(), + .cfg_tph_st_mode(), + .cfg_vf_tph_requester_enable(), + .cfg_vf_tph_st_mode(), + + .cfg_msg_received(), + .cfg_msg_received_data(), + .cfg_msg_received_type(), + .cfg_msg_transmit(1'b0), + .cfg_msg_transmit_type(3'd0), + .cfg_msg_transmit_data(32'd0), + .cfg_msg_transmit_done(), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_dsn(64'd0), + + .cfg_bus_number(), + + .cfg_power_state_change_ack(1'b1), + .cfg_power_state_change_interrupt(), + + .cfg_err_cor_in(stat_err_cor), + .cfg_err_uncor_in(stat_err_uncor), + .cfg_flr_in_process(), + .cfg_flr_done(4'd0), + .cfg_vf_flr_in_process(), + .cfg_vf_flr_func_num(8'd0), + .cfg_vf_flr_done(8'd0), + + .cfg_link_training_enable(1'b1), + + .cfg_interrupt_int(4'd0), + .cfg_interrupt_pending(4'd0), + .cfg_interrupt_sent(), + // .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + // .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + // .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + // .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + // .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + // .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + // .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + // .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), + // .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), + // .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent), + // .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail), + // .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .cfg_pm_aspm_l1_entry_reject(1'b0), + .cfg_pm_aspm_tx_l0s_entry_disable(1'b0), + + .cfg_hot_reset_out(), + + .cfg_config_space_enable(1'b1), + .cfg_req_pm_transition_l23_ready(1'b0), + .cfg_hot_reset_in(1'b0), + + .cfg_ds_port_number(8'd0), + .cfg_ds_bus_number(8'd0), + .cfg_ds_device_number(5'd0), + + .sys_clk(pcie_sys_clk), + .sys_clk_gt(pcie_sys_clk_gt), + .sys_reset(pcie_reset_n), + + .phy_rdy_out() +); + +fpga_core #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) +) +core_inst ( + /* + * Clock: 125 MHz + * Synchronous reset + */ + .clk_125mhz(clk_125mhz_int), + .rst_125mhz(rst_125mhz_int), + + /* + * GPIO + */ + .sfp_led(sfp_led), + .led(led), + .led_r(led_r), + .led_g(led_g), + .led_hb(led_hb), + + /* + * Ethernet: SFP+ + */ + .sfp_rx_p(sfp_rx_p), + .sfp_rx_n(sfp_rx_n), + .sfp_tx_p(sfp_tx_p), + .sfp_tx_n(sfp_tx_n), + .sfp_mgt_refclk_p(sfp_mgt_refclk_p), + .sfp_mgt_refclk_n(sfp_mgt_refclk_n), + .sfp_mgt_refclk_out(), + .sfp_npres(sfp_npres), + .sfp_tx_fault(sfp_tx_fault), + .sfp_los(sfp_los), + + /* + * PCIe + */ + .pcie_clk(pcie_user_clk), + .pcie_rst(pcie_user_rst), + .s_axis_pcie_cq(axis_pcie_cq), + .m_axis_pcie_cc(axis_pcie_cc), + .m_axis_pcie_rq(axis_pcie_rq), + .s_axis_pcie_rc(axis_pcie_rc), + + .pcie_rq_seq_num0(pcie_rq_seq_num0), + .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), + .pcie_rq_seq_num1(pcie_rq_seq_num1), + .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_rcb_status(cfg_rcb_status), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + // .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + // .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + // .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + // .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + // .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + // .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + // .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + // .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), + // .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), + // .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), + // .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), + // .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number) +); + +endmodule + +`resetall diff --git a/src/cndm_proto/board/AS02MC04/fpga/rtl/fpga_core.sv b/src/cndm_proto/board/AS02MC04/fpga/rtl/fpga_core.sv new file mode 100644 index 0000000..bdb38e7 --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/rtl/fpga_core.sv @@ -0,0 +1,515 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2014-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic + */ +module fpga_core # +( + // simulation (set to avoid vendor primitives) + parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") + parameter string VENDOR = "XILINX", + // device family + parameter string FAMILY = "kintexuplus", + parameter RQ_SEQ_NUM_W = 6, + // 10G/25G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 +) +( + /* + * Clock: 125MHz + * Synchronous reset + */ + input wire logic clk_125mhz, + input wire logic rst_125mhz, + + /* + * GPIO + */ + output wire logic sfp_led[2], + output wire logic [3:0] led, + output wire logic led_r, + output wire logic led_g, + output wire logic led_hb, + + /* + * Ethernet: SFP+ + */ + input wire logic sfp_rx_p[2], + input wire logic sfp_rx_n[2], + output wire logic sfp_tx_p[2], + output wire logic sfp_tx_n[2], + input wire logic sfp_mgt_refclk_p, + input wire logic sfp_mgt_refclk_n, + output wire logic sfp_mgt_refclk_out, + input wire logic [1:0] sfp_npres, + input wire logic [1:0] sfp_tx_fault, + input wire logic [1:0] sfp_los, + + /* + * PCIe + */ + input wire logic pcie_clk, + input wire logic pcie_rst, + taxi_axis_if.snk s_axis_pcie_cq, + taxi_axis_if.src m_axis_pcie_cc, + taxi_axis_if.src m_axis_pcie_rq, + taxi_axis_if.snk s_axis_pcie_rc, + + input wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0, + input wire pcie_rq_seq_num_vld0, + input wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1, + input wire pcie_rq_seq_num_vld1, + + input wire [2:0] cfg_max_payload, + input wire [2:0] cfg_max_read_req, + input wire [3:0] cfg_rcb_status, + + output wire [9:0] cfg_mgmt_addr, + output wire [7:0] cfg_mgmt_function_number, + output wire cfg_mgmt_write, + output wire [31:0] cfg_mgmt_write_data, + output wire [3:0] cfg_mgmt_byte_enable, + output wire cfg_mgmt_read, + output wire [31:0] cfg_mgmt_read_data, + input wire cfg_mgmt_read_write_done, + + input wire [7:0] cfg_fc_ph, + input wire [11:0] cfg_fc_pd, + input wire [7:0] cfg_fc_nph, + input wire [11:0] cfg_fc_npd, + input wire [7:0] cfg_fc_cplh, + input wire [11:0] cfg_fc_cpld, + output wire [2:0] cfg_fc_sel, + + input wire [3:0] cfg_interrupt_msi_enable, + input wire [11:0] cfg_interrupt_msi_mmenable, + input wire cfg_interrupt_msi_mask_update, + input wire [31:0] cfg_interrupt_msi_data, + output wire [1:0] cfg_interrupt_msi_select, + output wire [31:0] cfg_interrupt_msi_int, + output wire [31:0] cfg_interrupt_msi_pending_status, + output wire cfg_interrupt_msi_pending_status_data_enable, + output wire [1:0] cfg_interrupt_msi_pending_status_function_num, + input wire cfg_interrupt_msi_sent, + input wire cfg_interrupt_msi_fail, + output wire [2:0] cfg_interrupt_msi_attr, + output wire cfg_interrupt_msi_tph_present, + output wire [1:0] cfg_interrupt_msi_tph_type, + output wire [7:0] cfg_interrupt_msi_tph_st_tag, + output wire [7:0] cfg_interrupt_msi_function_number +); + +// SFP+ +wire sfp_tx_clk[2]; +wire sfp_tx_rst[2]; +wire sfp_rx_clk[2]; +wire sfp_rx_rst[2]; + +wire sfp_rx_status[2]; + +assign sfp_led[0] = !sfp_rx_status[0]; +assign sfp_led[1] = !sfp_rx_status[1]; +assign led = '1; +assign led_r = 1'b1; +assign led_g = 1'b1; + +localparam HB_COUNT = 62500000; +localparam CL_HB_COUNT = $clog2(HB_COUNT); +logic [CL_HB_COUNT-1:0] hb_count_reg = '0; +logic hb_reg = 1'b0; + +assign led_hb = !hb_reg; + +always_ff @(posedge clk_125mhz) begin + if (hb_count_reg == 0) begin + hb_count_reg <= HB_COUNT; + hb_reg <= !hb_reg; + end else begin + hb_count_reg <= hb_count_reg - 1; + end + + if (rst_125mhz) begin + hb_count_reg <= '0; + hb_reg <= 1'b0; + end +end + +wire sfp_gtpowergood; + +wire sfp_mgt_refclk; +wire sfp_mgt_refclk_int; +wire sfp_mgt_refclk_bufg; + +assign sfp_mgt_refclk_out = sfp_mgt_refclk_bufg; + +wire sfp_rst; + +taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_tx[2](); +taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[2](); +taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_rx[2](); +taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_sfp_stat(); + +if (SIM) begin + + assign sfp_mgt_refclk = sfp_mgt_refclk_p; + assign sfp_mgt_refclk_int = sfp_mgt_refclk_p; + assign sfp_mgt_refclk_bufg = sfp_mgt_refclk_int; + +end else begin + + IBUFDS_GTE4 ibufds_gte4_sfp_mgt_refclk_inst ( + .I (sfp_mgt_refclk_p), + .IB (sfp_mgt_refclk_n), + .CEB (1'b0), + .O (sfp_mgt_refclk), + .ODIV2 (sfp_mgt_refclk_int) + ); + + BUFG_GT bufg_gt_sfp_mgt_refclk_inst ( + .CE (sfp_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (sfp_mgt_refclk_int), + .O (sfp_mgt_refclk_bufg) + ); + +end + +taxi_sync_reset #( + .N(4) +) +sfp_sync_reset_inst ( + .clk(sfp_mgt_refclk_bufg), + .rst(rst_125mhz), + .out(sfp_rst) +); + +taxi_apb_if #( + .ADDR_W(18), + .DATA_W(16) +) +gt_apb_ctrl(); + +taxi_eth_mac_25g_us #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + + .CNT(2), + + // GT config + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + + // GT type + .GT_TYPE("GTY"), + + // GT parameters + .GT_TX_POLARITY('0), + .GT_RX_POLARITY('0), + + // MAC/PHY config + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .DATA_W(MAC_DATA_W), + .PADDING_EN(1'b1), + .DIC_EN(1'b1), + .MIN_FRAME_LEN(64), + .PTP_TS_EN(1'b0), + .PTP_TS_FMT_TOD(1'b1), + .PTP_TS_W(96), + .PRBS31_EN(1'b0), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/6.4), + .STAT_EN(1'b0) +) +sfp_mac_inst ( + .xcvr_ctrl_clk(clk_125mhz), + .xcvr_ctrl_rst(sfp_rst), + + /* + * Transceiver control + */ + .s_apb_ctrl(gt_apb_ctrl), + + /* + * Common + */ + .xcvr_gtpowergood_out(sfp_gtpowergood), + .xcvr_gtrefclk00_in(sfp_mgt_refclk), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(sfp_mgt_refclk), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), + + /* + * Serial data + */ + .xcvr_txp(sfp_tx_p), + .xcvr_txn(sfp_tx_n), + .xcvr_rxp(sfp_rx_p), + .xcvr_rxn(sfp_rx_n), + + /* + * MAC clocks + */ + .rx_clk(sfp_rx_clk), + .rx_rst_in('{2{1'b0}}), + .rx_rst_out(sfp_rx_rst), + .tx_clk(sfp_tx_clk), + .tx_rst_in('{2{1'b0}}), + .tx_rst_out(sfp_tx_rst), + .ptp_sample_clk('{2{1'b0}}), + + /* + * Transmit interface (AXI stream) + */ + .s_axis_tx(axis_sfp_tx), + .m_axis_tx_cpl(axis_sfp_tx_cpl), + + /* + * Receive interface (AXI stream) + */ + .m_axis_rx(axis_sfp_rx), + + /* + * PTP clock + */ + .tx_ptp_ts('{2{'0}}), + .tx_ptp_ts_step('{2{1'b0}}), + .rx_ptp_ts('{2{'0}}), + .rx_ptp_ts_step('{2{1'b0}}), + + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + .tx_lfc_req('{2{1'b0}}), + .tx_lfc_resend('{2{1'b0}}), + .rx_lfc_en('{2{1'b0}}), + .rx_lfc_req(), + .rx_lfc_ack('{2{1'b0}}), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) + */ + .tx_pfc_req('{2{'0}}), + .tx_pfc_resend('{2{1'b0}}), + .rx_pfc_en('{2{'0}}), + .rx_pfc_req(), + .rx_pfc_ack('{2{'0}}), + + /* + * Pause interface + */ + .tx_lfc_pause_en('{2{1'b0}}), + .tx_pause_req('{2{1'b0}}), + .tx_pause_ack(), + + /* + * Statistics + */ + .stat_clk(clk_125mhz), + .stat_rst(rst_125mhz), + .m_axis_stat(axis_sfp_stat), + + /* + * Status + */ + .tx_start_packet(), + .stat_tx_byte(), + .stat_tx_pkt_len(), + .stat_tx_pkt_ucast(), + .stat_tx_pkt_mcast(), + .stat_tx_pkt_bcast(), + .stat_tx_pkt_vlan(), + .stat_tx_pkt_good(), + .stat_tx_pkt_bad(), + .stat_tx_err_oversize(), + .stat_tx_err_user(), + .stat_tx_err_underflow(), + .rx_start_packet(), + .rx_error_count(), + .rx_block_lock(), + .rx_high_ber(), + .rx_status(sfp_rx_status), + .stat_rx_byte(), + .stat_rx_pkt_len(), + .stat_rx_pkt_fragment(), + .stat_rx_pkt_jabber(), + .stat_rx_pkt_ucast(), + .stat_rx_pkt_mcast(), + .stat_rx_pkt_bcast(), + .stat_rx_pkt_vlan(), + .stat_rx_pkt_good(), + .stat_rx_pkt_bad(), + .stat_rx_err_oversize(), + .stat_rx_err_bad_fcs(), + .stat_rx_err_bad_block(), + .stat_rx_err_framing(), + .stat_rx_err_preamble(), + .stat_rx_fifo_drop('{2{1'b0}}), + .stat_tx_mcf(), + .stat_rx_mcf(), + .stat_tx_lfc_pkt(), + .stat_tx_lfc_xon(), + .stat_tx_lfc_xoff(), + .stat_tx_lfc_paused(), + .stat_tx_pfc_pkt(), + .stat_tx_pfc_xon(), + .stat_tx_pfc_xoff(), + .stat_tx_pfc_paused(), + .stat_rx_lfc_pkt(), + .stat_rx_lfc_xon(), + .stat_rx_lfc_xoff(), + .stat_rx_lfc_paused(), + .stat_rx_pfc_pkt(), + .stat_rx_pfc_xon(), + .stat_rx_pfc_xoff(), + .stat_rx_pfc_paused(), + + /* + * Configuration + */ + .cfg_tx_max_pkt_len('{2{16'd9218}}), + .cfg_tx_ifg('{2{8'd12}}), + .cfg_tx_enable('{2{1'b1}}), + .cfg_rx_max_pkt_len('{2{16'd9218}}), + .cfg_rx_enable('{2{1'b1}}), + .cfg_tx_prbs31_enable('{2{1'b0}}), + .cfg_rx_prbs31_enable('{2{1'b0}}), + .cfg_mcf_rx_eth_dst_mcast('{2{48'h01_80_C2_00_00_01}}), + .cfg_mcf_rx_check_eth_dst_mcast('{2{1'b1}}), + .cfg_mcf_rx_eth_dst_ucast('{2{48'd0}}), + .cfg_mcf_rx_check_eth_dst_ucast('{2{1'b0}}), + .cfg_mcf_rx_eth_src('{2{48'd0}}), + .cfg_mcf_rx_check_eth_src('{2{1'b0}}), + .cfg_mcf_rx_eth_type('{2{16'h8808}}), + .cfg_mcf_rx_opcode_lfc('{2{16'h0001}}), + .cfg_mcf_rx_check_opcode_lfc('{2{1'b1}}), + .cfg_mcf_rx_opcode_pfc('{2{16'h0101}}), + .cfg_mcf_rx_check_opcode_pfc('{2{1'b1}}), + .cfg_mcf_rx_forward('{2{1'b0}}), + .cfg_mcf_rx_enable('{2{1'b0}}), + .cfg_tx_lfc_eth_dst('{2{48'h01_80_C2_00_00_01}}), + .cfg_tx_lfc_eth_src('{2{48'h80_23_31_43_54_4C}}), + .cfg_tx_lfc_eth_type('{2{16'h8808}}), + .cfg_tx_lfc_opcode('{2{16'h0001}}), + .cfg_tx_lfc_en('{2{1'b0}}), + .cfg_tx_lfc_quanta('{2{16'hffff}}), + .cfg_tx_lfc_refresh('{2{16'h7fff}}), + .cfg_tx_pfc_eth_dst('{2{48'h01_80_C2_00_00_01}}), + .cfg_tx_pfc_eth_src('{2{48'h80_23_31_43_54_4C}}), + .cfg_tx_pfc_eth_type('{2{16'h8808}}), + .cfg_tx_pfc_opcode('{2{16'h0101}}), + .cfg_tx_pfc_en('{2{1'b0}}), + .cfg_tx_pfc_quanta('{2{'{8{16'hffff}}}}), + .cfg_tx_pfc_refresh('{2{'{8{16'h7fff}}}}), + .cfg_rx_lfc_opcode('{2{16'h0001}}), + .cfg_rx_lfc_en('{2{1'b0}}), + .cfg_rx_pfc_opcode('{2{16'h0101}}), + .cfg_rx_pfc_en('{2{1'b0}}) +); + +cndm_proto_pcie_us #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + .PORTS(2), + .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W), + .BAR0_APERTURE(24) +) +cndm_inst ( + /* + * PCIe + */ + .pcie_clk(pcie_clk), + .pcie_rst(pcie_rst), + .s_axis_pcie_cq(s_axis_pcie_cq), + .m_axis_pcie_cc(m_axis_pcie_cc), + .m_axis_pcie_rq(m_axis_pcie_rq), + .s_axis_pcie_rc(s_axis_pcie_rc), + + .pcie_rq_seq_num0(pcie_rq_seq_num0), + .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), + .pcie_rq_seq_num1(pcie_rq_seq_num1), + .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_rcb_status(cfg_rcb_status), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + /* + * Ethernet + */ + .mac_tx_clk(sfp_tx_clk), + .mac_tx_rst(sfp_tx_rst), + .mac_axis_tx(axis_sfp_tx), + .mac_axis_tx_cpl(axis_sfp_tx_cpl), + + .mac_rx_clk(sfp_rx_clk), + .mac_rx_rst(sfp_rx_rst), + .mac_axis_rx(axis_sfp_rx) +); + +endmodule + +`resetall diff --git a/src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/Makefile b/src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/Makefile new file mode 100644 index 0000000..d98ba29 --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/Makefile @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +DUT = fpga_core +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/cndm_proto/rtl/cndm_proto_pcie_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_SIM := "1'b1" +export PARAM_VENDOR := "\"XILINX\"" +export PARAM_FAMILY := "\"kintexuplus\"" +export PARAM_AXIS_PCIE_DATA_W := 256 +export PARAM_CFG_LOW_LATENCY := "1'b1" +export PARAM_COMBINED_MAC_PCS := "1'b1" +export PARAM_MAC_DATA_W := "64" + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/baser.py b/src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/cndm_proto.py b/src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/cndm_proto.py new file mode 120000 index 0000000..6697396 --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/cndm_proto.py @@ -0,0 +1 @@ +../../lib/taxi/src/cndm_proto/tb/cndm_proto.py \ No newline at end of file diff --git a/src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.py b/src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.py new file mode 100644 index 0000000..04f15c8 --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,508 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: MIT +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import logging +import os +import sys + +import pytest +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, FallingEdge, Timer + +from cocotbext.axi import AxiStreamBus +from cocotbext.eth import XgmiiFrame +from cocotbext.pcie.core import RootComplex +from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice + +try: + from baser import BaseRSerdesSource, BaseRSerdesSink + import cndm_proto +except ImportError: + # attempt import from current directory + sys.path.insert(0, os.path.join(os.path.dirname(__file__))) + try: + from baser import BaseRSerdesSource, BaseRSerdesSink + import cndm_proto + finally: + del sys.path[0] + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + # PCIe + self.rc = RootComplex() + + self.rc.max_payload_size = 0x1 # 256 bytes + self.rc.max_read_request_size = 0x2 # 512 bytes + + self.dev = UltraScalePlusPcieDevice( + # configuration options + pcie_generation=3, + pcie_link_width=8, + user_clk_frequency=250e6, + alignment="dword", + cq_straddle=False, + cc_straddle=False, + rq_straddle=False, + rc_straddle=False, + rc_4tlp_straddle=False, + pf_count=1, + max_payload_size=1024, + enable_client_tag=True, + enable_extended_tag=True, + enable_parity=False, + enable_rx_msg_interface=False, + enable_sriov=False, + enable_extended_configuration=False, + + pf0_msi_enable=True, + pf0_msi_count=32, + pf1_msi_enable=False, + pf1_msi_count=1, + pf2_msi_enable=False, + pf2_msi_count=1, + pf3_msi_enable=False, + pf3_msi_count=1, + pf0_msix_enable=False, + pf0_msix_table_size=31, + pf0_msix_table_bir=4, + pf0_msix_table_offset=0x00000000, + pf0_msix_pba_bir=4, + pf0_msix_pba_offset=0x00008000, + pf1_msix_enable=False, + pf1_msix_table_size=0, + pf1_msix_table_bir=0, + pf1_msix_table_offset=0x00000000, + pf1_msix_pba_bir=0, + pf1_msix_pba_offset=0x00000000, + pf2_msix_enable=False, + pf2_msix_table_size=0, + pf2_msix_table_bir=0, + pf2_msix_table_offset=0x00000000, + pf2_msix_pba_bir=0, + pf2_msix_pba_offset=0x00000000, + pf3_msix_enable=False, + pf3_msix_table_size=0, + pf3_msix_table_bir=0, + pf3_msix_table_offset=0x00000000, + pf3_msix_pba_bir=0, + pf3_msix_pba_offset=0x00000000, + + # signals + # Clock and Reset Interface + user_clk=dut.pcie_clk, + user_reset=dut.pcie_rst, + # user_lnk_up + # sys_clk + # sys_clk_gt + # sys_reset + # phy_rdy_out + + # Requester reQuest Interface + rq_bus=AxiStreamBus.from_entity(dut.m_axis_pcie_rq), + pcie_rq_seq_num0=dut.pcie_rq_seq_num0, + pcie_rq_seq_num_vld0=dut.pcie_rq_seq_num_vld0, + pcie_rq_seq_num1=dut.pcie_rq_seq_num1, + pcie_rq_seq_num_vld1=dut.pcie_rq_seq_num_vld1, + # pcie_rq_tag0 + # pcie_rq_tag1 + # pcie_rq_tag_av + # pcie_rq_tag_vld0 + # pcie_rq_tag_vld1 + + # Requester Completion Interface + rc_bus=AxiStreamBus.from_entity(dut.s_axis_pcie_rc), + + # Completer reQuest Interface + cq_bus=AxiStreamBus.from_entity(dut.s_axis_pcie_cq), + # pcie_cq_np_req + # pcie_cq_np_req_count + + # Completer Completion Interface + cc_bus=AxiStreamBus.from_entity(dut.m_axis_pcie_cc), + + # Transmit Flow Control Interface + # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, + # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, + + # Configuration Management Interface + # cfg_mgmt_addr=dut.cfg_mgmt_addr, + # cfg_mgmt_function_number=dut.cfg_mgmt_function_number, + # cfg_mgmt_write=dut.cfg_mgmt_write, + # cfg_mgmt_write_data=dut.cfg_mgmt_write_data, + # cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, + # cfg_mgmt_read=dut.cfg_mgmt_read, + # cfg_mgmt_read_data=dut.cfg_mgmt_read_data, + # cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, + # cfg_mgmt_debug_access + + # Configuration Status Interface + # cfg_phy_link_down + # cfg_phy_link_status + # cfg_negotiated_width + # cfg_current_speed + # cfg_max_payload=dut.cfg_max_payload, + # cfg_max_read_req=dut.cfg_max_read_req, + # cfg_function_status + # cfg_vf_status + # cfg_function_power_state + # cfg_vf_power_state + # cfg_link_power_state + # cfg_err_cor_out + # cfg_err_nonfatal_out + # cfg_err_fatal_out + # cfg_local_error_out + # cfg_local_error_valid + # cfg_rx_pm_state + # cfg_tx_pm_state + # cfg_ltssm_state + # cfg_rcb_status=dut.cfg_rcb_status, + # cfg_obff_enable + # cfg_pl_status_change + # cfg_tph_requester_enable + # cfg_tph_st_mode + # cfg_vf_tph_requester_enable + # cfg_vf_tph_st_mode + + # Configuration Received Message Interface + # cfg_msg_received + # cfg_msg_received_data + # cfg_msg_received_type + + # Configuration Transmit Message Interface + # cfg_msg_transmit + # cfg_msg_transmit_type + # cfg_msg_transmit_data + # cfg_msg_transmit_done + + # Configuration Flow Control Interface + cfg_fc_ph=dut.cfg_fc_ph, + cfg_fc_pd=dut.cfg_fc_pd, + cfg_fc_nph=dut.cfg_fc_nph, + cfg_fc_npd=dut.cfg_fc_npd, + cfg_fc_cplh=dut.cfg_fc_cplh, + cfg_fc_cpld=dut.cfg_fc_cpld, + cfg_fc_sel=dut.cfg_fc_sel, + + # Configuration Control Interface + # cfg_hot_reset_in + # cfg_hot_reset_out + # cfg_config_space_enable + # cfg_dsn + # cfg_bus_number + # cfg_ds_port_number + # cfg_ds_bus_number + # cfg_ds_device_number + # cfg_ds_function_number + # cfg_power_state_change_ack + # cfg_power_state_change_interrupt + # cfg_err_cor_in=dut.status_error_cor, + # cfg_err_uncor_in=dut.status_error_uncor, + # cfg_flr_in_process + # cfg_flr_done + # cfg_vf_flr_in_process + # cfg_vf_flr_func_num + # cfg_vf_flr_done + # cfg_pm_aspm_l1_entry_reject + # cfg_pm_aspm_tx_l0s_entry_disable + # cfg_req_pm_transition_l23_ready + # cfg_link_training_enable + + # Configuration Interrupt Controller Interface + # cfg_interrupt_int + # cfg_interrupt_sent + # cfg_interrupt_pending + cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, + cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, + cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, + cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, + cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, + cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, + cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, + cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, + cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, + cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, + cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, + # cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable, + # cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask, + # cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable, + # cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask, + # cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address, + # cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data, + # cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int, + # cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending, + # cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status, + # cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent, + # cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail, + cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, + cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, + cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, + cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, + cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, + + # Configuration Extend Interface + # cfg_ext_read_received + # cfg_ext_write_received + # cfg_ext_register_number + # cfg_ext_function_number + # cfg_ext_write_data + # cfg_ext_write_byte_enable + # cfg_ext_read_data + # cfg_ext_read_data_valid + ) + + # self.dev.log.setLevel(logging.DEBUG) + + self.rc.make_port().connect(self.dev) + + self.dev.functions[0].configure_bar(0, 2**int(dut.uut.cndm_inst.axil_ctrl_bar.ADDR_W)) + + # Ethernet + cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start()) + cocotb.start_soon(Clock(dut.sfp_mgt_refclk_p, 6.4, units="ns").start()) + + self.sfp_sources = [] + self.sfp_sinks = [] + + for ch in dut.uut.sfp_mac_inst.ch: + gt_inst = ch.ch_inst.gt.gt_inst + + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) + else: + clk = 2.56 + gbx_cfg = None + else: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None + + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + + self.sfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.sfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) + + dut.sfp_npres.setimmediatevalue(0) + dut.sfp_tx_fault.setimmediatevalue(0) + dut.sfp_los.setimmediatevalue(0) + + self.loopback_enable = False + cocotb.start_soon(self._run_loopback()) + + async def init(self): + + self.dut.rst_125mhz.setimmediatevalue(0) + + await FallingEdge(self.dut.pcie_rst) + await Timer(100, 'ns') + + for k in range(10): + await RisingEdge(self.dut.clk_125mhz) + + self.dut.rst_125mhz.value = 1 + + for k in range(10): + await RisingEdge(self.dut.clk_125mhz) + + self.dut.rst_125mhz.value = 0 + + for k in range(10): + await RisingEdge(self.dut.clk_125mhz) + + await self.rc.enumerate() + + async def _run_loopback(self): + while True: + await RisingEdge(self.dut.pcie_clk) + + if self.loopback_enable: + for src, snk in zip(self.sfp_sources, self.sfp_sinks): + while not snk.empty(): + await src.send(await snk.recv()) + +@cocotb.test() +async def run_test(dut): + + tb = TB(dut) + + await tb.init() + + tb.log.info("Init driver model") + driver = cndm_proto.Driver() + await driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id)) + + tb.log.info("Init complete") + + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk_125mhz) + + for snk in tb.sfp_sinks: + snk.clear() + + tb.log.info("Send and receive single packet on each port") + + for k in range(len(driver.ports)): + data = f"Corundum rocks on port {k}!".encode('ascii') + + await driver.ports[k].start_xmit(data) + + pkt = await tb.sfp_sinks[k].recv() + tb.log.info("Got TX packet: %s", pkt) + + assert pkt.get_payload().startswith(data) + assert pkt.check_fcs() + + await tb.sfp_sources[k].send(pkt) + + pkt = await driver.ports[k].recv() + tb.log.info("Got RX packet: %s", pkt) + + assert bytes(pkt).startswith(data) + + tb.log.info("Multiple small packets") + + count = 64 + pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await driver.ports[0].start_xmit(p) + + for k in range(count): + pkt = await driver.ports[0].recv() + + tb.log.info("Got RX packet: %s", pkt) + + assert bytes(pkt).startswith(pkts[k]) + + tb.loopback_enable = False + + tb.log.info("Multiple large packets") + + count = 64 + pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await driver.ports[0].start_xmit(p) + + for k in range(count): + pkt = await driver.ports[0].recv() + + tb.log.info("Got RX packet: %s", pkt) + + assert bytes(pkt) == pkts[k] + + tb.loopback_enable = False + + await RisingEdge(dut.clk_125mhz) + await RisingEdge(dut.clk_125mhz) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +@pytest.mark.parametrize("mac_data_w", [32, 64]) +def test_fpga_core(request, mac_data_w): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "cndm_proto", "rtl", "cndm_proto_pcie_us.f"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['SIM'] = "1'b1" + parameters['VENDOR'] = "\"XILINX\"" + parameters['FAMILY'] = "\"kintexuplus\"" + parameters['AXIS_PCIE_DATA_W'] = 256 + parameters['CFG_LOW_LATENCY'] = "1'b1" + parameters['COMBINED_MAC_PCS'] = "1'b1" + parameters['MAC_DATA_W'] = mac_data_w + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.sv b/src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.sv new file mode 100644 index 0000000..00866d9 --- /dev/null +++ b/src/cndm_proto/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.sv @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic testbench + */ +module test_fpga_core # +( + /* verilator lint_off WIDTHTRUNC */ + parameter logic SIM = 1'b0, + parameter string VENDOR = "XILINX", + parameter string FAMILY = "kintexuplus", + parameter AXIS_PCIE_DATA_W = 256, + parameter AXIS_PCIE_RC_USER_W = AXIS_PCIE_DATA_W < 512 ? 75 : 161, + parameter AXIS_PCIE_RQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 62 : 137, + parameter AXIS_PCIE_CQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 85 : 183, + parameter AXIS_PCIE_CC_USER_W = AXIS_PCIE_DATA_W < 512 ? 33 : 81, + // 10G/25G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 + /* verilator lint_on WIDTHTRUNC */ +) +(); + +localparam AXIS_PCIE_KEEP_W = (AXIS_PCIE_DATA_W/32); +localparam RQ_SEQ_NUM_W = AXIS_PCIE_RQ_USER_W == 60 ? 4 : 6; + +logic clk_125mhz; +logic rst_125mhz; + +logic sfp_led[2]; +logic [3:0] led; +logic led_r; +logic led_g; +logic led_hb; + +logic sfp_mgt_refclk_p; +logic sfp_mgt_refclk_n; +logic sfp_mgt_refclk_out; + +logic [1:0] sfp_npres; +logic [1:0] sfp_tx_fault; +logic [1:0] sfp_los; + +logic pcie_clk; +logic pcie_rst; + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_CQ_USER_W) +) s_axis_pcie_cq(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_CC_USER_W) +) m_axis_pcie_cc(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_RQ_USER_W) +) m_axis_pcie_rq(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_RC_USER_W) +) s_axis_pcie_rc(); + +logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0; +logic pcie_rq_seq_num_vld0; +logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1; +logic pcie_rq_seq_num_vld1; + +logic [2:0] cfg_max_payload; +logic [2:0] cfg_max_read_req; +logic [3:0] cfg_rcb_status; + +logic [9:0] cfg_mgmt_addr; +logic [7:0] cfg_mgmt_function_number; +logic cfg_mgmt_write; +logic [31:0] cfg_mgmt_write_data; +logic [3:0] cfg_mgmt_byte_enable; +logic cfg_mgmt_read; +logic [31:0] cfg_mgmt_read_data; +logic cfg_mgmt_read_write_done; + +logic [7:0] cfg_fc_ph; +logic [11:0] cfg_fc_pd; +logic [7:0] cfg_fc_nph; +logic [11:0] cfg_fc_npd; +logic [7:0] cfg_fc_cplh; +logic [11:0] cfg_fc_cpld; +logic [2:0] cfg_fc_sel; + +logic [3:0] cfg_interrupt_msi_enable; +logic [11:0] cfg_interrupt_msi_mmenable; +logic cfg_interrupt_msi_mask_update; +logic [31:0] cfg_interrupt_msi_data; +logic [1:0] cfg_interrupt_msi_select; +logic [31:0] cfg_interrupt_msi_int; +logic [31:0] cfg_interrupt_msi_pending_status; +logic cfg_interrupt_msi_pending_status_data_enable; +logic [1:0] cfg_interrupt_msi_pending_status_function_num; +logic cfg_interrupt_msi_sent; +logic cfg_interrupt_msi_fail; +logic [2:0] cfg_interrupt_msi_attr; +logic cfg_interrupt_msi_tph_present; +logic [1:0] cfg_interrupt_msi_tph_type; +logic [7:0] cfg_interrupt_msi_tph_st_tag; +logic [7:0] cfg_interrupt_msi_function_number; + +fpga_core #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W), + // 10G/25G MAC configuration + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) +) +uut ( + /* + * Clock: 125MHz + * Synchronous reset + */ + .clk_125mhz(clk_125mhz), + .rst_125mhz(rst_125mhz), + + /* + * GPIO + */ + .sfp_led(sfp_led), + .led(led), + .led_r(led_r), + .led_g(led_g), + .led_hb(led_hb), + + /* + * PCIe + */ + .pcie_clk(pcie_clk), + .pcie_rst(pcie_rst), + .s_axis_pcie_cq(s_axis_pcie_cq), + .m_axis_pcie_cc(m_axis_pcie_cc), + .m_axis_pcie_rq(m_axis_pcie_rq), + .s_axis_pcie_rc(s_axis_pcie_rc), + + .pcie_rq_seq_num0(pcie_rq_seq_num0), + .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), + .pcie_rq_seq_num1(pcie_rq_seq_num1), + .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_rcb_status(cfg_rcb_status), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + /* + * Ethernet: SFP+ + */ + .sfp_rx_p(), + .sfp_rx_n(), + .sfp_tx_p('{2{1'b0}}), + .sfp_tx_n('{2{1'b0}}), + .sfp_mgt_refclk_p(sfp_mgt_refclk_p), + .sfp_mgt_refclk_n(sfp_mgt_refclk_n), + .sfp_mgt_refclk_out(sfp_mgt_refclk_out), + .sfp_npres(sfp_npres), + .sfp_tx_fault(sfp_tx_fault), + .sfp_los(sfp_los) +); + +endmodule + +`resetall