diff --git a/src/eth/example/HTG940/fpga/fpga.xdc b/src/eth/example/HTG940/fpga/fpga.xdc deleted file mode 100644 index 630f722..0000000 --- a/src/eth/example/HTG940/fpga/fpga.xdc +++ /dev/null @@ -1,122 +0,0 @@ -# SPDX-License-Identifier: MIT -# -# Copyright (c) 2025 FPGA Ninja, LLC -# -# Authors: -# - Alex Forencich -# - -# XDC constraints for the HiTech Global HTG-9200 board -# part: xcvu9p-flgb2104-2-e -# part: xcvu13p-fhgb2104-2-e - -# General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] - -# System clocks -# DDR4 clocks from U37 (200 MHz) -#set_property -dict {LOC BA34 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_a_p] -#set_property -dict {LOC BB34 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_a_n] -#create_clock -period 5.000 -name sys_clk_ddr4_a [get_ports sys_clk_ddr4_a_p] - -# refclk from U39 (156.25 MHz) -set_property -dict {LOC AW28 IOSTANDARD LVDS} [get_ports ref_clk_p] -set_property -dict {LOC AY28 IOSTANDARD LVDS} [get_ports ref_clk_n] -create_clock -period 6.400 -name ref_clk [get_ports ref_clk_p] - -# LEDs -set_property -dict {LOC AP28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}] -set_property -dict {LOC AN28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}] -set_property -dict {LOC AP26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[2]}] -set_property -dict {LOC AP25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[3]}] -set_property -dict {LOC AR28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[4]}] -set_property -dict {LOC AR27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[5]}] -set_property -dict {LOC AT28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[6]}] -set_property -dict {LOC AR25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[7]}] - -set_false_path -to [get_ports {led[*]}] -set_output_delay 0 [get_ports {led[*]}] - -# Push buttons -set_property -dict {LOC AJ34 IOSTANDARD LVCMOS12} [get_ports {btn[0]}] -set_property -dict {LOC AK32 IOSTANDARD LVCMOS12} [get_ports {btn[1]}] - -set_false_path -from [get_ports {btn[*]}] -set_input_delay 0 [get_ports {btn[*]}] - -# DIP switches -set_property -dict {LOC BF33 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] -set_property -dict {LOC AK27 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] -set_property -dict {LOC AR32 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] -set_property -dict {LOC AR31 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] -set_property -dict {LOC AT32 IOSTANDARD LVCMOS12} [get_ports {sw[4]}] -set_property -dict {LOC AW30 IOSTANDARD LVCMOS12} [get_ports {sw[5]}] -set_property -dict {LOC BC32 IOSTANDARD LVCMOS12} [get_ports {sw[6]}] -set_property -dict {LOC BC33 IOSTANDARD LVCMOS12} [get_ports {sw[7]}] - -set_false_path -from [get_ports {sw[*]}] -set_input_delay 0 [get_ports {sw[*]}] - -# UART (U53 CP2103) -set_property -dict {LOC R15 IOSTANDARD LVCMOS18} [get_ports {uart_txd}] ;# U53.25 TXD_O -set_property -dict {LOC P15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_rxd}] ;# U53.24 RXD_I -set_property -dict {LOC L15 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U53.23 RTS_O_B -set_property -dict {LOC D14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U53.22 CTS_I_B -set_property -dict {LOC P16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_rst_n}] ;# U53.9 RST_B - -set_false_path -to [get_ports {uart_rxd uart_cts uart_rst_n}] -set_output_delay 0 [get_ports {uart_rxd uart_cts uart_rst_n}] -set_false_path -from [get_ports {uart_txd uart_rts}] -set_input_delay 0 [get_ports {uart_txd uart_rts}] - -# I2C -set_property -dict {LOC AV28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_scl] -set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_sda] -set_property -dict {LOC AV27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_rst_n] - -set_false_path -to [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}] -set_output_delay 0 [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}] -set_false_path -from [get_ports {i2c_main_sda i2c_main_scl}] -set_input_delay 0 [get_ports {i2c_main_sda i2c_main_scl}] - -# Gigabit Ethernet RGMII PHY -set_property -dict {LOC G20 IOSTANDARD LVCMOS18} [get_ports {phy_rx_clk}] ;# from U2.43 // MAYBE -set_property -dict {LOC A20 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[0]}] ;# from U2.44 -set_property -dict {LOC D21 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[1]}] ;# from U2.45 -set_property -dict {LOC E21 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[2]}] ;# from U2.46 -set_property -dict {LOC C21 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[3]}] ;# from U2.47 -set_property -dict {LOC B21 IOSTANDARD LVCMOS18} [get_ports {phy_rx_ctl}] ;# from U2.53 -set_property -dict {LOC B20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_tx_clk}] ;# from U2.40 -set_property -dict {LOC D20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] ;# from U2.38 -set_property -dict {LOC A19 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] ;# from U2.37 -set_property -dict {LOC B19 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] ;# from U2.36 -set_property -dict {LOC E20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] ;# from U2.35 -set_property -dict {LOC G21 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_tx_ctl}] ;# from U2.52 -#set_property -dict {LOC G19 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy_mdio}] ;# from U2.21 -#set_property -dict {LOC A18 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy_mdc}] ;# from U2.20 - -create_clock -period 8.000 -name {phy_rx_clk} [get_ports {phy_rx_clk}] - -#set_false_path -to [get_ports {phy_mdio phy_mdc}] -#set_output_delay 0 [get_ports {phy_mdio phy_mdc}] -#set_false_path -from [get_ports {phy_mdio}] -#set_input_delay 0 [get_ports {phy_mdio}] - -# QSPI flash -#set_property -dict {LOC AM26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[0]}] -#set_property -dict {LOC AN26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[1]}] -#set_property -dict {LOC AL25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[2]}] -#set_property -dict {LOC AM25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[3]}] -#set_property -dict {LOC BF27 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_cs_n}] - -#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}] -#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}] -#set_false_path -from [get_ports {qspi_1_dq}] -#set_input_delay 0 [get_ports {qspi_1_dq}] diff --git a/src/eth/example/HTG940/fpga/fpga_vu13p/Makefile b/src/eth/example/HTG940/fpga/fpga_vu13p/Makefile index 522e23a..e69fea8 100644 --- a/src/eth/example/HTG940/fpga/fpga_vu13p/Makefile +++ b/src/eth/example/HTG940/fpga/fpga_vu13p/Makefile @@ -27,8 +27,11 @@ SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # XDC files -XDC_FILES = ../fpga.xdc -XDC_FILES += ../eth_rgmii.xdc +XDC_FILES += ../syn/fpga.xdc +XDC_FILES += ../syn/gpio.xdc +XDC_FILES += ../syn/i2c.xdc +XDC_FILES += ../syn/phy.xdc +XDC_FILES += ../syn/eth_rgmii.xdc XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl diff --git a/src/eth/example/HTG940/fpga/fpga_vu9p/Makefile b/src/eth/example/HTG940/fpga/fpga_vu9p/Makefile index bc5cdd9..fd610b0 100644 --- a/src/eth/example/HTG940/fpga/fpga_vu9p/Makefile +++ b/src/eth/example/HTG940/fpga/fpga_vu9p/Makefile @@ -27,8 +27,11 @@ SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv # XDC files -XDC_FILES = ../fpga.xdc -XDC_FILES += ../eth_rgmii.xdc +XDC_FILES += ../syn/fpga.xdc +XDC_FILES += ../syn/gpio.xdc +XDC_FILES += ../syn/i2c.xdc +XDC_FILES += ../syn/phy.xdc +XDC_FILES += ../syn/eth_rgmii.xdc XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl diff --git a/src/eth/example/HTG940/fpga/syn/eth_rgmii.xdc b/src/eth/example/HTG940/fpga/syn/eth_rgmii.xdc new file mode 100644 index 0000000..0873ef5 --- /dev/null +++ b/src/eth/example/HTG940/fpga/syn/eth_rgmii.xdc @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# Ethernet constraints + +# IDELAY from PHY chip (RGMII) +set_property DELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_bit[*].idelay_inst}] + +# MMCM phase (RGMII) +set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst] diff --git a/src/eth/example/HTG940/fpga/syn/fpga.xdc b/src/eth/example/HTG940/fpga/syn/fpga.xdc new file mode 100644 index 0000000..6c70e56 --- /dev/null +++ b/src/eth/example/HTG940/fpga/syn/fpga.xdc @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# XDC constraints for the HiTech Global HTG-9200 board +# part: xcvu9p-flgb2104-2-e +# part: xcvu13p-fhgb2104-2-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +# System clocks +# DDR4 clocks from U37 (200 MHz) +#set_property -dict {LOC BA34 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_a_p] +#set_property -dict {LOC BB34 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_a_n] +#create_clock -period 5.000 -name sys_clk_ddr4_a [get_ports sys_clk_ddr4_a_p] + +# refclk from U39 (156.25 MHz) +set_property -dict {LOC AW28 IOSTANDARD LVDS} [get_ports ref_clk_p] +set_property -dict {LOC AY28 IOSTANDARD LVDS} [get_ports ref_clk_n] +create_clock -period 6.400 -name ref_clk [get_ports ref_clk_p] diff --git a/src/eth/example/HTG940/fpga/syn/gpio.xdc b/src/eth/example/HTG940/fpga/syn/gpio.xdc new file mode 100644 index 0000000..2b56fd7 --- /dev/null +++ b/src/eth/example/HTG940/fpga/syn/gpio.xdc @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# XDC constraints for the HiTech Global HTG-9200 board +# part: xcvu9p-flgb2104-2-e +# part: xcvu13p-fhgb2104-2-e + +# LEDs +set_property -dict {LOC AP28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}] +set_property -dict {LOC AN28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}] +set_property -dict {LOC AP26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[2]}] +set_property -dict {LOC AP25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[3]}] +set_property -dict {LOC AR28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[4]}] +set_property -dict {LOC AR27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[5]}] +set_property -dict {LOC AT28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[6]}] +set_property -dict {LOC AR25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[7]}] + +set_false_path -to [get_ports {led[*]}] +set_output_delay 0 [get_ports {led[*]}] + +# Push buttons +set_property -dict {LOC AJ34 IOSTANDARD LVCMOS12} [get_ports {btn[0]}] +set_property -dict {LOC AK32 IOSTANDARD LVCMOS12} [get_ports {btn[1]}] + +set_false_path -from [get_ports {btn[*]}] +set_input_delay 0 [get_ports {btn[*]}] + +# DIP switches +set_property -dict {LOC BF33 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] +set_property -dict {LOC AK27 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] +set_property -dict {LOC AR32 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] +set_property -dict {LOC AR31 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] +set_property -dict {LOC AT32 IOSTANDARD LVCMOS12} [get_ports {sw[4]}] +set_property -dict {LOC AW30 IOSTANDARD LVCMOS12} [get_ports {sw[5]}] +set_property -dict {LOC BC32 IOSTANDARD LVCMOS12} [get_ports {sw[6]}] +set_property -dict {LOC BC33 IOSTANDARD LVCMOS12} [get_ports {sw[7]}] + +set_false_path -from [get_ports {sw[*]}] +set_input_delay 0 [get_ports {sw[*]}] + +# UART (U53 CP2103) +set_property -dict {LOC R15 IOSTANDARD LVCMOS18} [get_ports {uart_txd}] ;# U53.25 TXD_O +set_property -dict {LOC P15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_rxd}] ;# U53.24 RXD_I +set_property -dict {LOC L15 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U53.23 RTS_O_B +set_property -dict {LOC D14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U53.22 CTS_I_B +set_property -dict {LOC P16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_rst_n}] ;# U53.9 RST_B + +set_false_path -to [get_ports {uart_rxd uart_cts uart_rst_n}] +set_output_delay 0 [get_ports {uart_rxd uart_cts uart_rst_n}] +set_false_path -from [get_ports {uart_txd uart_rts}] +set_input_delay 0 [get_ports {uart_txd uart_rts}] diff --git a/src/eth/example/HTG940/fpga/syn/i2c.xdc b/src/eth/example/HTG940/fpga/syn/i2c.xdc new file mode 100644 index 0000000..4d9960e --- /dev/null +++ b/src/eth/example/HTG940/fpga/syn/i2c.xdc @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# XDC constraints for the HiTech Global HTG-9200 board +# part: xcvu9p-flgb2104-2-e +# part: xcvu13p-fhgb2104-2-e + +# I2C +set_property -dict {LOC AV28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_scl] +set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_sda] +set_property -dict {LOC AV27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_rst_n] + +set_false_path -to [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}] +set_output_delay 0 [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}] +set_false_path -from [get_ports {i2c_main_sda i2c_main_scl}] +set_input_delay 0 [get_ports {i2c_main_sda i2c_main_scl}] diff --git a/src/eth/example/HTG940/fpga/syn/phy.xdc b/src/eth/example/HTG940/fpga/syn/phy.xdc new file mode 100644 index 0000000..6cf51de --- /dev/null +++ b/src/eth/example/HTG940/fpga/syn/phy.xdc @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# XDC constraints for the HiTech Global HTG-9200 board +# part: xcvu9p-flgb2104-2-e +# part: xcvu13p-fhgb2104-2-e + +# Gigabit Ethernet RGMII PHY +set_property -dict {LOC G20 IOSTANDARD LVCMOS18} [get_ports {phy_rx_clk}] ;# from U2.43 // MAYBE +set_property -dict {LOC A20 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[0]}] ;# from U2.44 +set_property -dict {LOC D21 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[1]}] ;# from U2.45 +set_property -dict {LOC E21 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[2]}] ;# from U2.46 +set_property -dict {LOC C21 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[3]}] ;# from U2.47 +set_property -dict {LOC B21 IOSTANDARD LVCMOS18} [get_ports {phy_rx_ctl}] ;# from U2.53 +set_property -dict {LOC B20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_tx_clk}] ;# from U2.40 +set_property -dict {LOC D20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] ;# from U2.38 +set_property -dict {LOC A19 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] ;# from U2.37 +set_property -dict {LOC B19 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] ;# from U2.36 +set_property -dict {LOC E20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] ;# from U2.35 +set_property -dict {LOC G21 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_tx_ctl}] ;# from U2.52 +#set_property -dict {LOC G19 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy_mdio}] ;# from U2.21 +#set_property -dict {LOC A18 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy_mdc}] ;# from U2.20 + +create_clock -period 8.000 -name {phy_rx_clk} [get_ports {phy_rx_clk}] + +#set_false_path -to [get_ports {phy_mdio phy_mdc}] +#set_output_delay 0 [get_ports {phy_mdio phy_mdc}] +#set_false_path -from [get_ports {phy_mdio}] +#set_input_delay 0 [get_ports {phy_mdio}] diff --git a/src/eth/example/HTG940/fpga/syn/qspi.xdc b/src/eth/example/HTG940/fpga/syn/qspi.xdc new file mode 100644 index 0000000..feb8e6f --- /dev/null +++ b/src/eth/example/HTG940/fpga/syn/qspi.xdc @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# XDC constraints for the HiTech Global HTG-9200 board +# part: xcvu9p-flgb2104-2-e +# part: xcvu13p-fhgb2104-2-e + +# QSPI flash +set_property -dict {LOC AM26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[0]}] +set_property -dict {LOC AN26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[1]}] +set_property -dict {LOC AL25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[2]}] +set_property -dict {LOC AM25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[3]}] +set_property -dict {LOC BF27 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_cs_n}] + +set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}] +set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}] +set_false_path -from [get_ports {qspi_1_dq}] +set_input_delay 0 [get_ports {qspi_1_dq}]