diff --git a/README.md b/README.md index 6ee292b..c632b7f 100644 --- a/README.md +++ b/README.md @@ -84,8 +84,9 @@ To facilitate the dual-license model, contributions to the project can only be a * LFSR self-synchronizing scrambler * LFSR self-synchronizing descrambler * Low-speed serial - * UART + * I2C master * MDIO master + * UART * Primitives * Arbiter * Priority encoder diff --git a/rtl/lss/taxi_i2c_master.sv b/rtl/lss/taxi_i2c_master.sv new file mode 100644 index 0000000..9498acd --- /dev/null +++ b/rtl/lss/taxi_i2c_master.sv @@ -0,0 +1,896 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2015-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * I2C master + */ +module taxi_i2c_master ( + input wire logic clk, + input wire logic rst, + + /* + * Host interface + */ + taxi_axis_if.snk s_axis_cmd, + taxi_axis_if.snk s_axis_data, + taxi_axis_if.src m_axis_data, + + /* + * I2C interface + */ + input wire logic scl_i, + output wire logic scl_o, + output wire logic scl_t, + input wire logic sda_i, + output wire logic sda_o, + output wire logic sda_t, + + /* + * Status + */ + output wire logic busy, + output wire logic bus_control, + output wire logic bus_active, + output wire logic missed_ack, + + /* + * Configuration + */ + input wire logic [15:0] prescale, + input wire logic stop_on_idle +); + +/* + +I2C + +Read + __ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __ +sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_\_R___A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A____/ + ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____ +scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP + +Write + __ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __ +sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_/ W \_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_/ N \__/ + ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____ +scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP + +Command encoding: + + cmd[6:0] address + cmd[7] start + cmd[8] read + cmd[9] write + cmd[10] write_multiple + cmd[11] stop + +Commands: + +read + read data byte + set start to force generation of a start condition + start is implied when bus is inactive or active with write or different address + set stop to issue a stop condition after reading current byte + if stop is set with read command, then m_axis_data_tlast will be set + +write + write data byte + set start to force generation of a start condition + start is implied when bus is inactive or active with read or different address + set stop to issue a stop condition after writing current byte + +write multiple + write multiple data bytes (until s_axis_data_tlast) + set start to force generation of a start condition + start is implied when bus is inactive or active with read or different address + set stop to issue a stop condition after writing block + +stop + issue stop condition if bus is active + +Status: + +busy + module is communicating over the bus + +bus_control + module has control of bus in active state + +bus_active + bus is active, not necessarily controlled by this module + +missed_ack + strobed when a slave ack is missed + +Parameters: + +prescale + set prescale to 1/4 of the minimum clock period in units + of input clk cycles (prescale = Fclk / (FI2Cclk * 4)) + +stop_on_idle + automatically issue stop when command input is not valid + +Example of interfacing with tristate pins: +(this will work for any tristate bus) + +assign scl_i = scl_pin; +assign scl_pin = scl_t ? 1'bz : scl_o; +assign sda_i = sda_pin; +assign sda_pin = sda_t ? 1'bz : sda_o; + +Equivalent code that does not use *_t connections: +(we can get away with this because I2C is open-drain) + +assign scl_i = scl_pin; +assign scl_pin = scl_o ? 1'bz : 1'b0; +assign sda_i = sda_pin; +assign sda_pin = sda_o ? 1'bz : 1'b0; + +Example of two interconnected I2C devices: + +assign scl_1_i = scl_1_o & scl_2_o; +assign scl_2_i = scl_1_o & scl_2_o; +assign sda_1_i = sda_1_o & sda_2_o; +assign sda_2_i = sda_1_o & sda_2_o; + +Example of two I2C devices sharing the same pins: + +assign scl_1_i = scl_pin; +assign scl_2_i = scl_pin; +assign scl_pin = (scl_1_o & scl_2_o) ? 1'bz : 1'b0; +assign sda_1_i = sda_pin; +assign sda_2_i = sda_pin; +assign sda_pin = (sda_1_o & sda_2_o) ? 1'bz : 1'b0; + +Notes: + +scl_o should not be connected directly to scl_i, only via AND logic or a tristate +I/O pin. This would prevent devices from stretching the clock period. + +*/ + +localparam [3:0] + STATE_IDLE = 4'd0, + STATE_ACTIVE_WRITE = 4'd1, + STATE_ACTIVE_READ = 4'd2, + STATE_START_WAIT = 4'd3, + STATE_START = 4'd4, + STATE_ADDRESS_1 = 4'd5, + STATE_ADDRESS_2 = 4'd6, + STATE_WRITE_1 = 4'd7, + STATE_WRITE_2 = 4'd8, + STATE_WRITE_3 = 4'd9, + STATE_READ = 4'd10, + STATE_STOP = 4'd11; + +logic [3:0] state_reg = STATE_IDLE, state_next; + +localparam [3:0] + PHY_STATE_IDLE = 4'd0, + PHY_STATE_ACTIVE = 4'd1, + PHY_STATE_REPEATED_START_1 = 4'd2, + PHY_STATE_REPEATED_START_2 = 4'd3, + PHY_STATE_START_1 = 4'd4, + PHY_STATE_START_2 = 4'd5, + PHY_STATE_WRITE_BIT_1 = 4'd6, + PHY_STATE_WRITE_BIT_2 = 4'd7, + PHY_STATE_WRITE_BIT_3 = 4'd8, + PHY_STATE_READ_BIT_1 = 4'd9, + PHY_STATE_READ_BIT_2 = 4'd10, + PHY_STATE_READ_BIT_3 = 4'd11, + PHY_STATE_READ_BIT_4 = 4'd12, + PHY_STATE_STOP_1 = 4'd13, + PHY_STATE_STOP_2 = 4'd14, + PHY_STATE_STOP_3 = 4'd15; + +logic [3:0] phy_state_reg = STATE_IDLE, phy_state_next; + +logic phy_start_bit; +logic phy_stop_bit; +logic phy_write_bit; +logic phy_read_bit; +logic phy_release_bus; + +logic phy_tx_data; + +logic phy_rx_data_reg = 1'b0, phy_rx_data_next; + +logic [6:0] addr_reg = '0, addr_next; +logic [7:0] data_reg = '0, data_next; +logic last_reg = 1'b0, last_next; + +logic mode_read_reg = 1'b0, mode_read_next; +logic mode_write_multiple_reg = 1'b0, mode_write_multiple_next; +logic mode_stop_reg = 1'b0, mode_stop_next; + +logic [16:0] delay_reg = '0, delay_next; +logic delay_scl_reg = 1'b0, delay_scl_next; +logic delay_sda_reg = 1'b0, delay_sda_next; + +logic [3:0] bit_count_reg = '0, bit_count_next; + +logic s_axis_cmd_ready_reg = 1'b0, s_axis_cmd_ready_next; + +logic s_axis_data_tready_reg = 1'b0, s_axis_data_tready_next; + +logic [7:0] m_axis_data_tdata_reg = '0, m_axis_data_tdata_next; +logic m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next; +logic m_axis_data_tlast_reg = 1'b0, m_axis_data_tlast_next; + +logic scl_i_reg = 1'b1; +logic sda_i_reg = 1'b1; + +logic scl_o_reg = 1'b1, scl_o_next; +logic sda_o_reg = 1'b1, sda_o_next; + +logic last_scl_i_reg = 1'b1; +logic last_sda_i_reg = 1'b1; + +logic busy_reg = 1'b0; +logic bus_active_reg = 1'b0; +logic bus_control_reg = 1'b0, bus_control_next; +logic missed_ack_reg = 1'b0, missed_ack_next; + +wire [6:0] s_axis_cmd_address = s_axis_cmd.tdata[6:0]; +wire s_axis_cmd_start = s_axis_cmd.tdata[7]; +wire s_axis_cmd_read = s_axis_cmd.tdata[8]; +wire s_axis_cmd_write = s_axis_cmd.tdata[9]; +wire s_axis_cmd_write_multi = s_axis_cmd.tdata[10]; +wire s_axis_cmd_stop = s_axis_cmd.tdata[11]; + +assign s_axis_cmd.tready = s_axis_cmd_ready_reg; + +assign s_axis_data.tready = s_axis_data_tready_reg; + +assign m_axis_data.tdata = m_axis_data_tdata_reg; +assign m_axis_data.tkeep = '1; +assign m_axis_data.tstrb = m_axis_data.tkeep; +assign m_axis_data.tvalid = m_axis_data_tvalid_reg; +assign m_axis_data.tlast = m_axis_data_tlast_reg; +assign m_axis_data.tid = '0; +assign m_axis_data.tdest = '0; +assign m_axis_data.tuser = '0; + +assign scl_o = scl_o_reg; +assign scl_t = scl_o_reg; +assign sda_o = sda_o_reg; +assign sda_t = sda_o_reg; + +assign busy = busy_reg; +assign bus_active = bus_active_reg; +assign bus_control = bus_control_reg; +assign missed_ack = missed_ack_reg; + +wire scl_posedge = scl_i_reg && !last_scl_i_reg; +wire scl_negedge = !scl_i_reg && last_scl_i_reg; +wire sda_posedge = sda_i_reg && !last_sda_i_reg; +wire sda_negedge = !sda_i_reg && last_sda_i_reg; + +wire start_bit = sda_negedge && scl_i_reg; +wire stop_bit = sda_posedge && scl_i_reg; + +always_comb begin + state_next = STATE_IDLE; + + phy_start_bit = 1'b0; + phy_stop_bit = 1'b0; + phy_write_bit = 1'b0; + phy_read_bit = 1'b0; + phy_tx_data = 1'b0; + phy_release_bus = 1'b0; + + addr_next = addr_reg; + data_next = data_reg; + last_next = last_reg; + + mode_read_next = mode_read_reg; + mode_write_multiple_next = mode_write_multiple_reg; + mode_stop_next = mode_stop_reg; + + bit_count_next = bit_count_reg; + + s_axis_cmd_ready_next = 1'b0; + + s_axis_data_tready_next = 1'b0; + + m_axis_data_tdata_next = m_axis_data_tdata_reg; + m_axis_data_tvalid_next = m_axis_data_tvalid_reg && !m_axis_data.tready; + m_axis_data_tlast_next = m_axis_data_tlast_reg; + + missed_ack_next = 1'b0; + + // generate delays + if (phy_state_reg != PHY_STATE_IDLE && phy_state_reg != PHY_STATE_ACTIVE) begin + // wait for phy operation + state_next = state_reg; + end else begin + // process states + case (state_reg) + STATE_IDLE: begin + // line idle + s_axis_cmd_ready_next = 1'b1; + + if (s_axis_cmd.tready && s_axis_cmd.tvalid) begin + // command valid + if (s_axis_cmd_read ^ (s_axis_cmd_write || s_axis_cmd_write_multi)) begin + // read or write command + addr_next = s_axis_cmd_address; + mode_read_next = s_axis_cmd_read; + mode_write_multiple_next = s_axis_cmd_write_multi; + mode_stop_next = s_axis_cmd_stop; + + s_axis_cmd_ready_next = 1'b0; + + // start bit + if (bus_active) begin + state_next = STATE_START_WAIT; + end else begin + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end + end else begin + // invalid or unspecified - ignore + state_next = STATE_IDLE; + end + end else begin + state_next = STATE_IDLE; + end + end + STATE_ACTIVE_WRITE: begin + // line active with current address and read/write mode + s_axis_cmd_ready_next = 1'b1; + + if (s_axis_cmd.tready && s_axis_cmd.tvalid) begin + // command valid + if (s_axis_cmd_read ^ (s_axis_cmd_write || s_axis_cmd_write_multi)) begin + // read or write command + addr_next = s_axis_cmd_address; + mode_read_next = s_axis_cmd_read; + mode_write_multiple_next = s_axis_cmd_write_multi; + mode_stop_next = s_axis_cmd_stop; + + s_axis_cmd_ready_next = 1'b0; + + if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_read) begin + // address or mode mismatch or forced start - repeated start + + // repeated start bit + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end else begin + // address and mode match + + // start write + s_axis_data_tready_next = 1'b1; + state_next = STATE_WRITE_1; + end + end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multi)) begin + // stop command + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end else begin + // invalid or unspecified - ignore + state_next = STATE_ACTIVE_WRITE; + end + end else begin + if (stop_on_idle && s_axis_cmd.tready && !s_axis_cmd.tvalid) begin + // no waiting command and stop_on_idle selected, issue stop condition + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end else begin + state_next = STATE_ACTIVE_WRITE; + end + end + end + STATE_ACTIVE_READ: begin + // line active to current address + s_axis_cmd_ready_next = !m_axis_data.tvalid; + + if (s_axis_cmd.tready && s_axis_cmd.tvalid) begin + // command valid + if (s_axis_cmd_read ^ (s_axis_cmd_write || s_axis_cmd_write_multi)) begin + // read or write command + addr_next = s_axis_cmd_address; + mode_read_next = s_axis_cmd_read; + mode_write_multiple_next = s_axis_cmd_write_multi; + mode_stop_next = s_axis_cmd_stop; + + s_axis_cmd_ready_next = 1'b0; + + if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_write) begin + // address or mode mismatch or forced start - repeated start + + // write nack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + // repeated start bit + state_next = STATE_START; + end else begin + // address and mode match + + // write ack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b0; + // start next read + bit_count_next = 4'd8; + data_next = 8'd0; + state_next = STATE_READ; + end + end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multi)) begin + // stop command + // write nack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + // send stop bit + state_next = STATE_STOP; + end else begin + // invalid or unspecified - ignore + state_next = STATE_ACTIVE_READ; + end + end else begin + if (stop_on_idle && s_axis_cmd.tready && !s_axis_cmd.tvalid) begin + // no waiting command and stop_on_idle selected, issue stop condition + // write ack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + // send stop bit + state_next = STATE_STOP; + end else begin + state_next = STATE_ACTIVE_READ; + end + end + end + STATE_START_WAIT: begin + // wait for bus idle + + if (bus_active) begin + state_next = STATE_START_WAIT; + end else begin + // bus is idle, take control + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end + end + STATE_START: begin + // send start bit + + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end + STATE_ADDRESS_1: begin + // send address + bit_count_next = bit_count_reg - 1; + if (bit_count_reg > 1) begin + // send address + phy_write_bit = 1'b1; + phy_tx_data = addr_reg[bit_count_reg-2]; + state_next = STATE_ADDRESS_1; + end else if (bit_count_reg != 0) begin + // send read/write bit + phy_write_bit = 1'b1; + phy_tx_data = mode_read_reg; + state_next = STATE_ADDRESS_1; + end else begin + // read ack bit + phy_read_bit = 1'b1; + state_next = STATE_ADDRESS_2; + end + end + STATE_ADDRESS_2: begin + // read ack bit + missed_ack_next = phy_rx_data_reg; + + if (mode_read_reg) begin + // start read + bit_count_next = 4'd8; + state_next = STATE_READ; + end else begin + // start write + s_axis_data_tready_next = 1'b1; + state_next = STATE_WRITE_1; + end + end + STATE_WRITE_1: begin + s_axis_data_tready_next = 1'b1; + + if (s_axis_data.tready && s_axis_data.tvalid) begin + // got data, start write + data_next = s_axis_data.tdata; + last_next = s_axis_data.tlast; + bit_count_next = 4'd8; + s_axis_data_tready_next = 1'b0; + state_next = STATE_WRITE_2; + end else begin + // wait for data + state_next = STATE_WRITE_1; + end + end + STATE_WRITE_2: begin + // send data + bit_count_next = bit_count_reg - 1; + if (bit_count_reg != 0) begin + // write data bit + phy_write_bit = 1'b1; + phy_tx_data = data_reg[bit_count_reg-1]; + state_next = STATE_WRITE_2; + end else begin + // read ack bit + phy_read_bit = 1'b1; + state_next = STATE_WRITE_3; + end + end + STATE_WRITE_3: begin + // read ack bit + missed_ack_next = phy_rx_data_reg; + + if (mode_write_multiple_reg && !last_reg) begin + // more to write + state_next = STATE_WRITE_1; + end else if (mode_stop_reg) begin + // last cycle and stop selected + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end else begin + // otherwise, return to bus active state + state_next = STATE_ACTIVE_WRITE; + end + end + STATE_READ: begin + // read data + + bit_count_next = bit_count_reg - 1; + data_next = {data_reg[6:0], phy_rx_data_reg}; + if (bit_count_reg != 0) begin + // read next bit + phy_read_bit = 1'b1; + state_next = STATE_READ; + end else begin + // output data word + m_axis_data_tdata_next = data_next; + m_axis_data_tvalid_next = 1'b1; + m_axis_data_tlast_next = 1'b0; + if (mode_stop_reg) begin + // send nack and stop + m_axis_data_tlast_next = 1'b1; + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + state_next = STATE_STOP; + end else begin + // return to bus active state + state_next = STATE_ACTIVE_READ; + end + end + end + STATE_STOP: begin + // send stop bit + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end + default: begin + state_next = STATE_IDLE; + end + endcase + end +end + +always_comb begin + phy_state_next = PHY_STATE_IDLE; + + phy_rx_data_next = phy_rx_data_reg; + + delay_next = delay_reg; + delay_scl_next = delay_scl_reg; + delay_sda_next = delay_sda_reg; + + scl_o_next = scl_o_reg; + sda_o_next = sda_o_reg; + + bus_control_next = bus_control_reg; + + if (phy_release_bus) begin + // release bus and return to idle state + sda_o_next = 1'b1; + scl_o_next = 1'b1; + delay_scl_next = 1'b0; + delay_sda_next = 1'b0; + delay_next = '0; + phy_state_next = PHY_STATE_IDLE; + end else if (delay_scl_reg) begin + // wait for SCL to match command + delay_scl_next = scl_o_reg && !scl_i_reg; + phy_state_next = phy_state_reg; + end else if (delay_sda_reg) begin + // wait for SDA to match command + delay_sda_next = sda_o_reg && !sda_i_reg; + phy_state_next = phy_state_reg; + end else if (delay_reg != 0) begin + // time delay + delay_next = delay_reg - 1; + phy_state_next = phy_state_reg; + end else begin + case (phy_state_reg) + PHY_STATE_IDLE: begin + // bus idle - wait for start command + sda_o_next = 1'b1; + scl_o_next = 1'b1; + if (phy_start_bit) begin + sda_o_next = 1'b0; + delay_next = 17'(prescale); + phy_state_next = PHY_STATE_START_1; + end else begin + phy_state_next = PHY_STATE_IDLE; + end + end + PHY_STATE_ACTIVE: begin + // bus active + if (phy_start_bit) begin + sda_o_next = 1'b1; + delay_next = 17'(prescale); + phy_state_next = PHY_STATE_REPEATED_START_1; + end else if (phy_write_bit) begin + sda_o_next = phy_tx_data; + delay_next = 17'(prescale); + phy_state_next = PHY_STATE_WRITE_BIT_1; + end else if (phy_read_bit) begin + sda_o_next = 1'b1; + delay_next = 17'(prescale); + phy_state_next = PHY_STATE_READ_BIT_1; + end else if (phy_stop_bit) begin + sda_o_next = 1'b0; + delay_next = 17'(prescale); + phy_state_next = PHY_STATE_STOP_1; + end else begin + phy_state_next = PHY_STATE_ACTIVE; + end + end + PHY_STATE_REPEATED_START_1: begin + // generate repeated start bit + // ______ + // sda XXX/ \_______ + // _______ + // scl ______/ \___ + // + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = 17'(prescale); + phy_state_next = PHY_STATE_REPEATED_START_2; + end + PHY_STATE_REPEATED_START_2: begin + // generate repeated start bit + // ______ + // sda XXX/ \_______ + // _______ + // scl ______/ \___ + // + + sda_o_next = 1'b0; + delay_next = 17'(prescale); + phy_state_next = PHY_STATE_START_1; + end + PHY_STATE_START_1: begin + // generate start bit + // ___ + // sda \_______ + // _______ + // scl \___ + // + + scl_o_next = 1'b0; + delay_next = 17'(prescale); + phy_state_next = PHY_STATE_START_2; + end + PHY_STATE_START_2: begin + // generate start bit + // ___ + // sda \_______ + // _______ + // scl \___ + // + + bus_control_next = 1'b1; + phy_state_next = PHY_STATE_ACTIVE; + end + PHY_STATE_WRITE_BIT_1: begin + // write bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = 17'(prescale); + phy_state_next = PHY_STATE_WRITE_BIT_2; + end + PHY_STATE_WRITE_BIT_2: begin + // write bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b0; + delay_next = 17'(prescale); + phy_state_next = PHY_STATE_WRITE_BIT_3; + end + PHY_STATE_WRITE_BIT_3: begin + // write bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + phy_state_next = PHY_STATE_ACTIVE; + end + PHY_STATE_READ_BIT_1: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = 17'(prescale); + phy_state_next = PHY_STATE_READ_BIT_2; + end + PHY_STATE_READ_BIT_2: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + phy_rx_data_next = sda_i_reg; + delay_next = 17'(prescale); + phy_state_next = PHY_STATE_READ_BIT_3; + end + PHY_STATE_READ_BIT_3: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b0; + delay_next = 17'(prescale); + phy_state_next = PHY_STATE_READ_BIT_4; + end + PHY_STATE_READ_BIT_4: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + phy_state_next = PHY_STATE_ACTIVE; + end + PHY_STATE_STOP_1: begin + // stop bit + // ___ + // sda XXX\_______/ + // _______ + // scl _______/ + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = 17'(prescale); + phy_state_next = PHY_STATE_STOP_2; + end + PHY_STATE_STOP_2: begin + // stop bit + // ___ + // sda XXX\_______/ + // _______ + // scl _______/ + + sda_o_next = 1'b1; + delay_next = 17'(prescale); + phy_state_next = PHY_STATE_STOP_3; + end + PHY_STATE_STOP_3: begin + // stop bit + // ___ + // sda XXX\_______/ + // _______ + // scl _______/ + + bus_control_next = 1'b0; + phy_state_next = PHY_STATE_IDLE; + end + default: begin + phy_state_next = PHY_STATE_IDLE; + end + endcase + end +end + +always_ff @(posedge clk) begin + state_reg <= state_next; + phy_state_reg <= phy_state_next; + + phy_rx_data_reg <= phy_rx_data_next; + + addr_reg <= addr_next; + data_reg <= data_next; + last_reg <= last_next; + + mode_read_reg <= mode_read_next; + mode_write_multiple_reg <= mode_write_multiple_next; + mode_stop_reg <= mode_stop_next; + + delay_reg <= delay_next; + delay_scl_reg <= delay_scl_next; + delay_sda_reg <= delay_sda_next; + + bit_count_reg <= bit_count_next; + + s_axis_cmd_ready_reg <= s_axis_cmd_ready_next; + + s_axis_data_tready_reg <= s_axis_data_tready_next; + + m_axis_data_tdata_reg <= m_axis_data_tdata_next; + m_axis_data_tlast_reg <= m_axis_data_tlast_next; + m_axis_data_tvalid_reg <= m_axis_data_tvalid_next; + + scl_i_reg <= scl_i; + sda_i_reg <= sda_i; + + scl_o_reg <= scl_o_next; + sda_o_reg <= sda_o_next; + + last_scl_i_reg <= scl_i_reg; + last_sda_i_reg <= sda_i_reg; + + busy_reg <= !(state_reg == STATE_IDLE || state_reg == STATE_ACTIVE_WRITE || state_reg == STATE_ACTIVE_READ) || !(phy_state_reg == PHY_STATE_IDLE || phy_state_reg == PHY_STATE_ACTIVE); + + if (start_bit) begin + bus_active_reg <= 1'b1; + end else if (stop_bit) begin + bus_active_reg <= 1'b0; + end else begin + bus_active_reg <= bus_active_reg; + end + + bus_control_reg <= bus_control_next; + missed_ack_reg <= missed_ack_next; + + if (rst) begin + state_reg <= STATE_IDLE; + phy_state_reg <= PHY_STATE_IDLE; + delay_reg <= '0; + delay_scl_reg <= 1'b0; + delay_sda_reg <= 1'b0; + s_axis_cmd_ready_reg <= 1'b0; + s_axis_data_tready_reg <= 1'b0; + m_axis_data_tvalid_reg <= 1'b0; + scl_o_reg <= 1'b1; + sda_o_reg <= 1'b1; + busy_reg <= 1'b0; + bus_active_reg <= 1'b0; + bus_control_reg <= 1'b0; + missed_ack_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/tb/lss/taxi_i2c_master/Makefile b/tb/lss/taxi_i2c_master/Makefile new file mode 100644 index 0000000..22f9985 --- /dev/null +++ b/tb/lss/taxi_i2c_master/Makefile @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ns + +DUT = taxi_i2c_master +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += ../../../rtl/lss/$(DUT).sv +VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +# export PARAM_DEFAULT_PRESCALE := 1 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/tb/lss/taxi_i2c_master/test_taxi_i2c_master.py b/tb/lss/taxi_i2c_master/test_taxi_i2c_master.py new file mode 100644 index 0000000..fc919f7 --- /dev/null +++ b/tb/lss/taxi_i2c_master/test_taxi_i2c_master.py @@ -0,0 +1,189 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import logging +import os + +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, FallingEdge +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiStreamSource, AxiStreamSink, AxiStreamBus +from cocotbext.i2c import I2cMemory + + +CMD_START = 1 << 7 +CMD_READ = 1 << 8 +CMD_WRITE = 1 << 9 +CMD_WRITE_MULTI = 1 << 10 +CMD_STOP = 1 << 11 + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.fork(Clock(dut.clk, 8, units="ns").start()) + + self.cmd_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_cmd), dut.clk, dut.rst) + + self.data_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_data), dut.clk, dut.rst) + self.data_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_data), dut.clk, dut.rst) + + self.i2c_memory = I2cMemory(sda=dut.sda_o, sda_o=dut.sda_i, + scl=dut.scl_o, scl_o=dut.scl_i, addr=0x50, size=1024) + + dut.prescale.setimmediatevalue(2) + dut.stop_on_idle.setimmediatevalue(0) + + async def reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + async def i2c_write_data(self, addr, data, start=0, stop=0): + cmd = CMD_WRITE_MULTI | addr + if start: + cmd |= CMD_START + if stop: + cmd |= CMD_STOP + await self.cmd_source.send([cmd]) + await self.data_source.send(data) + await self.data_source.wait() + await self.i2c_wait() + + async def i2c_read_data(self, addr, count, start=0, stop=0): + for k in range(count): + cmd = CMD_READ | addr + if start and k == 0: + cmd |= CMD_START + if stop and k == count-1: + cmd |= CMD_STOP + await self.cmd_source.send([cmd]) + return (await self.data_sink.recv()).tdata + + async def i2c_wait(self): + if self.dut.busy.value.integer: + await FallingEdge(self.dut.busy) + + async def i2c_wait_bus_idle(self): + if self.dut.bus_active.value.integer: + await FallingEdge(self.dut.bus_active) + + +async def run_test(dut, payload_lengths=None, payload_data=None): + + tb = TB(dut) + + await tb.reset() + + tb.log.info("Test write") + + test_data = b'\x11\x22\x33\x44' + + await tb.i2c_write_data(0x50, b'\x00\x04'+test_data, stop=1) + await tb.i2c_wait_bus_idle() + + data = tb.i2c_memory.read_mem(4, 4) + + tb.log.info("Read data: %s", data) + + assert data == test_data + + # assert not missed ack + + tb.log.info("Test read") + + await tb.i2c_write_data(0x50, b'\x00\x04') + read_data = await tb.i2c_read_data(0x50, 4, start=1, stop=1) + + tb.log.info("Read data: %s", read_data) + + assert read_data == test_data + + # assert not missed ack + + tb.log.info("Test write to nonexistent device") + + await tb.i2c_write_data(0x55, b'\x00\x04'+b'\xde\xad\xbe\xef', stop=1) + await tb.i2c_wait_bus_idle() + + # assert missed ack + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +if cocotb.SIM_NAME: + + factory = TestFactory(run_test) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +def test_taxi_i2c_master(request): + dut = "taxi_i2c_master" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, "lss", f"{dut}.sv"), + os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + ] + + parameters = {} + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/tb/lss/taxi_i2c_master/test_taxi_i2c_master.sv b/tb/lss/taxi_i2c_master/test_taxi_i2c_master.sv new file mode 100644 index 0000000..e16138b --- /dev/null +++ b/tb/lss/taxi_i2c_master/test_taxi_i2c_master.sv @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * I2C master testbench + */ +module test_taxi_i2c_master +(); + +logic clk; +logic rst; + +taxi_axis_if #(.DATA_W(12), .KEEP_W(1)) s_axis_cmd(); +taxi_axis_if #(.DATA_W(8)) s_axis_data(); +taxi_axis_if #(.DATA_W(8)) m_axis_data(); + +logic scl_i; +logic scl_o; +logic scl_t; +logic sda_i; +logic sda_o; +logic sda_t; + +logic busy; +logic bus_control; +logic bus_active; +logic missed_ack; + +logic [15:0] prescale; +logic stop_on_idle; + +taxi_i2c_master +uut ( + .clk(clk), + .rst(rst), + + /* + * Host interface + */ + .s_axis_cmd(s_axis_cmd), + .s_axis_data(s_axis_data), + .m_axis_data(m_axis_data), + + /* + * I2C interface + */ + .scl_i(scl_i), + .scl_o(scl_o), + .scl_t(scl_t), + .sda_i(sda_i), + .sda_o(sda_o), + .sda_t(sda_t), + + /* + * Status + */ + .busy(busy), + .bus_control(bus_control), + .bus_active(bus_active), + .missed_ack(missed_ack), + + /* + * Configuration + */ + .prescale(prescale), + .stop_on_idle(stop_on_idle) +); + +endmodule + +`resetall