diff --git a/src/eth/example/KC705/fpga/fpga.xdc b/src/eth/example/KC705/fpga/fpga.xdc index c5cc284..7ab5cc3 100644 --- a/src/eth/example/KC705/fpga/fpga.xdc +++ b/src/eth/example/KC705/fpga/fpga.xdc @@ -80,9 +80,9 @@ set_false_path -from [get_ports {uart_rxd uart_rts}] set_input_delay 0 [get_ports {uart_rxd uart_rts}] # I2C interface -#set_property -dict {LOC K21 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_scl] -#set_property -dict {LOC L21 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_sda] -#set_property -dict {LOC P23 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset] +set_property -dict {LOC K21 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_scl] +set_property -dict {LOC L21 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_sda] +set_property -dict {LOC P23 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset] #set_false_path -to [get_ports {i2c_sda i2c_scl}] #set_output_delay 0 [get_ports {i2c_sda i2c_scl}] @@ -140,17 +140,28 @@ set_property -dict {LOC H6 } [get_ports phy_sgmii_rx_p] ;# MGTXRXP1_117 GTXE2_ set_property -dict {LOC H5 } [get_ports phy_sgmii_rx_n] ;# MGTXRXN1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A8 SOUT_N set_property -dict {LOC J4 } [get_ports phy_sgmii_tx_p] ;# MGTXTXP1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A3 SIN_P set_property -dict {LOC J3 } [get_ports phy_sgmii_tx_n] ;# MGTXTXN1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A4 SIN_N -set_property -dict {LOC G8 } [get_ports sgmii_clk_p] ;# MGTREFCLK0P_117 from U2.7 -set_property -dict {LOC G7 } [get_ports sgmii_clk_n] ;# MGTREFCLK0N_117 from U2.6 -#set_property -dict {LOC L8 } [get_ports sfp_clk_p] ;# MGTREFCLK0P_116 from Si5324 U70.28 CKOUT1_P -#set_property -dict {LOC L7 } [get_ports sfp_clk_n] ;# MGTREFCLK0N_116 from Si5324 U70.29 CKOUT1_N +set_property -dict {LOC G8 } [get_ports sgmii_mgt_refclk_p] ;# MGTREFCLK0P_117 from U2.7 +set_property -dict {LOC G7 } [get_ports sgmii_mgt_refclk_n] ;# MGTREFCLK0N_117 from U2.6 +#set_property -dict {LOC L8 } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_116 from Si5324 U70.28 CKOUT1_P +#set_property -dict {LOC L7 } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_116 from Si5324 U70.29 CKOUT1_N #set_property -dict {LOC W27 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to Si5324 U70.16 CKIN1_P #set_property -dict {LOC W28 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to Si5324 U70.17 CKIN1_N +#set_property -dict {LOC AE20 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports si5324_rst] +#set_property -dict {LOC AG24 IOSTANDARD LVCMOS25 PULLUP true} [get_ports si5324_int] + set_property -dict {LOC Y20 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable_b}] -create_clock -period 8.000 -name sgmii_clk [get_ports sgmii_clk_p] -#create_clock -period 6.400 -name sgmii_clk [get_ports sfp_clk_p] +# 125 MHz MGT reference clock (SGMII, 1000BASE-X) +#create_clock -period 8.000 -name sgmii_mgt_refclk [get_ports sgmii_mgt_refclk_p] + +# 156.25 MHz MGT reference clock (10GBASE-R) +#create_clock -period 6.400 -name sgmii_mgt_refclk [get_ports sfp_mgt_refclk_p] + +#set_false_path -to [get_ports {si5324_rst}] +#set_output_delay 0 [get_ports {si5324_rst}] +#set_false_path -from [get_ports {si5324_int}] +#set_input_delay 0 [get_ports {si5324_int}] set_false_path -to [get_ports {sfp_tx_disable_b}] set_output_delay 0 [get_ports {sfp_tx_disable_b}] diff --git a/src/eth/example/KC705/fpga/fpga_gmii_1g/Makefile b/src/eth/example/KC705/fpga/fpga_gmii_1g/Makefile index 98fd70d..19607f0 100644 --- a/src/eth/example/KC705/fpga/fpga_gmii_1g/Makefile +++ b/src/eth/example/KC705/fpga/fpga_gmii_1g/Makefile @@ -22,6 +22,7 @@ SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_gmii_fifo.f SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv diff --git a/src/eth/example/KC705/fpga/fpga_rgmii_1g/Makefile b/src/eth/example/KC705/fpga/fpga_rgmii_1g/Makefile index 3348903..06f95da 100644 --- a/src/eth/example/KC705/fpga/fpga_rgmii_1g/Makefile +++ b/src/eth/example/KC705/fpga/fpga_rgmii_1g/Makefile @@ -22,6 +22,7 @@ SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv diff --git a/src/eth/example/KC705/fpga/fpga_sgmii_1g/Makefile b/src/eth/example/KC705/fpga/fpga_sgmii_1g/Makefile index 3107772..6167a8a 100644 --- a/src/eth/example/KC705/fpga/fpga_sgmii_1g/Makefile +++ b/src/eth/example/KC705/fpga/fpga_sgmii_1g/Makefile @@ -21,6 +21,7 @@ SYN_FILES += $(RTL_DIR)/fpga_core.sv SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv diff --git a/src/eth/example/KC705/fpga/rtl/fpga.sv b/src/eth/example/KC705/fpga/rtl/fpga.sv index 0f29b93..c371f74 100644 --- a/src/eth/example/KC705/fpga/rtl/fpga.sv +++ b/src/eth/example/KC705/fpga/rtl/fpga.sv @@ -58,6 +58,13 @@ module fpga # input wire logic uart_rts, output wire logic uart_cts, + /* + * I2C + */ + inout wire logic i2c_scl, + inout wire logic i2c_sda, + output wire logic i2c_mux_reset, + /* * Ethernet: SFP+ */ @@ -69,8 +76,8 @@ module fpga # input wire logic phy_sgmii_rx_n, output wire logic phy_sgmii_tx_p, output wire logic phy_sgmii_tx_n, - input wire logic sgmii_clk_p, - input wire logic sgmii_clk_n, + input wire logic sgmii_mgt_refclk_p, + input wire logic sgmii_mgt_refclk_n, output wire logic sfp_tx_disable_b, @@ -265,6 +272,17 @@ sync_signal_inst ( wire [7:0] led_int; +// I2C +wire i2c_scl_i; +wire i2c_scl_o; +wire i2c_sda_i; +wire i2c_sda_o; + +assign i2c_scl_i = i2c_scl; +assign i2c_scl = i2c_scl_o ? 1'bz : 1'b0; +assign i2c_sda_i = i2c_sda; +assign i2c_sda = i2c_sda_o ? 1'bz : 1'b0; + // SGMII interface to PHY wire phy_sgmii_clk_int; wire phy_sgmii_rst_int; @@ -338,8 +356,8 @@ assign sgmii_an_config_vect[0] = 1'b1; // SGMII sgmii_pcs_pma_0 sgmii_pcspma ( // Transceiver Interface - .gtrefclk_p (sgmii_clk_p), - .gtrefclk_n (sgmii_clk_n), + .gtrefclk_p (sgmii_mgt_refclk_p), + .gtrefclk_n (sgmii_mgt_refclk_n), .gtrefclk_out (sgmii_gtrefclk), .gtrefclk_bufg_out (sgmii_gtrefclk_bufg), .txp (phy_sgmii_tx_p), @@ -554,7 +572,7 @@ if (BASET_PHY_TYPE == "RGMII") begin : phy_if ); for (genvar n = 0; n < 4; n = n + 1) begin : phy_rxd_idelay_bit - + IDELAYE2 #( .IDELAY_TYPE("FIXED") ) @@ -661,6 +679,14 @@ core_inst ( .uart_rts(uart_rts_int), .uart_cts(uart_cts), + /* + * I2C + */ + .i2c_scl_i(i2c_scl_i), + .i2c_scl_o(i2c_scl_o), + .i2c_sda_i(i2c_sda_i), + .i2c_sda_o(i2c_sda_o), + /* * Ethernet: 1000BASE-X SFP */ diff --git a/src/eth/example/KC705/fpga/rtl/fpga_core.sv b/src/eth/example/KC705/fpga/rtl/fpga_core.sv index 555bde7..b72b60e 100644 --- a/src/eth/example/KC705/fpga/rtl/fpga_core.sv +++ b/src/eth/example/KC705/fpga/rtl/fpga_core.sv @@ -58,6 +58,14 @@ module fpga_core # input wire logic uart_rts, output wire logic uart_cts, + /* + * I2C + */ + input wire logic i2c_scl_i, + output wire logic i2c_scl_o, + input wire logic i2c_sda_i, + output wire logic i2c_sda_o, + /* * Ethernet: 1000BASE-X SFP */ @@ -136,7 +144,7 @@ xfcp_if_uart_inst ( .prescale(16'(125000000/921600)) ); -taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1](); +taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[2](), xfcp_sw_us[2](); taxi_xfcp_switch #( .XFCP_ID_STR("KC705"), @@ -209,6 +217,30 @@ stat_mux_inst ( .m_axis(axis_stat) ); +// I2C +taxi_xfcp_mod_i2c_master #( + .XFCP_EXT_ID_STR("I2C"), + .DEFAULT_PRESCALE(16'(125000000/200000/4)) +) +xfcp_mod_i2c_inst ( + .clk(clk), + .rst(rst), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_sw_ds[1]), + .xfcp_usp_us(xfcp_sw_us[1]), + + /* + * I2C interface + */ + .i2c_scl_i(i2c_scl_i), + .i2c_scl_o(i2c_scl_o), + .i2c_sda_i(i2c_sda_i), + .i2c_sda_o(i2c_sda_o) +); + // BASE-T PHY assign phy_reset_n = !rst; diff --git a/src/eth/example/KC705/fpga/tb/fpga_core/Makefile b/src/eth/example/KC705/fpga/tb/fpga_core/Makefile index 37a4dd4..6b9a12a 100644 --- a/src/eth/example/KC705/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/KC705/fpga/tb/fpga_core/Makefile @@ -28,6 +28,7 @@ VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_gmii_fifo.f VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv diff --git a/src/eth/example/KC705/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/KC705/fpga/tb/fpga_core/test_fpga_core.py index 253ea88..8225486 100644 --- a/src/eth/example/KC705/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/KC705/fpga/tb/fpga_core/test_fpga_core.py @@ -150,20 +150,22 @@ async def run_test(dut): await tb.init() + tests = [] + tb.log.info("Start BASE-T MAC loopback test") if hasattr(dut, "baset_mac_gmii"): - baset_test_cr = cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx)) + tests.append(cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx))) elif hasattr(dut, "baset_mac_rgmii"): - baset_test_cr = cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx)) + tests.append(cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx))) elif hasattr(dut, "baset_mac_sgmii"): - baset_test_cr = cocotb.start_soon(mac_test(tb, tb.sgmii_source, tb.sgmii_sink)) + tests.append(cocotb.start_soon(mac_test(tb, tb.sgmii_source, tb.sgmii_sink))) tb.log.info("Start SFP MAC loopback test") - sfp_test_cr = cocotb.start_soon(mac_test(tb, tb.sfp_source, tb.sfp_sink)) + tests.append(cocotb.start_soon(mac_test(tb, tb.sfp_source, tb.sfp_sink))) - await Combine(baset_test_cr, sfp_test_cr) + await Combine(*tests) await RisingEdge(dut.clk) await RisingEdge(dut.clk) @@ -203,6 +205,7 @@ def test_fpga_core(request, phy_type): os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_rgmii_fifo.f"), os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_i2c_master.f"), os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"), os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),