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lss: Add I2C slave AXI lite master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
467
src/lss/rtl/taxi_i2c_slave_axil_master.sv
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467
src/lss/rtl/taxi_i2c_slave_axil_master.sv
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2019-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* I2C slave AXI lite master wrapper
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*/
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module taxi_i2c_slave_axil_master #
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(
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parameter FILTER_LEN = 4
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* I2C interface
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*/
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input wire logic i2c_scl_i,
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output wire logic i2c_scl_o,
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input wire logic i2c_sda_i,
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output wire logic i2c_sda_o,
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/*
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* AXI4-Lite master interface
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*/
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taxi_axil_if.wr_mst m_axil_wr,
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taxi_axil_if.rd_mst m_axil_rd,
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/*
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* Status
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*/
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output wire logic busy,
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output wire logic [6:0] bus_address,
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output wire logic bus_addressed,
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output wire logic bus_active,
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/*
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* Configuration
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*/
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input wire logic enable,
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input wire logic [6:0] device_address
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);
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/*
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I2C
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Read
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__ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
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sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_/ R \_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_/ N \__/
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____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
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scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP
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Write
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__ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
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sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_\_W___A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A____/
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____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
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scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP
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Operation:
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This module enables I2C control over an AXI lite bus, useful for enabling a
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design to operate as a peripheral to an external microcontroller or similar.
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The AXI lite interface are fully parametrizable, with the restriction that the
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bus must be divided into 2**m words of 8*2**n bits.
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Writing via I2C first accesses an internal address register, followed by the
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actual AXI lite bus. The first k bytes go to the address register, where
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k = ceil(log2(ADDR_W+log2(DATA_W/SELECT_W))/8)
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. The address pointer will automatically increment with reads and writes.
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For buses with word size > 8 bits, the address register is in bytes and
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unaligned writes will be padded with zeros. Writes to the same bus address in
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the same I2C transaction are coalesced and written either once a complete
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word is ready or when the I2C transaction terminates with a stop or repeated
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start.
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Reading via the I2C interface immediately starts reading from the AXI lite
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interface starting from the current value of the internal address register.
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Like writes, reads are also coalesced when possible. One AXI lite read is
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performed on the first I2C read. Once that has been completely transferred
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out, another read will be performed on the start of the next I2C read
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operation.
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Read
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
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|_|_|_|_|_|_|_|_| |_|_|_|_|_|_|_|_|_|_ ... _|_|_|_|_|_|_|_|_|_| |_|_|_|_|_|_|_|_|___|_|_|_|_|_|_|_|_|_ ... _|_|_|_|_|_|_|_|_| |_|
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ST Device Addr W A Address MSB A Address LSB A RS Device Addr R A Data byte 0 A Data byte N N SP
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Write
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
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|_|_|_|_|_|_|_|_| |_|_|_|_|_|_|_|_|_|_ ... _|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_ ... _|_|_|_|_|_|_|_|_|___|
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ST Device Addr W A Address MSB A Address LSB A Data byte 0 A Data byte N A SP
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Status:
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busy
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module is communicating over the bus
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bus_control
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module has control of bus in active state
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bus_active
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bus is active, not necessarily controlled by this module
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Parameters:
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device_address
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address of slave device
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Example of interfacing with tristate pins:
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assign scl_i = scl_pin;
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assign scl_pin = scl_o ? 1'bz : 1'b0;
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assign sda_i = sda_pin;
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assign sda_pin = sda_o ? 1'bz : 1'b0;
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Example of two interconnected internal I2C devices:
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assign scl_1_i = scl_1_o & scl_2_o;
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assign scl_2_i = scl_1_o & scl_2_o;
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assign sda_1_i = sda_1_o & sda_2_o;
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assign sda_2_i = sda_1_o & sda_2_o;
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Example of two I2C devices sharing the same pins:
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assign scl_1_i = scl_pin;
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assign scl_2_i = scl_pin;
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assign scl_pin = (scl_1_o & scl_2_o) ? 1'bz : 1'b0;
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assign sda_1_i = sda_pin;
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assign sda_2_i = sda_pin;
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assign sda_pin = (sda_1_o & sda_2_o) ? 1'bz : 1'b0;
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Notes:
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scl_o should not be connected directly to scl_i, only via AND logic or a tristate
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I/O pin. This would prevent devices from stretching the clock period.
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*/
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// TODO REMOVE THIS
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/* verilator lint_off WIDTHTRUNC */
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localparam DATA_W = m_axil_wr.DATA_W;
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localparam ADDR_W = m_axil_wr.ADDR_W;
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localparam STRB_W = m_axil_wr.STRB_W;
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// for interfaces that are more than one word wide, disable address lines
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localparam VALID_ADDR_W = ADDR_W - $clog2(STRB_W);
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// width of data port in words
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localparam BYTE_LANES = STRB_W;
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// size of words
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localparam BYTE_SIZE = DATA_W/BYTE_LANES;
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localparam WORD_PART_ADDR_W = $clog2(BYTE_SIZE/8);
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localparam ADDR_W_ADJ = ADDR_W+WORD_PART_ADDR_W;
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localparam ADDR_WORD_W = (ADDR_W_ADJ+7)/8;
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// check configuration
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if (BYTE_LANES * BYTE_SIZE != DATA_W)
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$fatal(0, "Error: AXI data width not evenly divisible (instance %m)");
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if (2**$clog2(BYTE_LANES) != BYTE_LANES)
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$fatal(0, "Error: AXI word width must be even power of two (instance %m)");
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if (8*2**$clog2(BYTE_SIZE/8) != BYTE_SIZE)
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$fatal(0, "Error: AXI word size must be a power of two multiple of 8 bits (instance %m)");
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localparam [2:0]
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STATE_IDLE = 3'd0,
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STATE_ADDRESS = 3'd1,
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STATE_READ_1 = 3'd2,
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STATE_READ_2 = 3'd3,
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STATE_WRITE_1 = 3'd4,
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STATE_WRITE_2 = 3'd5;
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logic [2:0] state_reg = STATE_IDLE, state_next;
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logic [7:0] count_reg = '0, count_next;
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logic last_cycle_reg = 1'b0;
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logic [ADDR_W_ADJ-1:0] addr_reg = '0, addr_next;
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logic [DATA_W-1:0] data_reg = '0, data_next;
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logic m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
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logic [STRB_W-1:0] m_axil_wstrb_reg = '0, m_axil_wstrb_next;
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logic m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
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logic m_axil_bready_reg = 1'b0, m_axil_bready_next;
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logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
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logic m_axil_rready_reg = 1'b0, m_axil_rready_next;
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logic busy_reg = 1'b0;
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taxi_axis_if #(.DATA_W(8)) data_in();
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taxi_axis_if #(.DATA_W(8)) data_out();
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logic [7:0] data_in_reg = '0, data_in_next;
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logic data_in_valid_reg = 1'b0, data_in_valid_next;
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assign data_in.tdata = data_in_reg;
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assign data_in.tvalid = data_in_valid_reg;
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assign data_in.tlast = 1'b1;
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assign data_in.tid = '0;
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assign data_in.tdest = '0;
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assign data_in.tuser = '0;
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logic data_out_ready_reg = 1'b0, data_out_ready_next;
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assign data_out.tready = data_out_ready_reg;
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assign m_axil_wr.awaddr = addr_reg;
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assign m_axil_wr.awprot = 3'b010;
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assign m_axil_wr.awvalid = m_axil_awvalid_reg;
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assign m_axil_wr.wdata = data_reg;
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assign m_axil_wr.wstrb = m_axil_wstrb_reg;
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assign m_axil_wr.wvalid = m_axil_wvalid_reg;
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assign m_axil_wr.bready = m_axil_bready_reg;
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assign m_axil_rd.araddr = addr_reg;
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assign m_axil_rd.arprot = 3'b010;
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assign m_axil_rd.arvalid = m_axil_arvalid_reg;
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assign m_axil_rd.rready = m_axil_rready_reg;
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assign busy = busy_reg;
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always_comb begin
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state_next = STATE_IDLE;
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count_next = count_reg;
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data_in_next = data_in_reg;
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data_in_valid_next = data_in_valid_reg && !data_in.tready;
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data_out_ready_next = 1'b0;
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addr_next = addr_reg;
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data_next = data_reg;
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m_axil_awvalid_next = m_axil_awvalid_reg && !m_axil_wr.awready;
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m_axil_wstrb_next = m_axil_wstrb_reg;
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m_axil_wvalid_next = m_axil_wvalid_reg && !m_axil_wr.wready;
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m_axil_bready_next = 1'b0;
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m_axil_arvalid_next = m_axil_arvalid_reg && !m_axil_rd.arready;
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m_axil_rready_next = 1'b0;
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case (state_reg)
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STATE_IDLE: begin
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// idle, wait for I2C interface
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if (data_out.tvalid) begin
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// store address and write
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count_next = 8'(ADDR_WORD_W-1);
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state_next = STATE_ADDRESS;
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end else if (data_in.tready && !data_in_valid_reg) begin
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// read
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m_axil_arvalid_next = 1'b1;
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m_axil_rready_next = 1'b1;
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state_next = STATE_READ_1;
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end
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end
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STATE_ADDRESS: begin
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// store address
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data_out_ready_next = 1'b1;
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if (data_out_ready_reg && data_out.tvalid) begin
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// store pointers
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addr_next[8*count_reg +: 8] = data_out.tdata;
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count_next = count_reg - 1;
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if (count_reg == 0) begin
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// end of header
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// set initial word offset
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if (ADDR_W == VALID_ADDR_W && WORD_PART_ADDR_W == 0) begin
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count_next = '0;
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end else begin
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count_next = 8'(addr_next[ADDR_W_ADJ-VALID_ADDR_W-1:0]);
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end
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m_axil_wstrb_next = 'd0;
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data_next = 'd0;
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if (data_out.tlast) begin
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// end of transaction
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state_next = STATE_IDLE;
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end else begin
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// start writing
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state_next = STATE_WRITE_1;
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end
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end else begin
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if (data_out.tlast) begin
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// end of transaction
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_ADDRESS;
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end
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end
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end else begin
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state_next = STATE_ADDRESS;
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end
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end
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STATE_READ_1: begin
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// wait for data
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m_axil_rready_next = 1'b1;
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if (m_axil_rd.rready && m_axil_rd.rvalid) begin
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// read cycle complete, store result
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m_axil_rready_next = 1'b0;
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data_next = m_axil_rd.rdata;
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addr_next = addr_reg + (1 << (ADDR_W-VALID_ADDR_W+WORD_PART_ADDR_W));
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state_next = STATE_READ_2;
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end else begin
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state_next = STATE_READ_1;
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end
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end
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STATE_READ_2: begin
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// send data
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if (data_out.tvalid || !bus_addressed) begin
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// no longer addressed or now addressed for write, return to idle
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state_next = STATE_IDLE;
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end else if (data_in.tready && !data_in_valid_reg) begin
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// transfer word and update pointers
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data_in_next = data_reg[8*count_reg +: 8];
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data_in_valid_next = 1'b1;
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count_next = count_reg + 1;
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if (count_reg == 8'((STRB_W*BYTE_SIZE/8)-1)) begin
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// end of stored data word; return to idle
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count_next = 0;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_READ_2;
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end
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end else begin
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state_next = STATE_READ_2;
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end
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end
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STATE_WRITE_1: begin
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// write data
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data_out_ready_next = 1'b1;
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if (data_out_ready_reg && data_out.tvalid) begin
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// store word
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data_next[8*count_reg +: 8] = data_out.tdata;
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count_next = count_reg + 1;
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m_axil_wstrb_next[count_reg >> ((BYTE_SIZE/8)-1)] = 1'b1;
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if (count_reg == 8'((STRB_W*BYTE_SIZE/8)-1) || data_out.tlast) begin
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// have full word or at end of block, start write operation
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count_next = 0;
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m_axil_awvalid_next = 1'b1;
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m_axil_wvalid_next = 1'b1;
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m_axil_bready_next = 1'b1;
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state_next = STATE_WRITE_2;
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end else begin
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state_next = STATE_WRITE_1;
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end
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end else begin
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state_next = STATE_WRITE_1;
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end
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end
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STATE_WRITE_2: begin
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// wait for write completion
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m_axil_bready_next = 1'b1;
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if (m_axil_wr.bready && m_axil_wr.bvalid) begin
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// end of write operation
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data_next = 'd0;
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addr_next = addr_reg + (1 << (ADDR_W-VALID_ADDR_W+WORD_PART_ADDR_W));
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m_axil_bready_next = 1'b0;
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m_axil_wstrb_next = 'd0;
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if (last_cycle_reg) begin
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// end of transaction
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_WRITE_1;
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end
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end else begin
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state_next = STATE_WRITE_2;
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end
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end
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default: begin
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// invalid state - return to idle
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state_next = STATE_IDLE;
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end
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endcase
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end
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always_ff @(posedge clk) begin
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state_reg <= state_next;
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count_reg <= count_next;
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if (data_out_ready_reg & data_out.tvalid) begin
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last_cycle_reg <= data_out.tlast;
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end
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addr_reg <= addr_next;
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data_reg <= data_next;
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m_axil_awvalid_reg <= m_axil_awvalid_next;
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m_axil_wstrb_reg <= m_axil_wstrb_next;
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m_axil_wvalid_reg <= m_axil_wvalid_next;
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m_axil_bready_reg <= m_axil_bready_next;
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m_axil_arvalid_reg <= m_axil_arvalid_next;
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m_axil_rready_reg <= m_axil_rready_next;
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busy_reg <= state_next != STATE_IDLE;
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data_in_reg <= data_in_next;
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data_in_valid_reg <= data_in_valid_next;
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||||
data_out_ready_reg <= data_out_ready_next;
|
||||
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
data_in_valid_reg <= 1'b0;
|
||||
data_out_ready_reg <= 1'b0;
|
||||
m_axil_awvalid_reg <= 1'b0;
|
||||
m_axil_wvalid_reg <= 1'b0;
|
||||
m_axil_bready_reg <= 1'b0;
|
||||
m_axil_arvalid_reg <= 1'b0;
|
||||
m_axil_rready_reg <= 1'b0;
|
||||
busy_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
taxi_i2c_slave #(
|
||||
.FILTER_LEN(FILTER_LEN)
|
||||
)
|
||||
i2c_slave_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
// Host interface
|
||||
.release_bus(1'b0),
|
||||
.s_axis_data(data_in),
|
||||
.m_axis_data(data_out),
|
||||
|
||||
// I2C Interface
|
||||
.scl_i(i2c_scl_i),
|
||||
.scl_o(i2c_scl_o),
|
||||
.sda_i(i2c_sda_i),
|
||||
.sda_o(i2c_sda_o),
|
||||
|
||||
// Status
|
||||
.busy(),
|
||||
.bus_address(bus_address),
|
||||
.bus_addressed(bus_addressed),
|
||||
.bus_active(bus_active),
|
||||
|
||||
// Configuration
|
||||
.enable(enable),
|
||||
.device_address(device_address),
|
||||
.device_address_mask(7'h7f)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user