diff --git a/src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.py b/src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.py
index 251fbf9..0040c76 100644
--- a/src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.py
+++ b/src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.py
@@ -204,6 +204,8 @@ def test_taxi_i2c_master(request):
         os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
     ]
 
+    verilog_sources = process_f_files(verilog_sources)
+
     parameters = {}
 
     extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
diff --git a/src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py b/src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py
index e46b35b..e52aa7f 100644
--- a/src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py
+++ b/src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py
@@ -175,6 +175,8 @@ def test_taxi_i2c_single_reg(request):
         os.path.join(rtl_dir, f"{dut}.sv"),
     ]
 
+    verilog_sources = process_f_files(verilog_sources)
+
     parameters = {}
 
     parameters['FILTER_LEN'] = 4
diff --git a/src/lss/tb/taxi_i2c_slave/test_taxi_i2c_slave.py b/src/lss/tb/taxi_i2c_slave/test_taxi_i2c_slave.py
index 783b89b..a3b522a 100644
--- a/src/lss/tb/taxi_i2c_slave/test_taxi_i2c_slave.py
+++ b/src/lss/tb/taxi_i2c_slave/test_taxi_i2c_slave.py
@@ -133,6 +133,8 @@ def test_taxi_i2c_slave(request):
         os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
     ]
 
+    verilog_sources = process_f_files(verilog_sources)
+
     parameters = {}
 
     parameters['FILTER_LEN'] = 4
diff --git a/src/lss/tb/taxi_i2c_slave_axil_master/test_taxi_i2c_slave_axil_master.py b/src/lss/tb/taxi_i2c_slave_axil_master/test_taxi_i2c_slave_axil_master.py
index d8f5de1..c15cbf8 100644
--- a/src/lss/tb/taxi_i2c_slave_axil_master/test_taxi_i2c_slave_axil_master.py
+++ b/src/lss/tb/taxi_i2c_slave_axil_master/test_taxi_i2c_slave_axil_master.py
@@ -172,6 +172,8 @@ def test_taxi_i2c_slave_axil_master(request):
         os.path.join(rtl_dir, f"{dut}.f"),
     ]
 
+    verilog_sources = process_f_files(verilog_sources)
+
     parameters = {}
 
     parameters['FILTER_LEN'] = 4