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lss: Add missing file list file handling

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-08-02 15:15:29 -07:00
parent 89f60f26ff
commit 467b044e88
4 changed files with 8 additions and 0 deletions
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2
src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.py
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@@ -204,6 +204,8 @@ def test_taxi_i2c_master(request):
os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

2
src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py
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@@ -175,6 +175,8 @@ def test_taxi_i2c_single_reg(request):
os.path.join(rtl_dir, f"{dut}.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['FILTER_LEN'] = 4

2
src/lss/tb/taxi_i2c_slave/test_taxi_i2c_slave.py
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@@ -133,6 +133,8 @@ def test_taxi_i2c_slave(request):
os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['FILTER_LEN'] = 4

2
src/lss/tb/taxi_i2c_slave_axil_master/test_taxi_i2c_slave_axil_master.py
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@@ -172,6 +172,8 @@ def test_taxi_i2c_slave_axil_master(request):
os.path.join(rtl_dir, f"{dut}.f"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['FILTER_LEN'] = 4