eth: Update ZCU111 example design to use 32-bit MACs at 10G

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/eth/example/ZCU111/fpga/fpga/Makefile

@@ -41,7 +41,7 @@ IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl
 IP_TCL_FILES += ../ip/usp_rfdc_1ghz_1gsps.tcl
 
 # Configuration
-#CONFIG_TCL_FILES = ./config.tcl
+CONFIG_TCL_FILES = ./config.tcl
 
 include ../common/vivado.mk
 
@@ -55,4 +55,3 @@ program: $(FPGA_TOP).bit
 	echo "program_hw_devices [current_hw_device]" >> program.tcl
 	echo "exit" >> program.tcl
 	vivado -nojournal -nolog -mode batch -source program.tcl
-

src/eth/example/ZCU111/fpga/fpga/config.tcl

@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "64"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/ZCU111/fpga/fpga_10g/Makefile

@@ -37,11 +37,11 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
 
 # IP
-IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl
 IP_TCL_FILES += ../ip/usp_rfdc_1ghz_1gsps.tcl
 
 # Configuration
-#CONFIG_TCL_FILES = ./config.tcl
+CONFIG_TCL_FILES = ./config.tcl
 
 include ../common/vivado.mk
 
@@ -55,4 +55,3 @@ program: $(FPGA_TOP).bit
 	echo "program_hw_devices [current_hw_device]" >> program.tcl
 	echo "exit" >> program.tcl
 	vivado -nojournal -nolog -mode batch -source program.tcl
-

src/eth/example/ZCU111/fpga/fpga_10g/config.tcl

@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "32"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/ZCU111/fpga/rtl/fpga.sv

@@ -22,7 +22,11 @@ module fpga #
     // vendor ("GENERIC", "XILINX", "ALTERA")
     parameter string VENDOR = "XILINX",
     // device family
-    parameter string FAMILY = "zynquplusRFSOC"
+    parameter string FAMILY = "zynquplusRFSOC",
+    // 10G/25G MAC configuration
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1,
+    parameter MAC_DATA_W = 64
 )
 (
     /*
@@ -756,7 +760,10 @@ fpga_core #(
     .VENDOR(VENDOR),
     .FAMILY(FAMILY),
     .ADC_CNT(ADC_CNT),
-    .DAC_CNT(DAC_CNT)
+    .DAC_CNT(DAC_CNT),
+    .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
+    .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
+    .MAC_DATA_W(MAC_DATA_W)
 )
 core_inst (
     /*

src/eth/example/ZCU111/fpga/rtl/fpga_core.sv

@@ -26,7 +26,11 @@ module fpga_core #
     // number of RFDC ADC channels
     parameter ADC_CNT = 8,
     // number of RFDC DAC channels
-    parameter DAC_CNT = ADC_CNT
+    parameter DAC_CNT = ADC_CNT,
+    // 10G/25G MAC configuration
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1,
+    parameter MAC_DATA_W = 64
 )
 (
     /*
@@ -291,9 +295,9 @@ wire sfp_mgt_refclk_0_bufg;
 
 wire sfp_rst;
 
-taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_tx[4]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_sfp_tx[4]();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[4]();
-taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_rx[4]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_sfp_rx[4]();
 
 if (SIM) begin
 
@@ -340,12 +344,14 @@ taxi_eth_mac_25g_us #(
     .CNT(4),
 
     // GT config
-    .CFG_LOW_LATENCY(1),
+    .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
 
     // GT type
     .GT_TYPE("GTY"),
 
-    // PHY parameters
+    // MAC/PHY config
+    .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
+    .DATA_W(MAC_DATA_W),
     .PADDING_EN(1'b1),
     .DIC_EN(1'b1),
     .MIN_FRAME_LEN(64),

src/eth/example/ZCU111/fpga/tb/fpga_core/Makefile

@@ -44,6 +44,9 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 export PARAM_SIM := "1'b1"
 export PARAM_VENDOR := "\"XILINX\""
 export PARAM_FAMILY := "\"zynquplusRFSOC\""
+export PARAM_CFG_LOW_LATENCY := "1'b1"
+export PARAM_COMBINED_MAC_PCS := "1'b1"
+export PARAM_MAC_DATA_W := "64"
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst

src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py

@@ -13,6 +13,7 @@ import logging
 import os
 import sys
 
+import pytest
 import cocotb_test.simulator
 
 import cocotb
@@ -51,12 +52,20 @@ class TB:
         for ch in dut.uut.sfp_mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
-            if ch.ch_inst.CFG_LOW_LATENCY.value:
+            if ch.ch_inst.DATA_W.value == 64:
-                clk = 2.482
+                if ch.ch_inst.CFG_LOW_LATENCY.value:
-                gbx_cfg = (66, [64, 65])
+                    clk = 2.482
+                    gbx_cfg = (66, [64, 65])
+                else:
+                    clk = 2.56
+                    gbx_cfg = None
             else:
-                clk = 2.56
+                if ch.ch_inst.CFG_LOW_LATENCY.value:
-                gbx_cfg = None
+                    clk = 3.102
+                    gbx_cfg = (66, [64, 65])
+                else:
+                    clk = 3.2
+                    gbx_cfg = None
 
             cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
             cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start())
@@ -127,6 +136,8 @@ async def mac_test(tb, source, sink):
     for k in range(1200):
         await RisingEdge(tb.dut.clk_125mhz)
 
+    sink.clear()
+
     tb.log.info("Multiple small packets")
 
     count = 64
@@ -204,7 +215,8 @@ def process_f_files(files):
     return list(lst.values())
 
 
-def test_fpga_core(request):
+@pytest.mark.parametrize("mac_data_w", [32, 64])
+def test_fpga_core(request, mac_data_w):
     dut = "fpga_core"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = module
@@ -230,6 +242,9 @@ def test_fpga_core(request):
     parameters['SIM'] = "1'b1"
     parameters['VENDOR'] = "\"XILINX\""
     parameters['FAMILY'] = "\"zynquplusRFSOC\""
+    parameters['CFG_LOW_LATENCY'] = "1'b1"
+    parameters['COMBINED_MAC_PCS'] = "1'b1"
+    parameters['MAC_DATA_W'] = mac_data_w
 
     extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
 

src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.sv

@@ -26,7 +26,10 @@ module test_fpga_core #
     parameter ADC_SAMPLE_CNT = 4,
     parameter DAC_CNT = ADC_CNT,
     parameter DAC_SAMPLE_W = ADC_SAMPLE_W,
-    parameter DAC_SAMPLE_CNT = ADC_SAMPLE_CNT
+    parameter DAC_SAMPLE_CNT = ADC_SAMPLE_CNT,
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1,
+    parameter MAC_DATA_W = 64
     /* verilator lint_on WIDTHTRUNC */
 )
 ();
@@ -106,7 +109,10 @@ fpga_core #(
     .VENDOR(VENDOR),
     .FAMILY(FAMILY),
     .ADC_CNT(ADC_CNT),
-    .DAC_CNT(DAC_CNT)
+    .DAC_CNT(DAC_CNT),
+    .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
+    .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
+    .MAC_DATA_W(MAC_DATA_W)
 )
 uut (
     /*