diff --git a/src/zircon/rtl/zircon_ip_len_cksum.sv b/src/zircon/rtl/zircon_ip_len_cksum.sv
new file mode 100644
index 0000000..1839f6f
--- /dev/null
+++ b/src/zircon/rtl/zircon_ip_len_cksum.sv
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * Zircon IP stack - Length and checksum computation
+ */
+module zircon_ip_len_cksum #
+(
+    parameter START_OFFSET = 14
+)
+(
+    input  wire logic  clk,
+    input  wire logic  rst,
+
+    /*
+     * Packet passthrough
+     */
+    taxi_axis_if.snk   s_axis_pkt,
+    taxi_axis_if.src   m_axis_pkt,
+
+    /*
+     * Packet metadata output
+     */
+    taxi_axis_if.src   m_axis_meta
+);
+
+localparam DATA_W = s_axis_pkt.DATA_W;
+localparam KEEP_W = s_axis_pkt.KEEP_W;
+localparam META_W = m_axis_meta.DATA_W;
+
+localparam ID_W = m_axis_meta.ID_W;
+localparam ID_EN = s_axis_pkt.ID_EN && m_axis_meta.ID_EN;
+localparam DEST_W = m_axis_meta.DEST_W;
+localparam DEST_EN = s_axis_pkt.DEST_EN && m_axis_meta.DEST_EN;
+localparam USER_W = m_axis_meta.USER_W;
+localparam USER_EN = s_axis_pkt.USER_EN && m_axis_meta.USER_EN;
+
+parameter LEVELS = $clog2(DATA_W/8);
+parameter OFFSET_W = START_OFFSET/KEEP_W > 1 ? $clog2(START_OFFSET/KEEP_W) : 1;
+
+// check configuration
+if (KEEP_W * 8 != DATA_W)
+    $fatal(0, "Error: Interface requires byte (8-bit) granularity (instance %m)");
+
+if (META_W != 32)
+    $fatal(0, "Error: Interface width must be 32 (instance %m)");
+
+if (m_axis_meta.KEEP_W * 8 != META_W)
+    $fatal(0, "Error: Interface requires byte (8-bit) granularity (instance %m)");
+
+logic [OFFSET_W-1:0] offset_reg = OFFSET_W'(START_OFFSET/KEEP_W);
+logic [KEEP_W-1:0] mask_reg = {KEEP_W{1'b1}} << START_OFFSET;
+
+logic [DATA_W-1:0] sum_reg[LEVELS-2:0];
+logic [(LEVELS-1)*4-1:0] len_reg[LEVELS-2:0];
+logic [ID_W-1:0] id_reg[LEVELS-2:0];
+logic [DEST_W-1:0] dest_reg[LEVELS-2:0];
+logic [USER_W-1:0] user_reg[LEVELS-2:0];
+logic [LEVELS-2:0] sum_valid_reg = '0;
+logic [LEVELS-2:0] sum_last_reg = '0;
+
+logic [16+LEVELS-1:0] sum_acc_temp;
+logic [15:0] sum_acc_reg = '0;
+logic [15:0] len_acc_reg = '0;
+
+logic [15:0] m_axis_meta_len_reg = '0;
+logic [15:0] m_axis_meta_csum_reg = '0;
+logic m_axis_meta_valid_reg = 1'b0;
+logic [ID_W-1:0] m_axis_meta_id_reg = '0;
+logic [DEST_W-1:0] m_axis_meta_dest_reg = '0;
+logic [USER_W-1:0] m_axis_meta_user_reg = '0;
+
+assign m_axis_pkt.tdata = s_axis_pkt.tdata;
+assign m_axis_pkt.tkeep = s_axis_pkt.tkeep;
+assign m_axis_pkt.tstrb = s_axis_pkt.tstrb;
+assign m_axis_pkt.tid = s_axis_pkt.tid;
+assign m_axis_pkt.tdest = s_axis_pkt.tdest;
+assign m_axis_pkt.tuser = s_axis_pkt.tuser;
+assign m_axis_pkt.tlast = s_axis_pkt.tlast;
+assign m_axis_pkt.tvalid = s_axis_pkt.tvalid;
+assign s_axis_pkt.tready = m_axis_pkt.tready;
+
+assign m_axis_meta.tdata = {m_axis_meta_csum_reg, m_axis_meta_len_reg};
+assign m_axis_meta.tkeep = '1;
+assign m_axis_meta.tstrb = m_axis_meta.tkeep;
+assign m_axis_meta.tid = ID_EN ? m_axis_meta_id_reg : '0;
+assign m_axis_meta.tdest = DEST_EN ? m_axis_meta_dest_reg : '0;
+assign m_axis_meta.tuser = USER_EN ? m_axis_meta_user_reg : '0;
+assign m_axis_meta.tlast = 1'b1;
+assign m_axis_meta.tvalid = m_axis_meta_valid_reg;
+
+// Mask input data
+wire [DATA_W-1:0] pkt_data_masked;
+
+for (genvar j = 0; j < KEEP_W; j = j + 1) begin
+    assign pkt_data_masked[j*8 +: 8] = (s_axis_pkt.tkeep[j] && mask_reg[j]) ? s_axis_pkt.tdata[j*8 +: 8] : 8'd0;
+end
+
+always_ff @(posedge clk) begin
+    sum_valid_reg[0] <= 1'b0;
+
+    if (s_axis_pkt.tvalid && s_axis_pkt.tready) begin
+        for (integer i = 0; i < DATA_W/8/4; i = i + 1) begin
+            sum_reg[0][i*17 +: 17] <= {pkt_data_masked[(4*i+0)*8 +: 8], pkt_data_masked[(4*i+1)*8 +: 8]} + {pkt_data_masked[(4*i+2)*8 +: 8], pkt_data_masked[(4*i+3)*8 +: 8]};
+            len_reg[0][i*3 +: 3] <= 3'(s_axis_pkt.tkeep[(4*i+0)]) + 3'(s_axis_pkt.tkeep[(4*i+1)]) + 3'(s_axis_pkt.tkeep[(4*i+2)]) + 3'(s_axis_pkt.tkeep[(4*i+3)]);
+        end
+        sum_valid_reg[0] <= 1'b1;
+        sum_last_reg[0] <= s_axis_pkt.tlast;
+        id_reg[0] <= ID_W'(s_axis_pkt.tid);
+        dest_reg[0] <= DEST_W'(s_axis_pkt.tdest);
+        user_reg[0] <= USER_W'(s_axis_pkt.tuser);
+
+        if (s_axis_pkt.tlast) begin
+            offset_reg <= OFFSET_W'(START_OFFSET/KEEP_W);
+            mask_reg <= {KEEP_W{1'b1}} << START_OFFSET;
+        end else if (START_OFFSET < KEEP_W || offset_reg == 0) begin
+            mask_reg <= {KEEP_W{1'b1}};
+        end else begin
+            offset_reg <= offset_reg - 1;
+            if (offset_reg == 1) begin
+                mask_reg <= {KEEP_W{1'b1}} << (START_OFFSET%KEEP_W);
+            end else begin
+                mask_reg <= {KEEP_W{1'b0}};
+            end
+        end
+    end
+
+    if (rst) begin
+        offset_reg <= OFFSET_W'(START_OFFSET/KEEP_W);
+        mask_reg <= {KEEP_W{1'b1}} << START_OFFSET;
+        sum_valid_reg[0] <= 1'b0;
+    end
+end
+
+for (genvar l = 1; l < LEVELS-1; l = l + 1) begin
+
+    always_ff @(posedge clk) begin
+        sum_valid_reg[l] <= 1'b0;
+
+        if (sum_valid_reg[l-1]) begin
+            for (integer i = 0; i < DATA_W/8/4/2**l; i = i + 1) begin
+                sum_reg[l][i*(17+l) +: (17+l)] <= sum_reg[l-1][(i*2+0)*(17+l-1) +: (17+l-1)] + sum_reg[l-1][(i*2+1)*(17+l-1) +: (17+l-1)];
+                len_reg[l][i*(3+l) +: (3+l)] <= len_reg[l-1][(i*2+0)*(3+l-1) +: (3+l-1)] + len_reg[l-1][(i*2+1)*(3+l-1) +: (3+l-1)];
+            end
+            sum_valid_reg[l] <= 1'b1;
+            sum_last_reg[l] <= sum_last_reg[l-1];
+            id_reg[l] <= id_reg[l-1];
+            dest_reg[l] <= dest_reg[l-1];
+            user_reg[l] <= user_reg[l-1];
+        end
+
+        if (rst) begin
+            sum_valid_reg[l] <= 1'b0;
+        end
+    end
+
+end
+
+always_ff @(posedge clk) begin
+    m_axis_meta_valid_reg <= 1'b0;
+
+    sum_acc_temp = sum_reg[LEVELS-2][16+LEVELS-1-1:0] + (16+LEVELS)'(sum_acc_reg);
+    sum_acc_temp = (16+LEVELS)'(sum_acc_temp[15:0] + 16'(sum_acc_temp >> 16));
+    sum_acc_temp = (16+LEVELS)'(sum_acc_temp[15:0] + 16'(sum_acc_temp[16]));
+
+    m_axis_meta_len_reg <= len_acc_reg + 16'(len_reg[LEVELS-2][3+LEVELS-1-1:0]);
+    m_axis_meta_csum_reg <= sum_acc_temp[15:0];
+    m_axis_meta_id_reg <= id_reg[LEVELS-2];
+    m_axis_meta_dest_reg <= dest_reg[LEVELS-2];
+    m_axis_meta_user_reg <= user_reg[LEVELS-2];
+
+    if (sum_valid_reg[LEVELS-2]) begin
+        if (sum_last_reg[LEVELS-2]) begin
+            m_axis_meta_valid_reg <= 1'b1;
+            sum_acc_reg <= '0;
+            len_acc_reg <= '0;
+        end else begin
+            sum_acc_reg <= sum_acc_temp[15:0];
+            len_acc_reg <= len_acc_reg + 16'(len_reg[LEVELS-2][3+LEVELS-1-1:0]);
+        end
+    end
+
+    if (rst) begin
+        m_axis_meta_valid_reg <= 1'b0;
+        sum_acc_reg <= '0;
+    end
+end
+
+endmodule
+
+`resetall
diff --git a/src/zircon/tb/zircon_ip_len_cksum/Makefile b/src/zircon/tb/zircon_ip_len_cksum/Makefile
new file mode 100644
index 0000000..84c1326
--- /dev/null
+++ b/src/zircon/tb/zircon_ip_len_cksum/Makefile
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = zircon_ip_len_cksum
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 32
+export PARAM_META_W := 32
+export PARAM_START_OFFSET := 14
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
diff --git a/src/zircon/tb/zircon_ip_len_cksum/test_zircon_ip_len_cksum.py b/src/zircon/tb/zircon_ip_len_cksum/test_zircon_ip_len_cksum.py
new file mode 100644
index 0000000..f09dbb4
--- /dev/null
+++ b/src/zircon/tb/zircon_ip_len_cksum/test_zircon_ip_len_cksum.py
@@ -0,0 +1,287 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import logging
+import os
+import struct
+
+import scapy.config
+import scapy.utils
+import scapy.pton_ntop
+from scapy.layers.l2 import Ether, Dot1Q, Dot1AD, ARP
+from scapy.layers.inet import IP, ICMP, UDP, TCP
+from scapy.layers.inet import IPOption_MTU_Probe
+from scapy.layers.inet6 import IPv6, ICMPv6ND_NS
+from scapy.layers.inet6 import IPv6ExtHdrFragment, IPv6ExtHdrHopByHop, RouterAlert
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+
+
+# don't hide ports
+scapy.config.conf.noenum.add(TCP.sport, TCP.dport)
+scapy.config.conf.noenum.add(UDP.sport, UDP.dport)
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 3.2, units="ns").start())
+
+        self.pkt_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_pkt), dut.clk, dut.rst)
+        self.pkt_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_pkt), dut.clk, dut.rst)
+        self.meta_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_meta), dut.clk, dut.rst)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    test_pkts = []
+
+    payload = bytearray(range(64))
+
+    ip_id = 0
+
+    l2hdrs = []
+
+    # Ethernet
+    eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
+    l2hdrs.append(eth)
+
+    # Ethernet with 802.1Q VLAN
+    eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
+    vlan = Dot1Q(vlan=123)
+    l2hdrs.append(eth / vlan)
+
+    # Ethernet with 802.1Q QinQ
+    eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
+    vlan = Dot1AD(vlan=456)
+    l2hdrs.append(eth / vlan)
+
+    # Ethernet with 802.1Q QinQ and VLAN
+    eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
+    vlan = Dot1AD(vlan=456) / Dot1Q(vlan=123)
+    l2hdrs.append(eth / vlan)
+
+    for l2hdr in l2hdrs:
+
+        # Raw ethernet
+        test_pkts.append(l2hdr / payload)
+
+        # ARP
+        arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2,
+            hwsrc='5A:51:52:53:54:55', psrc='192.168.1.100',
+            hwdst='DA:D1:D2:D3:D4:D5', pdst='192.168.1.101')
+        test_pkts.append(l2hdr / arp)
+
+        l3hdrs = []
+
+        # IPv4
+        ip = IP(src='10.1.0.1', dst='10.2.0.1', id=ip_id)
+        l3hdrs.append(ip)
+
+        # IPv4 (fragmented)
+        ip = IP(src='10.1.0.1', dst='10.2.0.1', flags=1, id=ip_id)
+        l3hdrs.append(ip)
+
+        # IPv4 with options
+        ip = IP(src='10.1.0.1', dst='10.2.0.1', id=ip_id, options=[IPOption_MTU_Probe()])
+        l3hdrs.append(ip)
+
+        # IPv6
+        ip6 = IPv6(src='fd12:3456:789a:1::1', dst='fd12:3456:789a:2::1', fl=ip_id)
+        l3hdrs.append(ip6)
+
+        # IPv6 with extensions (fragmented)
+        ip6 = IPv6(src='fd12:3456:789a:1::1', dst='fd12:3456:789a:2::1', fl=ip_id)
+        frag = IPv6ExtHdrFragment()
+        l3hdrs.append(ip6 / frag)
+
+        # IPv6 with extensions
+        ip6 = IPv6(src='fd12:3456:789a:1::1', dst='fd12:3456:789a:2::1', fl=ip_id)
+        hbh = IPv6ExtHdrHopByHop(options=[RouterAlert()])
+        l3hdrs.append(ip6 / hbh)
+
+        # IPv6 with extensions 2
+        ip6 = IPv6(src='fd12:3456:789a:1::1', dst='fd12:3456:789a:2::1', fl=ip_id)
+        hbh = IPv6ExtHdrHopByHop(options=[RouterAlert(), RouterAlert(), RouterAlert(), RouterAlert()])
+        l3hdrs.append(ip6 / hbh)
+
+        for l3hdr in l3hdrs:
+
+            l3hdr = l3hdr.copy()
+            if IP in l3hdr:
+                l3hdr.id = ip_id
+            if IPv6 in l3hdr:
+                l3hdr.fl = ip_id
+
+            # IP (empty)
+            if IP in l3hdr:
+                hdr = l3hdr.copy()
+                hdr.proto = 59
+                test_pkts.append(l2hdr / hdr)
+            else:
+                test_pkts.append(l2hdr / l3hdr)
+
+            # IP (unsupported protocol)
+            if IP in l3hdr:
+                hdr = l3hdr.copy()
+                hdr.proto = 59
+                test_pkts.append(l2hdr / hdr / payload)
+            else:
+                test_pkts.append(l2hdr / l3hdr / payload)
+
+            if IP in l3hdr:
+                # ICMP
+                icmp = ICMP(type=8)
+                test_pkts.append(l2hdr / l3hdr / icmp / payload)
+
+            if IPv6 in l3hdr:
+                # ICMPv6 / NDP
+                ns = ICMPv6ND_NS(tgt='::')
+                test_pkts.append(l2hdr / l3hdr / ns)
+
+            # UDP (empty)
+            udp = UDP(sport=ip_id, dport=0x1000+ip_id)
+            test_pkts.append(l2hdr / l3hdr / udp)
+
+            # UDP
+            udp = UDP(sport=ip_id, dport=0x1000+ip_id)
+            test_pkts.append(l2hdr / l3hdr / udp / payload)
+
+            # TCP (empty)
+            tcp = TCP(sport=ip_id, dport=0x1000+ip_id, seq=54321, ack=12345, window=8192)
+            test_pkts.append(l2hdr / l3hdr / tcp)
+
+            # TCP with options (empty)
+            tcp = TCP(sport=ip_id, dport=0x1000+ip_id, seq=54321, ack=12345, window=8192, options=[('Timestamp',(0,0))])
+            test_pkts.append(l2hdr / l3hdr / tcp)
+
+            # TCP
+            tcp = TCP(sport=ip_id, dport=0x1000+ip_id, seq=54321, ack=12345, window=8192)
+            test_pkts.append(l2hdr / l3hdr / tcp / payload)
+
+            # TCP with options
+            tcp = TCP(sport=ip_id, dport=0x1000+ip_id, seq=54321, ack=12345, window=8192, options=[('Timestamp',(0,0))])
+            test_pkts.append(l2hdr / l3hdr / tcp / payload)
+
+            ip_id += 1
+
+    for pkt in test_pkts:
+        tb.log.info("Packet: %r", pkt)
+
+        pkt_b = pkt.build()
+
+        rx_csum = ~scapy.utils.checksum(bytes(pkt_b[14:])) & 0xffff
+
+        await tb.pkt_source.send(AxiStreamFrame(pkt_b))
+
+        meta = await tb.meta_sink.recv()
+
+        tb.log.info("Metadata: %r", meta)
+
+        pkt_len, pkt_sum = struct.unpack_from('<HH', meta.tdata, 0)
+
+        tb.log.info("Payload length: %d", pkt_len)
+        tb.log.info("Packet checksum: 0x%04x", pkt_sum)
+
+        assert pkt_len == len(pkt_b)
+        assert pkt_sum == rx_csum
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_zircon_ip_len_cksum(request, data_w=32):
+    dut = "zircon_ip_len_cksum"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = data_w
+    parameters['META_W'] = 32
+    parameters['START_OFFSET'] = 14
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )
diff --git a/src/zircon/tb/zircon_ip_len_cksum/test_zircon_ip_len_cksum.sv b/src/zircon/tb/zircon_ip_len_cksum/test_zircon_ip_len_cksum.sv
new file mode 100644
index 0000000..c45b7e6
--- /dev/null
+++ b/src/zircon/tb/zircon_ip_len_cksum/test_zircon_ip_len_cksum.sv
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * testbench
+ */
+module test_zircon_ip_len_cksum #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 32,
+    parameter META_W = 32,
+    parameter START_OFFSET = 14
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(1)) s_axis_pkt();
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(1)) m_axis_pkt();
+taxi_axis_if #(.DATA_W(META_W), .USER_EN(1), .USER_W(1)) m_axis_meta();
+
+zircon_ip_len_cksum #(
+    .START_OFFSET(START_OFFSET)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * Packet header input
+     */
+    .s_axis_pkt(s_axis_pkt),
+    .m_axis_pkt(m_axis_pkt),
+
+    /*
+     * Packet metadata output
+     */
+    .m_axis_meta(m_axis_meta)
+);
+
+endmodule
+
+`resetall