From 499a70982f817b4bc36dbfc5951c1e58084647e3 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Sun, 1 Mar 2026 20:43:13 -0800
Subject: [PATCH] prim: Fix single-clock TDP RAM inference

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 src/prim/rtl/taxi_ram_2rw_1c.sv | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/prim/rtl/taxi_ram_2rw_1c.sv b/src/prim/rtl/taxi_ram_2rw_1c.sv
index f79b5ff..711db6e 100644
--- a/src/prim/rtl/taxi_ram_2rw_1c.sv
+++ b/src/prim/rtl/taxi_ram_2rw_1c.sv
@@ -74,7 +74,9 @@ always_ff @(posedge clk) begin
             a_rd_data_reg <= mem[a_addr];
         end
     end
+end
 
+always_ff @(posedge clk) begin
     if (b_en) begin
         if (b_wr_en) begin
             if (STRB_EN) begin