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prim: Fix single-clock TDP RAM inference

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2026-03-01 20:43:13 -08:00
parent 32b073ade9
commit 499a70982f
1 changed files with 2 additions and 0 deletions
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src/prim/rtl/taxi_ram_2rw_1c.sv
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@@ -74,7 +74,9 @@ always_ff @(posedge clk) begin
a_rd_data_reg <= mem[a_addr]; a_rd_data_reg <= mem[a_addr];
end end
end end
end
always_ff @(posedge clk) begin
if (b_en) begin if (b_en) begin
if (b_wr_en) begin if (b_wr_en) begin
if (STRB_EN) begin if (STRB_EN) begin