diff --git a/README.md b/README.md index 4e76242..b8e3961 100644 --- a/README.md +++ b/README.md @@ -227,6 +227,7 @@ Example designs are provided for several different FPGA boards, showcasing many * HiTech Global HTG-9200 (Xilinx Virtex UltraScale+ XCVU9P/XCVU13P) * HiTech Global HTG-ZRF8-R2 (Xilinx Zynq UltraScale+ RFSoC XCZU28DR/XCZU48DR) * HiTech Global HTG-ZRF8-EM (Xilinx Zynq UltraScale+ RFSoC XCZU28DR/XCZU48DR) +* Opal Kelley XEM8320 (Xilinx Artix UltraScale+ XCAU25P) * Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P) * Xilinx Alveo U45N/SN1000 (Xilinx Virtex UltraScale+ XCU26) * Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50) diff --git a/src/eth/example/XEM8320/fpga/README.md b/src/eth/example/XEM8320/fpga/README.md new file mode 100644 index 0000000..54eca7d --- /dev/null +++ b/src/eth/example/XEM8320/fpga/README.md @@ -0,0 +1,33 @@ +# Taxi Example Design for XEM8320 + +## Introduction + +This example design targets the Opal Kelley XEM8320 FPGA board. + +The design places looped-back MACs on SFP+ cages. + +* SFP+ cages + * Looped-back 1000BASE-X via Xilinx PCS/PMA core and GTH transceiver + * Looped-back 10GBASE-R MAC via GTH transceiver + +## Board details + +* FPGA: xcau25p-ffvb676-2-e +* 10GBASE-R PHY: Soft PCS with GTH transceiver + +## Licensing + +* Toolchain + * Vivado Enterprise (requires license) +* IP + * No licensed vendor IP or 3rd party IP + +## How to build + +Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. + +## How to test + +Run `make program` to program the board with Vivado. + +To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. diff --git a/src/eth/example/XEM8320/fpga/common/vivado.mk b/src/eth/example/XEM8320/fpga/common/vivado.mk new file mode 100644 index 0000000..07c56e2 --- /dev/null +++ b/src/eth/example/XEM8320/fpga/common/vivado.mk @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: MIT +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016-2025 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - list of source files +# INC_FILES - list of include files +# XDC_FILES - list of timing constraint files +# XCI_FILES - list of IP XCI files +# IP_TCL_FILES - list of IP TCL files (sourced during project creation) +# CONFIG_TCL_FILES - list of config TCL files (sourced before each build) +# +# Note: both SYN_FILES and INC_FILES support file list files. File list +# files are files with a .f extension that contain a list of additional +# files to include, one path relative to the .f file location per line. +# The .f files are processed recursively, and then the complete file list +# is de-duplicated, with later files in the list taking precedence. +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include $(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) +XDC_FILES ?= $(PROJECT).xdc + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES))) +INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES))) + +################################################################### +# Main Targets +# +# all: build everything (fpga) +# fpga: build FPGA config +# vivado: open project in Vivado +# tmpclean: remove intermediate files +# clean: remove output files and project files +# distclean: remove archived output files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file + +# create fresh project if Makefile or IP files have changed +create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@ + for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done + +# source config TCL scripts if any source file has changed +update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# output files (including potentially bit, bin, ltx, and xsa) +$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \ + if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi diff --git a/src/eth/example/XEM8320/fpga/fpga.xdc b/src/eth/example/XEM8320/fpga/fpga.xdc new file mode 100644 index 0000000..36d7471 --- /dev/null +++ b/src/eth/example/XEM8320/fpga/fpga.xdc @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# XDC constraints for the Opal Kelley XEM8320 board +# part: xcau25p-ffvb676-2-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 85 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +# System clocks +# 100 MHz system clock +set_property -dict {LOC T24 IOSTANDARD LVDS} [get_ports clk_100mhz_p] ;# from U42 +set_property -dict {LOC U24 IOSTANDARD LVDS} [get_ports clk_100mhz_n] ;# from U42 +create_clock -period 10.000 -name clk_100mhz [get_ports clk_100mhz_p] + +# 100 MHz DDR4 clock +#set_property -dict {LOC AD20 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_p] ;# from U43 +#set_property -dict {LOC AE20 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_n] ;# from U43 +#create_clock -period 10.000 -name clk_ddr4 [get_ports clk_ddr4_p] + +# LEDs +set_property -dict {LOC G19 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}] ;# to D1 +set_property -dict {LOC B16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}] ;# to D2 +set_property -dict {LOC F22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[2]}] ;# to D3 +set_property -dict {LOC E22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[3]}] ;# to D4 +set_property -dict {LOC M24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[4]}] ;# to D5 +set_property -dict {LOC G22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[5]}] ;# to D6 + +set_false_path -to [get_ports {led[*]}] +set_output_delay 0 [get_ports {led[*]}] + +# SFP+ interfaces +set_property -dict {LOC M2 } [get_ports {sfp_rx_p[0]}] ;# MGTYRXP0_226 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +set_property -dict {LOC M1 } [get_ports {sfp_rx_n[0]}] ;# MGTYRXN0_226 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +set_property -dict {LOC N5 } [get_ports {sfp_tx_p[0]}] ;# MGTYTXP0_226 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +set_property -dict {LOC N4 } [get_ports {sfp_tx_n[0]}] ;# MGTYTXN0_226 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2 +set_property -dict {LOC K2 } [get_ports {sfp_rx_p[1]}] ;# MGTYRXP1_226 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +set_property -dict {LOC K1 } [get_ports {sfp_rx_n[1]}] ;# MGTYRXN1_226 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +set_property -dict {LOC L5 } [get_ports {sfp_tx_p[1]}] ;# MGTYTXP1_226 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +set_property -dict {LOC L4 } [get_ports {sfp_tx_n[1]}] ;# MGTYTXN1_226 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2 +#set_property -dict {LOC P7 } [get_ports sfp_mgt_refclk_0_p] ;# MGTREFCLK0P_226 from U39 +#set_property -dict {LOC P6 } [get_ports sfp_mgt_refclk_0_n] ;# MGTREFCLK0N_226 from U39 +#set_property -dict {LOC M7 } [get_ports sfp_mgt_refclk_1_p] ;# MGTREFCLK1P_226 from J19 +#set_property -dict {LOC M6 } [get_ports sfp_mgt_refclk_1_n] ;# MGTREFCLK1N_226 from J20 +set_property -dict {LOC Y7 } [get_ports sfp_mgt_refclk_2_p] ;# MGTREFCLK0P_224 from U52 +set_property -dict {LOC Y6 } [get_ports sfp_mgt_refclk_2_n] ;# MGTREFCLK0N_224 from U52 +set_property -dict {LOC C13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[0]}] +set_property -dict {LOC F13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[1]}] +set_property -dict {LOC C14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_tx_fault[0]}] +set_property -dict {LOC F14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_tx_fault[1]}] +set_property -dict {LOC D14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_npres[0]}] +set_property -dict {LOC A14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_npres[1]}] +set_property -dict {LOC E13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_los[0]}] +set_property -dict {LOC A13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_los[1]}] +set_property -dict {LOC D13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0][0]}] +set_property -dict {LOC E12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0][1]}] +set_property -dict {LOC B14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1][0]}] +set_property -dict {LOC A12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1][1]}] +#set_property -dict {LOC B12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[0]}] +#set_property -dict {LOC C12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_scl[0]}] +#set_property -dict {LOC F12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_sda[1]}] +#set_property -dict {LOC G12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {sfp_i2c_scl[1]}] + +# 156.25 MHz MGT reference clock +#create_clock -period 8.000 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p] + +# MGT reference clock from SMA +#create_clock -period 6.400 -name sfp_mgt_refclk_1 [get_ports sfp_mgt_refclk_1_p] + +# 156.25 MHz MGT reference clock +create_clock -period 6.400 -name sfp_mgt_refclk_2 [get_ports sfp_mgt_refclk_2_p] + +set_false_path -to [get_ports {sfp_tx_disable[*] sfp_rs[*]}] +set_output_delay 0 [get_ports {sfp_tx_disable[*] sfp_rs[*]}] +set_false_path -from [get_ports {sfp_tx_fault[*] sfp_npres[*] sfp_los[*]}] +set_input_delay 0 [get_ports {sfp_tx_fault[*] sfp_npres[*] sfp_los[*]}] + +#set_false_path -to [get_ports {sfp_i2c_sda[*] sfp_i2c_scl[*]}] +#set_output_delay 0 [get_ports {sfp_i2c_sda[*] sfp_i2c_scl[*]}] +#set_false_path -from [get_ports {sfp_i2c_sda[*] sfp_i2c_scl[*]}] +#set_input_delay 0 [get_ports {sfp_i2c_sda[*] sfp_i2c_scl[*]}] + +# DDR4 +# MT40A512M16LY-075:E U16 +#set_property -dict {LOC AD18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}] +#set_property -dict {LOC AE17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}] +#set_property -dict {LOC AB17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}] +#set_property -dict {LOC AE18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}] +#set_property -dict {LOC AD19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}] +#set_property -dict {LOC AF17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}] +#set_property -dict {LOC Y17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}] +#set_property -dict {LOC AE16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}] +#set_property -dict {LOC AA17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}] +#set_property -dict {LOC AC17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}] +#set_property -dict {LOC AC19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}] +#set_property -dict {LOC AC16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}] +#set_property -dict {LOC AF20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}] +#set_property -dict {LOC AD16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}] +#set_property -dict {LOC AA19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}] +#set_property -dict {LOC AF19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}] +#set_property -dict {LOC AA18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}] +#set_property -dict {LOC AC18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}] +#set_property -dict {LOC AF18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}] +#set_property -dict {LOC AB19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}] +#set_property -dict {LOC Y20 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}] +#set_property -dict {LOC Y21 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}] +#set_property -dict {LOC AA20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}] +#set_property -dict {LOC AF22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}] +#set_property -dict {LOC Y18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}] +#set_property -dict {LOC AB20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}] +#set_property -dict {LOC AE26 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}] + +#set_property -dict {LOC AF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}] +#set_property -dict {LOC AB25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}] +#set_property -dict {LOC AB26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}] +#set_property -dict {LOC AC24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}] +#set_property -dict {LOC AF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}] +#set_property -dict {LOC AB24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}] +#set_property -dict {LOC AD24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}] +#set_property -dict {LOC AD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}] +#set_property -dict {LOC AB21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}] +#set_property -dict {LOC AE21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}] +#set_property -dict {LOC AE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}] +#set_property -dict {LOC AD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}] +#set_property -dict {LOC AC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}] +#set_property -dict {LOC AD21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}] +#set_property -dict {LOC AC22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}] +#set_property -dict {LOC AC21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}] +#set_property -dict {LOC AC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}] ;# U16.G3 DQSL_T +#set_property -dict {LOC AD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}] ;# U16.F3 DQSL_C +#set_property -dict {LOC AA22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}] ;# U16.B7 DQSU_T +#set_property -dict {LOC AB22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}] ;# U16.A7 DQSU_C +#set_property -dict {LOC AE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}] ;# U16.E7 DML_B/DBIL_B +#set_property -dict {LOC AE22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}] ;# U16.E2 DMU_B/DBIU_B diff --git a/src/eth/example/XEM8320/fpga/fpga/Makefile b/src/eth/example/XEM8320/fpga/fpga/Makefile new file mode 100644 index 0000000..393e2a2 --- /dev/null +++ b/src/eth/example/XEM8320/fpga/fpga/Makefile @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcau25p-ffvb676-2-e +FPGA_TOP = fpga +FPGA_ARCH = artixuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl + +# Configuration +#CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(PROJECT).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl diff --git a/src/eth/example/XEM8320/fpga/lib/taxi b/src/eth/example/XEM8320/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/XEM8320/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/src/eth/example/XEM8320/fpga/rtl/fpga.sv b/src/eth/example/XEM8320/fpga/rtl/fpga.sv new file mode 100644 index 0000000..d0c1a74 --- /dev/null +++ b/src/eth/example/XEM8320/fpga/rtl/fpga.sv @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2014-2026 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga # +( + // simulation (set to avoid vendor primitives) + parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") + parameter string VENDOR = "XILINX", + // device family + parameter string FAMILY = "artixuplus" +) +( + /* + * Clock: 125MHz LVDS + */ + input wire logic clk_100mhz_p, + input wire logic clk_100mhz_n, + + /* + * GPIO + */ + output wire logic [5:0] led, + + /* + * Ethernet: SFP+ + */ + input wire logic sfp_rx_p[2], + input wire logic sfp_rx_n[2], + output wire logic sfp_tx_p[2], + output wire logic sfp_tx_n[2], + // input wire logic sfp_mgt_refclk_0_p, + // input wire logic sfp_mgt_refclk_0_n, + // input wire logic sfp_mgt_refclk_1_p, + // input wire logic sfp_mgt_refclk_1_n, + input wire logic sfp_mgt_refclk_2_p, + input wire logic sfp_mgt_refclk_2_n, + + output wire logic sfp_tx_disable[2], + input wire logic sfp_tx_fault[2], + input wire logic sfp_npres[2], + input wire logic sfp_los[2], + output wire logic [1:0] sfp_rs[2] + + // inout wire logic sfp_i2c_sda[2], + // inout wire logic sfp_i2c_scl[2] +); + +// Clock and reset + +wire clk_100mhz_ibufg; + +// Internal 125 MHz clock +wire clk_125mhz_mmcm_out; +wire clk_125mhz_int; +wire rst_125mhz_int; + +// Internal 62.5 MHz clock +wire clk_62mhz_mmcm_out; +wire clk_62mhz_int; + +wire mmcm_rst = 1'b0; +wire mmcm_locked; +wire mmcm_clkfb; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_100mhz_ibufg_inst ( + .O (clk_100mhz_ibufg), + .I (clk_100mhz_p), + .IB (clk_100mhz_n) +); + +// MMCM instance +MMCME3_BASE #( + // 125 MHz input + .CLKIN1_PERIOD(8.0), + .REF_JITTER1(0.010), + // 100 MHz input / 2 = 50 MHz PFD (range 10 MHz to 500 MHz) + .DIVCLK_DIVIDE(2), + // 50 MHz PFD * 25 = 1250 MHz VCO (range 600 MHz to 1440 MHz) + .CLKFBOUT_MULT_F(25), + .CLKFBOUT_PHASE(0), + // 1250 MHz / 10 = 125 MHz, 0 degrees + .CLKOUT0_DIVIDE_F(10), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + // 1250 MHz / 20 = 62.5 MHz, 0 degrees + .CLKOUT1_DIVIDE(20), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + // Not used + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + // Not used + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + // Not used + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT4_CASCADE("FALSE"), + // Not used + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + // Not used + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + + // optimized bandwidth + .BANDWIDTH("OPTIMIZED"), + // don't wait for lock during startup + .STARTUP_WAIT("FALSE") +) +clk_mmcm_inst ( + // 125 MHz input + .CLKIN1(clk_100mhz_ibufg), + // direct clkfb feeback + .CLKFBIN(mmcm_clkfb), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + // 125 MHz, 0 degrees + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + // 62.5 MHz, 0 degrees + .CLKOUT1(clk_62mhz_mmcm_out), + .CLKOUT1B(), + // Not used + .CLKOUT2(), + .CLKOUT2B(), + // Not used + .CLKOUT3(), + .CLKOUT3B(), + // Not used + .CLKOUT4(), + // Not used + .CLKOUT5(), + // Not used + .CLKOUT6(), + // reset input + .RST(mmcm_rst), + // don't power down + .PWRDWN(1'b0), + // locked output + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +BUFG +clk_62mhz_bufg_inst ( + .I(clk_62mhz_mmcm_out), + .O(clk_62mhz_int) +); + +taxi_sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +fpga_core #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY) +) +core_inst ( + /* + * Clock: 125MHz + * Synchronous reset + */ + .clk_125mhz(clk_125mhz_int), + .rst_125mhz(rst_125mhz_int), + + /* + * GPIO + */ + .led(led), + + /* + * Ethernet: SFP+ + */ + .sfp_rx_p(sfp_rx_p), + .sfp_rx_n(sfp_rx_n), + .sfp_tx_p(sfp_tx_p), + .sfp_tx_n(sfp_tx_n), + // .sfp_mgt_refclk_0_p(sfp_mgt_refclk_0_p), + // .sfp_mgt_refclk_0_n(sfp_mgt_refclk_0_n), + // .sfp_mgt_refclk_1_p(sfp_mgt_refclk_1_p), + // .sfp_mgt_refclk_1_n(sfp_mgt_refclk_1_n), + .sfp_mgt_refclk_2_p(sfp_mgt_refclk_2_p), + .sfp_mgt_refclk_2_n(sfp_mgt_refclk_2_n), + + .sfp_tx_disable(sfp_tx_disable), + .sfp_tx_fault(sfp_tx_fault), + .sfp_npres(sfp_npres), + .sfp_los(sfp_los), + .sfp_rs(sfp_rs) +); + +endmodule + +`resetall diff --git a/src/eth/example/XEM8320/fpga/rtl/fpga_core.sv b/src/eth/example/XEM8320/fpga/rtl/fpga_core.sv new file mode 100644 index 0000000..27c7607 --- /dev/null +++ b/src/eth/example/XEM8320/fpga/rtl/fpga_core.sv @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2014-2026 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic + */ +module fpga_core # +( + // simulation (set to avoid vendor primitives) + parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") + parameter string VENDOR = "XILINX", + // device family + parameter string FAMILY = "artixuplus" +) +( + /* + * Clock: 125MHz + * Synchronous reset + */ + input wire logic clk_125mhz, + input wire logic rst_125mhz, + + /* + * GPIO + */ + output wire logic [5:0] led, + + /* + * Ethernet: SFP+ + */ + input wire logic sfp_rx_p[2], + input wire logic sfp_rx_n[2], + output wire logic sfp_tx_p[2], + output wire logic sfp_tx_n[2], + // input wire logic sfp_mgt_refclk_0_p, + // input wire logic sfp_mgt_refclk_0_n, + // input wire logic sfp_mgt_refclk_1_p, + // input wire logic sfp_mgt_refclk_1_n, + input wire logic sfp_mgt_refclk_2_p, + input wire logic sfp_mgt_refclk_2_n, + + output wire logic sfp_tx_disable[2], + input wire logic sfp_tx_fault[2], + input wire logic sfp_npres[2], + input wire logic sfp_los[2], + output wire logic [1:0] sfp_rs[2] +); + +// SFP+ +assign sfp_tx_disable = '{2{1'b0}}; +assign sfp_rs = '{2{2'b11}}; + +wire sfp_tx_clk[2]; +wire sfp_tx_rst[2]; +wire sfp_rx_clk[2]; +wire sfp_rx_rst[2]; + +wire sfp_rx_status[2]; + +assign led[0] = sfp_rx_status[0]; +assign led[1] = sfp_rx_status[1]; +assign led[2] = 1'b0; +assign led[3] = 1'b0; +assign led[4] = 1'b0; +assign led[5] = 1'b0; + +wire sfp_gtpowergood; + +wire sfp_mgt_refclk_2; +wire sfp_mgt_refclk_2_int; +wire sfp_mgt_refclk_2_bufg; + +wire sfp_rst; + +taxi_axis_if #(.DATA_W(32), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_tx[2](); +taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[2](); +taxi_axis_if #(.DATA_W(32), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_rx[2](); +taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_sfp_stat(); + +if (SIM) begin + + assign sfp_mgt_refclk_2 = sfp_mgt_refclk_2_p; + assign sfp_mgt_refclk_2_int = sfp_mgt_refclk_2_p; + assign sfp_mgt_refclk_2_bufg = sfp_mgt_refclk_2_int; + +end else begin + + IBUFDS_GTE4 ibufds_gte4_sfp_mgt_refclk_2_inst ( + .I (sfp_mgt_refclk_2_p), + .IB (sfp_mgt_refclk_2_n), + .CEB (1'b0), + .O (sfp_mgt_refclk_2), + .ODIV2 (sfp_mgt_refclk_2_int) + ); + + BUFG_GT bufg_gt_sfp_mgt_refclk_2_inst ( + .CE (sfp_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (sfp_mgt_refclk_2_int), + .O (sfp_mgt_refclk_2_bufg) + ); + +end + +taxi_sync_reset #( + .N(4) +) +sfp_sync_reset_inst ( + .clk(sfp_mgt_refclk_2_bufg), + .rst(rst_125mhz), + .out(sfp_rst) +); + +taxi_apb_if #( + .ADDR_W(18), + .DATA_W(16) +) +gt_apb_ctrl(); + +taxi_eth_mac_25g_us #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + + .CNT(2), + + // GT config + .CFG_LOW_LATENCY(1), + + // GT type + .GT_TYPE("GTY"), + + // PHY parameters + .DATA_W(axis_sfp_tx[0].DATA_W), + .PADDING_EN(1'b1), + .DIC_EN(1'b1), + .MIN_FRAME_LEN(64), + .PTP_TS_EN(1'b0), + .PTP_TD_EN(1'b0), + .PTP_TS_FMT_TOD(1'b1), + .PTP_TS_W(96), + .PTP_TD_SDI_PIPELINE(2), + .PRBS31_EN(1'b0), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/6.4), + .STAT_EN(1'b0) +) +sfp_mac_inst ( + .xcvr_ctrl_clk(clk_125mhz), + .xcvr_ctrl_rst(sfp_rst), + + /* + * Transceiver control + */ + .s_apb_ctrl(gt_apb_ctrl), + + /* + * Common + */ + .xcvr_gtpowergood_out(sfp_gtpowergood), + .xcvr_gtrefclk00_in(sfp_mgt_refclk_2), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(sfp_mgt_refclk_2), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), + + /* + * Serial data + */ + .xcvr_txp(sfp_tx_p), + .xcvr_txn(sfp_tx_n), + .xcvr_rxp(sfp_rx_p), + .xcvr_rxn(sfp_rx_n), + + /* + * MAC clocks + */ + .rx_clk(sfp_rx_clk), + .rx_rst_in('{2{1'b0}}), + .rx_rst_out(sfp_rx_rst), + .tx_clk(sfp_tx_clk), + .tx_rst_in('{2{1'b0}}), + .tx_rst_out(sfp_tx_rst), + + /* + * Transmit interface (AXI stream) + */ + .s_axis_tx(axis_sfp_tx), + .m_axis_tx_cpl(axis_sfp_tx_cpl), + + /* + * Receive interface (AXI stream) + */ + .m_axis_rx(axis_sfp_rx), + + /* + * PTP clock + */ + .ptp_clk(1'b0), + .ptp_rst(1'b0), + .ptp_sample_clk(1'b0), + .ptp_td_sdi(1'b0), + .tx_ptp_ts_in('{2{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{2{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), + + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + .tx_lfc_req('{2{1'b0}}), + .tx_lfc_resend('{2{1'b0}}), + .rx_lfc_en('{2{1'b0}}), + .rx_lfc_req(), + .rx_lfc_ack('{2{1'b0}}), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) + */ + .tx_pfc_req('{2{'0}}), + .tx_pfc_resend('{2{1'b0}}), + .rx_pfc_en('{2{'0}}), + .rx_pfc_req(), + .rx_pfc_ack('{2{'0}}), + + /* + * Pause interface + */ + .tx_lfc_pause_en('{2{1'b0}}), + .tx_pause_req('{2{1'b0}}), + .tx_pause_ack(), + + /* + * Statistics + */ + .stat_clk(clk_125mhz), + .stat_rst(rst_125mhz), + .m_axis_stat(axis_sfp_stat), + + /* + * Status + */ + .tx_start_packet(), + .stat_tx_byte(), + .stat_tx_pkt_len(), + .stat_tx_pkt_ucast(), + .stat_tx_pkt_mcast(), + .stat_tx_pkt_bcast(), + .stat_tx_pkt_vlan(), + .stat_tx_pkt_good(), + .stat_tx_pkt_bad(), + .stat_tx_err_oversize(), + .stat_tx_err_user(), + .stat_tx_err_underflow(), + .rx_start_packet(), + .rx_error_count(), + .rx_block_lock(), + .rx_high_ber(), + .rx_status(sfp_rx_status), + .stat_rx_byte(), + .stat_rx_pkt_len(), + .stat_rx_pkt_fragment(), + .stat_rx_pkt_jabber(), + .stat_rx_pkt_ucast(), + .stat_rx_pkt_mcast(), + .stat_rx_pkt_bcast(), + .stat_rx_pkt_vlan(), + .stat_rx_pkt_good(), + .stat_rx_pkt_bad(), + .stat_rx_err_oversize(), + .stat_rx_err_bad_fcs(), + .stat_rx_err_bad_block(), + .stat_rx_err_framing(), + .stat_rx_err_preamble(), + .stat_rx_fifo_drop('{2{1'b0}}), + .stat_tx_mcf(), + .stat_rx_mcf(), + .stat_tx_lfc_pkt(), + .stat_tx_lfc_xon(), + .stat_tx_lfc_xoff(), + .stat_tx_lfc_paused(), + .stat_tx_pfc_pkt(), + .stat_tx_pfc_xon(), + .stat_tx_pfc_xoff(), + .stat_tx_pfc_paused(), + .stat_rx_lfc_pkt(), + .stat_rx_lfc_xon(), + .stat_rx_lfc_xoff(), + .stat_rx_lfc_paused(), + .stat_rx_pfc_pkt(), + .stat_rx_pfc_xon(), + .stat_rx_pfc_xoff(), + .stat_rx_pfc_paused(), + + /* + * Configuration + */ + .cfg_tx_max_pkt_len('{2{16'd9218}}), + .cfg_tx_ifg('{2{8'd12}}), + .cfg_tx_enable('{2{1'b1}}), + .cfg_rx_max_pkt_len('{2{16'd9218}}), + .cfg_rx_enable('{2{1'b1}}), + .cfg_tx_prbs31_enable('{2{1'b0}}), + .cfg_rx_prbs31_enable('{2{1'b0}}), + .cfg_mcf_rx_eth_dst_mcast('{2{48'h01_80_C2_00_00_01}}), + .cfg_mcf_rx_check_eth_dst_mcast('{2{1'b1}}), + .cfg_mcf_rx_eth_dst_ucast('{2{48'd0}}), + .cfg_mcf_rx_check_eth_dst_ucast('{2{1'b0}}), + .cfg_mcf_rx_eth_src('{2{48'd0}}), + .cfg_mcf_rx_check_eth_src('{2{1'b0}}), + .cfg_mcf_rx_eth_type('{2{16'h8808}}), + .cfg_mcf_rx_opcode_lfc('{2{16'h0001}}), + .cfg_mcf_rx_check_opcode_lfc('{2{1'b1}}), + .cfg_mcf_rx_opcode_pfc('{2{16'h0101}}), + .cfg_mcf_rx_check_opcode_pfc('{2{1'b1}}), + .cfg_mcf_rx_forward('{2{1'b0}}), + .cfg_mcf_rx_enable('{2{1'b0}}), + .cfg_tx_lfc_eth_dst('{2{48'h01_80_C2_00_00_01}}), + .cfg_tx_lfc_eth_src('{2{48'h80_23_31_43_54_4C}}), + .cfg_tx_lfc_eth_type('{2{16'h8808}}), + .cfg_tx_lfc_opcode('{2{16'h0001}}), + .cfg_tx_lfc_en('{2{1'b0}}), + .cfg_tx_lfc_quanta('{2{16'hffff}}), + .cfg_tx_lfc_refresh('{2{16'h7fff}}), + .cfg_tx_pfc_eth_dst('{2{48'h01_80_C2_00_00_01}}), + .cfg_tx_pfc_eth_src('{2{48'h80_23_31_43_54_4C}}), + .cfg_tx_pfc_eth_type('{2{16'h8808}}), + .cfg_tx_pfc_opcode('{2{16'h0101}}), + .cfg_tx_pfc_en('{2{1'b0}}), + .cfg_tx_pfc_quanta('{2{'{8{16'hffff}}}}), + .cfg_tx_pfc_refresh('{2{'{8{16'h7fff}}}}), + .cfg_rx_lfc_opcode('{2{16'h0001}}), + .cfg_rx_lfc_en('{2{1'b0}}), + .cfg_rx_pfc_opcode('{2{16'h0101}}), + .cfg_rx_pfc_en('{2{1'b0}}) +); + +for (genvar n = 0; n < 2; n = n + 1) begin : sfp_ch + + taxi_axis_async_fifo #( + .DEPTH(16384), + .RAM_PIPELINE(2), + .FRAME_FIFO(1), + .USER_BAD_FRAME_VALUE(1'b1), + .USER_BAD_FRAME_MASK(1'b1), + .DROP_OVERSIZE_FRAME(1), + .DROP_BAD_FRAME(1), + .DROP_WHEN_FULL(1) + ) + ch_fifo ( + /* + * AXI4-Stream input (sink) + */ + .s_clk(sfp_rx_clk[n]), + .s_rst(sfp_rx_rst[n]), + .s_axis(axis_sfp_rx[n]), + + /* + * AXI4-Stream output (source) + */ + .m_clk(sfp_tx_clk[n]), + .m_rst(sfp_tx_rst[n]), + .m_axis(axis_sfp_tx[n]), + + /* + * Pause + */ + .s_pause_req(1'b0), + .s_pause_ack(), + .m_pause_req(1'b0), + .m_pause_ack(), + + /* + * Status + */ + .s_status_depth(), + .s_status_depth_commit(), + .s_status_overflow(), + .s_status_bad_frame(), + .s_status_good_frame(), + .m_status_depth(), + .m_status_depth_commit(), + .m_status_overflow(), + .m_status_bad_frame(), + .m_status_good_frame() + ); + +end + +endmodule + +`resetall diff --git a/src/eth/example/XEM8320/fpga/tb/fpga_core/Makefile b/src/eth/example/XEM8320/fpga/tb/fpga_core/Makefile new file mode 100644 index 0000000..3b082ec --- /dev/null +++ b/src/eth/example/XEM8320/fpga/tb/fpga_core/Makefile @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2020-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +DUT = fpga_core +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_SIM := "1'b1" +export PARAM_VENDOR := "\"XILINX\"" +export PARAM_FAMILY := "\"artixuplus\"" + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/eth/example/XEM8320/fpga/tb/fpga_core/baser.py b/src/eth/example/XEM8320/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/eth/example/XEM8320/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/src/eth/example/XEM8320/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/XEM8320/fpga/tb/fpga_core/test_fpga_core.py new file mode 100644 index 0000000..cbdcd1c --- /dev/null +++ b/src/eth/example/XEM8320/fpga/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,223 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: MIT +""" + +Copyright (c) 2020-2026 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import logging +import os +import sys + +import pytest +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Combine + +from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink +from cocotbext.eth import XgmiiFrame +from cocotbext.uart import UartSource, UartSink + +try: + from baser import BaseRSerdesSource, BaseRSerdesSink +except ImportError: + # attempt import from current directory + sys.path.insert(0, os.path.join(os.path.dirname(__file__))) + try: + from baser import BaseRSerdesSource, BaseRSerdesSink + finally: + del sys.path[0] + + +class TB: + def __init__(self, dut, speed=1000e6): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start()) + + self.sfp_sources = [] + self.sfp_sinks = [] + + cocotb.start_soon(Clock(dut.sfp_mgt_refclk_2_p, 6.4, units="ns").start()) + + for ch in dut.sfp_mac_inst.ch: + gt_inst = ch.ch_inst.gt.gt_inst + + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None + + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + + self.sfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.sfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) + + async def init(self): + + self.dut.rst_125mhz.setimmediatevalue(0) + + for k in range(10): + await RisingEdge(self.dut.clk_125mhz) + + self.dut.rst_125mhz.value = 1 + + for k in range(10): + await RisingEdge(self.dut.clk_125mhz) + + self.dut.rst_125mhz.value = 0 + + for k in range(10): + await RisingEdge(self.dut.clk_125mhz) + + +async def mac_test_10g(tb, source, sink): + tb.log.info("Test MAC") + + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk_125mhz) + + tb.log.info("Multiple small packets") + + count = 64 + + pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] + + for p in pkts: + await source.send(XgmiiFrame.from_payload(p)) + + for k in range(count): + rx_frame = await sink.recv() + + tb.log.info("RX frame: %s", rx_frame) + + assert rx_frame.get_payload() == pkts[k] + assert rx_frame.check_fcs() + + tb.log.info("Multiple large packets") + + count = 32 + + pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] + + for p in pkts: + await source.send(XgmiiFrame.from_payload(p)) + + for k in range(count): + rx_frame = await sink.recv() + + tb.log.info("RX frame: %s", rx_frame) + + assert rx_frame.get_payload() == pkts[k] + assert rx_frame.check_fcs() + + tb.log.info("MAC test done") + + +@cocotb.test() +async def run_test(dut): + + tb = TB(dut) + + await tb.init() + + tests = [] + + for k in range(len(tb.sfp_sources)): + tb.log.info("Start SFP %d 10G MAC loopback test", k) + tests.append(cocotb.start_soon(mac_test_10g(tb, tb.sfp_sources[k], tb.sfp_sinks[k]))) + + await Combine(*tests) + + await RisingEdge(dut.clk_125mhz) + await RisingEdge(dut.clk_125mhz) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['SIM'] = "1'b1" + parameters['VENDOR'] = "\"XILINX\"" + parameters['FAMILY'] = "\"artixuplus\"" + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + )