eth: Capture TX tag on the first cylce of the packet

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/eth/rtl/taxi_axis_baser_tx_32.sv

@@ -375,7 +375,6 @@ always_comb begin
         if (PTP_TS_EN) begin
             m_axis_tx_cpl_ts_next = ptp_ts;
         end
-        m_axis_tx_cpl_tag_next = s_axis_tx.tid;
         if (TX_CPL_CTRL_IN_TUSER) begin
             m_axis_tx_cpl_valid_next = (s_axis_tx.tuser >> 1) == 0;
         end else begin
@@ -475,6 +474,8 @@ always_comb begin
                 s_tdata_next = s_axis_tx_tdata_masked;
                 s_empty_next = keep2empty(s_axis_tx.tkeep);
 
+                m_axis_tx_cpl_tag_next = s_axis_tx.tid;
+
                 if (s_axis_tx.tvalid && cfg_tx_enable) begin
                     // Preamble and SFD
                     output_data_next = {4{ETH_PRE}};

src/eth/rtl/taxi_axis_baser_tx_64.sv

@@ -211,7 +211,7 @@ logic s_axis_tx_tready_reg = 1'b0, s_axis_tx_tready_next;
 
 logic [PTP_TS_W-1:0] m_axis_tx_cpl_ts_reg = '0;
 logic [PTP_TS_W-1:0] m_axis_tx_cpl_ts_adj_reg = '0;
-logic [TX_TAG_W-1:0] m_axis_tx_cpl_tag_reg = '0;
+logic [TX_TAG_W-1:0] m_axis_tx_cpl_tag_reg = '0, m_axis_tx_cpl_tag_next;
 logic m_axis_tx_cpl_valid_reg = 1'b0;
 logic m_axis_tx_cpl_valid_int_reg = 1'b0;
 logic m_axis_tx_cpl_ts_borrow_reg = 1'b0;
@@ -411,6 +411,8 @@ always_comb begin
     s_tdata_next = s_tdata_reg;
     s_empty_next = s_empty_reg;
 
+    m_axis_tx_cpl_tag_next = m_axis_tx_cpl_tag_reg;
+
     output_data_next = s_tdata_reg;
     output_type_next = OUTPUT_TYPE_IDLE;
 
@@ -502,6 +504,8 @@ always_comb begin
                 s_tdata_next = s_axis_tx_tdata_masked;
                 s_empty_next = keep2empty(s_axis_tx.tkeep);
 
+                m_axis_tx_cpl_tag_next = s_axis_tx.tid;
+
                 if (s_axis_tx.tvalid && s_axis_tx.tready) begin
                     // Preamble and SFD
                     output_data_next = {ETH_SFD, {7{ETH_PRE}}};
@@ -764,6 +768,7 @@ always_ff @(posedge clk) begin
 
     s_axis_tx_tready_reg <= s_axis_tx_tready_next;
 
+    m_axis_tx_cpl_tag_reg <= m_axis_tx_cpl_tag_next;
     m_axis_tx_cpl_valid_reg <= 1'b0;
     m_axis_tx_cpl_valid_int_reg <= 1'b0;
 
@@ -818,7 +823,6 @@ always_ff @(posedge clk) begin
                 end
                 start_packet_reg <= 2'b01;
             end
-            m_axis_tx_cpl_tag_reg <= s_axis_tx.tid;
             if (TX_CPL_CTRL_IN_TUSER) begin
                 if (PTP_TS_FMT_TOD) begin
                     m_axis_tx_cpl_valid_int_reg <= (s_axis_tx.tuser >> 1) == 0;

src/eth/rtl/taxi_axis_gmii_tx.sv

@@ -233,7 +233,6 @@ always_comb begin
 
     if (start_packet_reg) begin
         m_axis_tx_cpl_ts_next = ptp_ts;
-        m_axis_tx_cpl_tag_next = s_axis_tx.tid;
         if (TX_CPL_CTRL_IN_TUSER) begin
             m_axis_tx_cpl_valid_next = (s_axis_tx.tuser >> 1) == 0;
         end else begin
@@ -348,6 +347,8 @@ always_comb begin
                 gmii_txd_next = '0;
                 gmii_tx_en_next = 1'b0;
 
+                m_axis_tx_cpl_tag_next = s_axis_tx.tid;
+
                 if (s_axis_tx.tvalid && cfg_tx_enable) begin
                     mii_odd_next = 1'b1;
                     gmii_txd_next = ETH_PRE;

src/eth/rtl/taxi_axis_xgmii_tx_32.sv

@@ -324,7 +324,6 @@ always_comb begin
         if (PTP_TS_EN) begin
             m_axis_tx_cpl_ts_next = ptp_ts;
         end
-        m_axis_tx_cpl_tag_next = s_axis_tx.tid;
         if (TX_CPL_CTRL_IN_TUSER) begin
             m_axis_tx_cpl_valid_next = (s_axis_tx.tuser >> 1) == 0;
         end else begin
@@ -427,6 +426,8 @@ always_comb begin
                 s_tdata_next = s_axis_tx_tdata_masked;
                 s_empty_next = keep2empty(s_axis_tx.tkeep);
 
+                m_axis_tx_cpl_tag_next = s_axis_tx.tid;
+
                 if (s_axis_tx.tvalid && cfg_tx_enable) begin
                     // XGMII start and preamble
                     xgmii_txd_next = {{3{ETH_PRE}}, XGMII_START};

src/eth/rtl/taxi_axis_xgmii_tx_64.sv

@@ -160,7 +160,7 @@ logic s_axis_tx_tready_reg = 1'b0, s_axis_tx_tready_next;
 
 logic [PTP_TS_W-1:0] m_axis_tx_cpl_ts_reg = '0;
 logic [PTP_TS_W-1:0] m_axis_tx_cpl_ts_adj_reg = '0;
-logic [TX_TAG_W-1:0] m_axis_tx_cpl_tag_reg = '0;
+logic [TX_TAG_W-1:0] m_axis_tx_cpl_tag_reg = '0, m_axis_tx_cpl_tag_next;
 logic m_axis_tx_cpl_valid_reg = 1'b0;
 logic m_axis_tx_cpl_valid_int_reg = 1'b0;
 logic m_axis_tx_cpl_ts_borrow_reg = 1'b0;
@@ -355,6 +355,8 @@ always_comb begin
     s_tdata_next = s_tdata_reg;
     s_empty_next = s_empty_reg;
 
+    m_axis_tx_cpl_tag_next = m_axis_tx_cpl_tag_reg;
+
     // XGMII idle
     xgmii_txd_next = {CTRL_W{XGMII_IDLE}};
     xgmii_txc_next = {CTRL_W{1'b1}};
@@ -448,6 +450,8 @@ always_comb begin
                 s_tdata_next = s_axis_tx_tdata_masked;
                 s_empty_next = keep2empty(s_axis_tx.tkeep);
 
+                m_axis_tx_cpl_tag_next = s_axis_tx.tid;
+
                 if (s_axis_tx.tvalid && s_axis_tx.tready) begin
                     // XGMII start, preamble, and SFD
                     xgmii_txd_next = {ETH_SFD, {6{ETH_PRE}}, XGMII_START};
@@ -708,6 +712,7 @@ always_ff @(posedge clk) begin
 
     s_axis_tx_tready_reg <= s_axis_tx_tready_next;
 
+    m_axis_tx_cpl_tag_reg <= m_axis_tx_cpl_tag_next;
     m_axis_tx_cpl_valid_reg <= 1'b0;
     m_axis_tx_cpl_valid_int_reg <= 1'b0;
 
@@ -754,7 +759,6 @@ always_ff @(posedge clk) begin
                 end
                 start_packet_reg <= 2'b01;
             end
-            m_axis_tx_cpl_tag_reg <= s_axis_tx.tid;
             if (TX_CPL_CTRL_IN_TUSER) begin
                 if (PTP_TS_FMT_TOD) begin
                     m_axis_tx_cpl_valid_int_reg <= (s_axis_tx.tuser >> 1) == 0;