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dma: Clean up array init

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2026-03-08 14:41:24 -07:00
parent 9d701c9186
commit 4b7ca2a569
8 changed files with 51 additions and 159 deletions
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18
src/dma/rtl/taxi_dma_psdpram.sv
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@@ -58,26 +58,12 @@ if (SEGS != dma_ram_rd.SEGS || SEG_DATA_W != dma_ram_rd.SEG_DATA_W)
for (genvar n = 0; n < SEGS; n = n + 1) begin
(* ramstyle = "no_rw_check" *)
logic [SEG_DATA_W-1:0] mem_reg[2**INT_ADDR_W];
logic [SEG_DATA_W-1:0] mem_reg[2**INT_ADDR_W] = '{default: '0};
logic wr_done_reg = 1'b0;
logic [PIPELINE-1:0] rd_resp_valid_pipe_reg = '0;
logic [SEG_DATA_W-1:0] rd_resp_data_pipe_reg[PIPELINE];
initial begin
// two nested loops for smaller number of iterations per loop
// workaround for synthesizer complaints about large loop counts
for (integer i = 0; i < 2**INT_ADDR_W; i = i + 2**(INT_ADDR_W/2)) begin
for (integer j = i; j < i + 2**(INT_ADDR_W/2); j = j + 1) begin
mem_reg[j] = '0;
end
end
for (integer i = 0; i < PIPELINE; i = i + 1) begin
rd_resp_data_pipe_reg[i] = '0;
end
end
logic [SEG_DATA_W-1:0] rd_resp_data_pipe_reg[PIPELINE] = '{default: '0};
always_ff @(posedge clk) begin
wr_done_reg <= 1'b0;