dma: Clean up array init

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/dma/rtl/taxi_dma_if_axi_rd.sv

@@ -328,46 +328,29 @@ logic op_tbl_finish_en;
 
 logic [2**OP_TAG_W-1:0] op_tbl_active = '0;
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [AXI_ADDR_W-1:0] op_tbl_axi_addr[2**OP_TAG_W];
+logic [AXI_ADDR_W-1:0] op_tbl_axi_addr[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [RAM_SEL_W-1:0] op_tbl_ram_sel[2**OP_TAG_W];
+logic [RAM_SEL_W-1:0] op_tbl_ram_sel[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [RAM_ADDR_W-1:0] op_tbl_ram_addr[2**OP_TAG_W];
+logic [RAM_ADDR_W-1:0] op_tbl_ram_addr[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [12:0] op_tbl_len[2**OP_TAG_W];
+logic [12:0] op_tbl_len[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic op_tbl_zero_len[2**OP_TAG_W];
+logic op_tbl_zero_len[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [CYCLE_COUNT_W-1:0] op_tbl_cycle_count[2**OP_TAG_W];
+logic [CYCLE_COUNT_W-1:0] op_tbl_cycle_count[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [TAG_W-1:0] op_tbl_tag[2**OP_TAG_W];
+logic [TAG_W-1:0] op_tbl_tag[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic op_tbl_last[2**OP_TAG_W];
+logic op_tbl_last[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic op_tbl_write_complete[2**OP_TAG_W];
+logic op_tbl_write_complete[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic op_tbl_error_a[2**OP_TAG_W];
+logic op_tbl_error_a[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic op_tbl_error_b[2**OP_TAG_W];
+logic op_tbl_error_b[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [3:0] op_tbl_error_code[2**OP_TAG_W];
+logic [3:0] op_tbl_error_code[2**OP_TAG_W] = '{default: '0};
-
-initial begin
-    for (integer i = 0; i < 2**OP_TAG_W; i = i + 1) begin
-        op_tbl_axi_addr[i] = '0;
-        op_tbl_ram_sel[i] = '0;
-        op_tbl_ram_addr[i] = '0;
-        op_tbl_len[i] = '0;
-        op_tbl_zero_len[i] = 1'b0;
-        op_tbl_cycle_count[i] = '0;
-        op_tbl_tag[i] = '0;
-        op_tbl_last[i] = '0;
-        op_tbl_write_complete[i] = '0;
-        op_tbl_error_a[i] = '0;
-        op_tbl_error_b[i] = '0;
-        op_tbl_error_code[i] = '0;
-    end
-end
 
 always_comb begin
     req_state_next = REQ_STATE_IDLE;

src/dma/rtl/taxi_dma_if_axi_wr.sv

@@ -357,40 +357,25 @@ logic op_tbl_finish_en;
 logic [2**OP_TAG_W-1:0] op_tbl_active = '0;
 logic [2**OP_TAG_W-1:0] op_tbl_write_complete = '0;
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [AXI_ADDR_W-1:0] op_tbl_axi_addr[2**OP_TAG_W];
+logic [AXI_ADDR_W-1:0] op_tbl_axi_addr[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [IMM_W-1:0] op_tbl_imm[2**OP_TAG_W];
+logic [IMM_W-1:0] op_tbl_imm[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic op_tbl_imm_en[2**OP_TAG_W];
+logic op_tbl_imm_en[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [12:0] op_tbl_len[2**OP_TAG_W];
+logic [12:0] op_tbl_len[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic op_tbl_zero_len[2**OP_TAG_W];
+logic op_tbl_zero_len[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [CYCLE_COUNT_W-1:0] op_tbl_cycle_count[2**OP_TAG_W];
+logic [CYCLE_COUNT_W-1:0] op_tbl_cycle_count[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [RAM_OFFSET_W-1:0] op_tbl_offset[2**OP_TAG_W];
+logic [RAM_OFFSET_W-1:0] op_tbl_offset[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [TAG_W-1:0] op_tbl_tag[2**OP_TAG_W];
+logic [TAG_W-1:0] op_tbl_tag[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic op_tbl_last[2**OP_TAG_W];
+logic op_tbl_last[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [3:0] op_tbl_error_code[2**OP_TAG_W];
+logic [3:0] op_tbl_error_code[2**OP_TAG_W] = '{default: '0};
-
-initial begin
-    for (integer i = 0; i < 2**OP_TAG_W; i = i + 1) begin
-        op_tbl_axi_addr[i] = '0;
-        op_tbl_imm[i] = '0;
-        op_tbl_imm_en[i] = '0;
-        op_tbl_len[i] = '0;
-        op_tbl_zero_len[i] = 1'b0;
-        op_tbl_cycle_count[i] = '0;
-        op_tbl_offset[i] = '0;
-        op_tbl_tag[i] = '0;
-        op_tbl_last[i] = '0;
-        op_tbl_error_code[i] = '0;
-    end
-end
 
 always_comb begin
     req_state_next = REQ_STATE_IDLE;

src/dma/rtl/taxi_dma_if_pcie_us_rd.sv

@@ -484,17 +484,17 @@ logic [PCIE_TAG_W-1:0] pcie_tag_table_finish_ptr;
 logic pcie_tag_table_finish_en;
 
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [RAM_SEL_W-1:0] pcie_tag_table_ram_sel[2**PCIE_TAG_W];
+logic [RAM_SEL_W-1:0] pcie_tag_table_ram_sel[2**PCIE_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [RAM_ADDR_W-1:0] pcie_tag_table_ram_addr[2**PCIE_TAG_W];
+logic [RAM_ADDR_W-1:0] pcie_tag_table_ram_addr[2**PCIE_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [OP_TAG_W-1:0] pcie_tag_table_op_tag[2**PCIE_TAG_W];
+logic [OP_TAG_W-1:0] pcie_tag_table_op_tag[2**PCIE_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic pcie_tag_table_zero_len[2**PCIE_TAG_W];
+logic pcie_tag_table_zero_len[2**PCIE_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic pcie_tag_table_active_a[2**PCIE_TAG_W];
+logic pcie_tag_table_active_a[2**PCIE_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic pcie_tag_table_active_b[2**PCIE_TAG_W];
+logic pcie_tag_table_active_b[2**PCIE_TAG_W] = '{default: '0};
 
 logic [PCIE_TAG_W-1:0] pcie_tag_fifo_wr_tag;
 
@@ -524,23 +524,23 @@ logic [OP_TAG_W-1:0] op_tbl_rd_finish_ptr;
 logic op_tbl_rd_finish_en;
 
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [TAG_W-1:0] op_tbl_tag [2**OP_TAG_W];
+logic [TAG_W-1:0] op_tbl_tag [2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic op_tbl_rd_init_a [2**OP_TAG_W];
+logic op_tbl_rd_init_a [2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic op_tbl_rd_init_b [2**OP_TAG_W];
+logic op_tbl_rd_init_b [2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic op_tbl_rd_commit [2**OP_TAG_W];
+logic op_tbl_rd_commit [2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [OP_TBL_RD_COUNT_W-1:0] op_tbl_rd_count_start [2**OP_TAG_W];
+logic [OP_TBL_RD_COUNT_W-1:0] op_tbl_rd_count_start [2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [OP_TBL_RD_COUNT_W-1:0] op_tbl_rd_count_finish [2**OP_TAG_W];
+logic [OP_TBL_RD_COUNT_W-1:0] op_tbl_rd_count_finish [2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic op_tbl_error_a [2**OP_TAG_W];
+logic op_tbl_error_a [2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic op_tbl_error_b [2**OP_TAG_W];
+logic op_tbl_error_b [2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [3:0] op_tbl_error_code [2**OP_TAG_W];
+logic [3:0] op_tbl_error_code [2**OP_TAG_W] = '{default: '0};
 
 logic [OP_TAG_W+1-1:0] op_tag_fifo_wr_ptr_reg = '0;
 logic [OP_TAG_W+1-1:0] op_tag_fifo_rd_ptr_reg = '0, op_tag_fifo_rd_ptr_next;
@@ -549,29 +549,6 @@ logic [OP_TAG_W-1:0] op_tag_fifo_mem [2**OP_TAG_W];
 logic [OP_TAG_W-1:0] op_tag_fifo_wr_tag;
 logic op_tag_fifo_we;
 
-initial begin
-    for (integer i = 0; i < 2**OP_TAG_W; i = i + 1) begin
-        op_tbl_tag[i] = '0;
-        op_tbl_rd_init_a[i] = '0;
-        op_tbl_rd_init_b[i] = '0;
-        op_tbl_rd_commit[i] = '0;
-        op_tbl_rd_count_start[i] = '0;
-        op_tbl_rd_count_finish[i] = '0;
-        op_tbl_error_a[i] = '0;
-        op_tbl_error_b[i] = '0;
-        op_tbl_error_code[i] = '0;
-    end
-
-    for (integer i = 0; i < 2**PCIE_TAG_W; i = i + 1) begin
-        pcie_tag_table_ram_sel[i] = '0;
-        pcie_tag_table_ram_addr[i] = '0;
-        pcie_tag_table_op_tag[i] = '0;
-        pcie_tag_table_zero_len[i] = '0;
-        pcie_tag_table_active_a[i] = '0;
-        pcie_tag_table_active_b[i] = '0;
-    end
-end
-
 always_comb begin
     req_state_next = REQ_STATE_IDLE;
 

src/dma/rtl/taxi_dma_if_pcie_us_wr.sv

@@ -405,34 +405,21 @@ logic op_tbl_finish_en;
 logic [2**OP_TAG_W-1:0] op_tbl_active = '0;
 logic [2**OP_TAG_W-1:0] op_tbl_tx_done = '0;
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [PCIE_ADDR_W-1:0] op_tbl_pcie_addr[2**OP_TAG_W];
+logic [PCIE_ADDR_W-1:0] op_tbl_pcie_addr[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [11:0] op_tbl_len[2**OP_TAG_W];
+logic [11:0] op_tbl_len[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic op_tbl_zero_len[2**OP_TAG_W];
+logic op_tbl_zero_len[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [10:0] op_tbl_dword_len[2**OP_TAG_W];
+logic [10:0] op_tbl_dword_len[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [CYCLE_COUNT_W-1:0] op_tbl_cycle_count[2**OP_TAG_W];
+logic [CYCLE_COUNT_W-1:0] op_tbl_cycle_count[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [RAM_OFFSET_W-1:0] op_tbl_offset[2**OP_TAG_W];
+logic [RAM_OFFSET_W-1:0] op_tbl_offset[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic [TAG_W-1:0] op_tbl_tag[2**OP_TAG_W];
+logic [TAG_W-1:0] op_tbl_tag[2**OP_TAG_W] = '{default: '0};
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-logic op_tbl_last[2**OP_TAG_W];
+logic op_tbl_last[2**OP_TAG_W] = '{default: '0};
-
-initial begin
-    for (integer i = 0; i < 2**OP_TAG_W; i = i + 1) begin
-        op_tbl_pcie_addr[i] = '0;
-        op_tbl_len[i] = '0;
-        op_tbl_zero_len[i] = '0;
-        op_tbl_dword_len[i] = '0;
-        op_tbl_cycle_count[i] = '0;
-        op_tbl_offset[i] = '0;
-        op_tbl_tag[i] = '0;
-        op_tbl_last[i] = '0;
-    end
-end
 
 always_comb begin
     req_state_next = REQ_STATE_IDLE;

src/dma/rtl/taxi_dma_psdpram.sv

@@ -58,26 +58,12 @@ if (SEGS != dma_ram_rd.SEGS || SEG_DATA_W != dma_ram_rd.SEG_DATA_W)
 for (genvar n = 0; n < SEGS; n = n + 1) begin
 
     (* ramstyle = "no_rw_check" *)
-    logic [SEG_DATA_W-1:0] mem_reg[2**INT_ADDR_W];
+    logic [SEG_DATA_W-1:0] mem_reg[2**INT_ADDR_W] = '{default: '0};
 
     logic wr_done_reg = 1'b0;
 
     logic [PIPELINE-1:0] rd_resp_valid_pipe_reg = '0;
-    logic [SEG_DATA_W-1:0] rd_resp_data_pipe_reg[PIPELINE];
+    logic [SEG_DATA_W-1:0] rd_resp_data_pipe_reg[PIPELINE] = '{default: '0};
-
-    initial begin
-        // two nested loops for smaller number of iterations per loop
-        // workaround for synthesizer complaints about large loop counts
-        for (integer i = 0; i < 2**INT_ADDR_W; i = i + 2**(INT_ADDR_W/2)) begin
-            for (integer j = i; j < i + 2**(INT_ADDR_W/2); j = j + 1) begin
-                mem_reg[j] = '0;
-            end
-        end
-
-        for (integer i = 0; i < PIPELINE; i = i + 1) begin
-            rd_resp_data_pipe_reg[i] = '0;
-        end
-    end
 
     always_ff @(posedge clk) begin
         wr_done_reg <= 1'b0;

src/dma/rtl/taxi_dma_psdpram_async.sv

@@ -59,26 +59,12 @@ if (SEGS != dma_ram_rd.SEGS || SEG_DATA_W != dma_ram_rd.SEG_DATA_W)
 for (genvar n = 0; n < SEGS; n = n + 1) begin
 
     (* ramstyle = "no_rw_check" *)
-    logic [SEG_DATA_W-1:0] mem_reg[2**INT_ADDR_W];
+    logic [SEG_DATA_W-1:0] mem_reg[2**INT_ADDR_W] = '{default: '0};
 
     logic wr_done_reg = 1'b0;
 
     logic [PIPELINE-1:0] rd_resp_valid_pipe_reg = '0;
-    logic [SEG_DATA_W-1:0] rd_resp_data_pipe_reg[PIPELINE];
+    logic [SEG_DATA_W-1:0] rd_resp_data_pipe_reg[PIPELINE] = '{default: '0};
-
-    initial begin
-        // two nested loops for smaller number of iterations per loop
-        // workaround for synthesizer complaints about large loop counts
-        for (integer i = 0; i < 2**INT_ADDR_W; i = i + 2**(INT_ADDR_W/2)) begin
-            for (integer j = i; j < i + 2**(INT_ADDR_W/2); j = j + 1) begin
-                mem_reg[j] = '0;
-            end
-        end
-
-        for (integer i = 0; i < PIPELINE; i = i + 1) begin
-            rd_resp_data_pipe_reg[i] = '0;
-        end
-    end
 
     always_ff @(posedge clk_wr) begin
         wr_done_reg <= 1'b0;

src/dma/rtl/taxi_dma_ram_demux_rd.sv

@@ -76,17 +76,11 @@ for (genvar n = 0; n < SEGS; n = n + 1) begin
         logic [FIFO_AW+1-1:0] fifo_wr_ptr_reg = '0;
         logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = '0;
         (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-        logic [CL_PORTS-1:0] fifo_sel[2**FIFO_AW];
+        logic [CL_PORTS-1:0] fifo_sel[2**FIFO_AW] = '{default: '0};
 
         wire fifo_empty = fifo_wr_ptr_reg == fifo_rd_ptr_reg;
         wire fifo_full = fifo_wr_ptr_reg == (fifo_rd_ptr_reg ^ (1 << FIFO_AW));
 
-        initial begin
-            for (integer i = 0; i < 2**FIFO_AW; i = i + 1) begin
-                fifo_sel[i] = '0;
-            end
-        end
-
         // RAM read command demux
 
         wire [DMA_SEL_W-1:0]   seg_ctrl_rd_cmd_sel   = dma_ram_rd.rd_cmd_sel[n];

src/dma/rtl/taxi_dma_ram_demux_wr.sv

@@ -76,17 +76,11 @@ for (genvar n = 0; n < SEGS; n = n + 1) begin
         logic [FIFO_AW+1-1:0] fifo_wr_ptr_reg = '0;
         logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = '0;
         (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-        logic [CL_PORTS-1:0] fifo_sel[2**FIFO_AW];
+        logic [CL_PORTS-1:0] fifo_sel[2**FIFO_AW] = '{default: '0};
 
         wire fifo_empty = fifo_wr_ptr_reg == fifo_rd_ptr_reg;
         wire fifo_full = fifo_wr_ptr_reg == (fifo_rd_ptr_reg ^ (1 << FIFO_AW));
 
-        initial begin
-            for (integer i = 0; i < 2**FIFO_AW; i = i + 1) begin
-                fifo_sel[i] = '0;
-            end
-        end
-
         // RAM write command demux
 
         wire [DMA_SEL_W-1:0]   seg_ctrl_wr_cmd_sel   = dma_ram_wr.wr_cmd_sel[n];