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eth: Modularize NetFPGA SUME constraint files

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-04-14 23:50:25 -07:00
parent c227f43556
commit 4c12434f10
7 changed files with 229 additions and 186 deletions
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185
src/eth/example/NetFPGA_SUME/fpga/fpga.xdc
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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2014-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# XDC constraints for the Xilinx VC709
# part: xc7vx690tffg1761-2
# General configuration
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
# 200 MHz system clock
set_property -dict {LOC H19 IOSTANDARD LVDS} [get_ports clk_200mhz_p]
set_property -dict {LOC G18 IOSTANDARD LVDS} [get_ports clk_200mhz_n]
create_clock -period 5 -name clk_200mhz [get_ports clk_200mhz_p]
# 200 MHz QDRII A/B MIG clock
#set_property -dict {LOC AD32 IOSTANDARD LVDS} [get_ports clk_qdrii_200mhz_p]
#set_property -dict {LOC AD33 IOSTANDARD LVDS} [get_ports clk_qdrii_200mhz_n]
#create_clock -period 5 -name clk_qdrii_200mhz [get_ports clk_qdrii_200mhz_p]
# 200 MHz QDRII C MIG clock
#set_property -dict {LOC AU14 IOSTANDARD LVDS} [get_ports clk_qdriic_200mhz_p]
#set_property -dict {LOC AU13 IOSTANDARD LVDS} [get_ports clk_qdriic_200mhz_n]
#create_clock -period 5 -name clk_qdriic_200mhz [get_ports clk_qdriic_200mhz_p]
# 233.33 MHz DDR3 MIG clock
#set_property -dict {LOC E34 IOSTANDARD LVDS} [get_ports clk_ddr_233mhz_p]
#set_property -dict {LOC E35 IOSTANDARD LVDS} [get_ports clk_ddr_233mhz_n]
#create_clock -period 4.286 -name clk_ddr_233mhz [get_ports clk_ddr_233mhz_p]
# LEDs
set_property -dict {LOC G13 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0][0]}]
set_property -dict {LOC L15 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0][1]}]
set_property -dict {LOC AL22 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1][0]}]
set_property -dict {LOC BA20 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1][1]}]
set_property -dict {LOC AY18 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[2][0]}]
set_property -dict {LOC AY17 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[2][1]}]
set_property -dict {LOC P31 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[3][0]}]
set_property -dict {LOC K32 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[3][1]}]
set_property -dict {LOC AR22 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {led[0]}]
set_property -dict {LOC AR23 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {led[1]}]
set_false_path -to [get_ports {sfp_led[*][*] led[*]}]
set_output_delay 0 [get_ports {sfp_led[*][*] led[*]}]
# Push buttons
set_property -dict {LOC AR13 IOSTANDARD LVCMOS15} [get_ports {btn[0]}]
set_property -dict {LOC BB12 IOSTANDARD LVCMOS15} [get_ports {btn[1]}]
set_false_path -from [get_ports {btn[*]}]
set_input_delay 0 [get_ports {btn[*]}]
# UART (IC47 FT2232HQ)
set_property -dict {LOC BA19 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# IC47.38 RXD_I
set_property -dict {LOC AY19 IOSTANDARD LVCMOS15} [get_ports {uart_rxd}] ;# IC47.39 TXD_O
set_property -dict {LOC BB16 IOSTANDARD LVCMOS15} [get_ports {uart_rts}] ;# IC47.40 RTS_O_B
set_property -dict {LOC BA16 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# IC47.41 CTS_I_B
set_false_path -to [get_ports {uart_txd uart_cts}]
set_output_delay 0 [get_ports {uart_txd uart_cts}]
set_false_path -from [get_ports {uart_rxd uart_rts}]
set_input_delay 0 [get_ports {uart_rxd uart_rts}]
# I2C interface
set_property -dict {LOC AK24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports i2c_scl]
set_property -dict {LOC AK25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports i2c_sda]
set_property -dict {LOC AM39 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports i2c_mux_reset]
set_false_path -to [get_ports {i2c_sda i2c_scl i2c_mux_reset}]
set_output_delay 0 [get_ports {i2c_sda i2c_scl i2c_mux_reset}]
set_false_path -from [get_ports {i2c_sda i2c_scl}]
set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
# SFP+ Interfaces
set_property -dict {LOC A6 } [get_ports {sfp_rx_p[0]}] ;# MGTHRXP3_119 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
set_property -dict {LOC A5 } [get_ports {sfp_rx_n[0]}] ;# MGTHRXN3_119 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
set_property -dict {LOC B4 } [get_ports {sfp_tx_p[0]}] ;# MGTHTXP3_119 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
set_property -dict {LOC B3 } [get_ports {sfp_tx_n[0]}] ;# MGTHTXN3_119 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
set_property -dict {LOC B8 } [get_ports {sfp_rx_p[1]}] ;# MGTHRXP2_119 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
set_property -dict {LOC B7 } [get_ports {sfp_rx_n[1]}] ;# MGTHRXN2_119 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
set_property -dict {LOC C2 } [get_ports {sfp_tx_p[1]}] ;# MGTHTXP2_119 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
set_property -dict {LOC C1 } [get_ports {sfp_tx_n[1]}] ;# MGTHTXN2_119 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
set_property -dict {LOC C6 } [get_ports {sfp_rx_p[2]}] ;# MGTHRXP1_119 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
set_property -dict {LOC C5 } [get_ports {sfp_rx_n[2]}] ;# MGTHRXN1_119 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
set_property -dict {LOC D4 } [get_ports {sfp_tx_p[2]}] ;# MGTHTXP1_119 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
set_property -dict {LOC D3 } [get_ports {sfp_tx_n[2]}] ;# MGTHTXN1_119 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
set_property -dict {LOC D8 } [get_ports {sfp_rx_p[3]}] ;# MGTHRXP0_119 GTHE2_CHANNEL_X1Y36 / GTHE2_COMMON_X1Y9
set_property -dict {LOC D7 } [get_ports {sfp_rx_n[3]}] ;# MGTHRXN0_119 GTHE2_CHANNEL_X1Y36 / GTHE2_COMMON_X1Y9
set_property -dict {LOC E2 } [get_ports {sfp_tx_p[3]}] ;# MGTHTXP0_119 GTHE2_CHANNEL_X1Y36 / GTHE2_COMMON_X1Y9
set_property -dict {LOC E1 } [get_ports {sfp_tx_n[3]}] ;# MGTHTXN0_119 GTHE2_CHANNEL_X1Y36 / GTHE2_COMMON_X1Y9
set_property -dict {LOC E10 } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_118 from IC20.28
set_property -dict {LOC E9 } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_118 from IC20.29
#set_property -dict {LOC AW32 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to IC20.16
#set_property -dict {LOC AW33 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to IC20.17
set_property -dict {LOC BA29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5324_rst]
set_property -dict {LOC AM29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports si5324_int]
set_property -dict {LOC N18 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_mod_detect[0]}]
set_property -dict {LOC L19 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_mod_detect[1]}]
set_property -dict {LOC J37 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_mod_detect[2]}]
set_property -dict {LOC H36 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_mod_detect[3]}]
set_property -dict {LOC N19 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0][0]}]
set_property -dict {LOC P18 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0][1]}]
set_property -dict {LOC P20 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1][0]}]
set_property -dict {LOC N20 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1][1]}]
set_property -dict {LOC F39 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[2][0]}]
set_property -dict {LOC G36 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[2][1]}]
set_property -dict {LOC H38 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[3][0]}]
set_property -dict {LOC G38 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[3][1]}]
set_property -dict {LOC L17 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_los[0]}]
set_property -dict {LOC L20 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_los[1]}]
set_property -dict {LOC G37 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_los[2]}]
set_property -dict {LOC J36 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_los[3]}]
set_property -dict {LOC M18 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[0]}]
set_property -dict {LOC B31 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[1]}]
set_property -dict {LOC J38 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[2]}]
set_property -dict {LOC L21 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[3]}]
set_property -dict {LOC M19 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_tx_fault[0]}]
set_property -dict {LOC C26 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_tx_fault[1]}]
set_property -dict {LOC E39 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_tx_fault[2]}]
set_property -dict {LOC J26 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_tx_fault[3]}]
# 156.25 MHz MGT reference clock
create_clock -period 6.4 -name sfp_mgt_refclk [get_ports sfp_mgt_refclk_p]
set_false_path -to [get_ports {si5324_rst}]
set_output_delay 0 [get_ports {si5324_rst}]
set_false_path -from [get_ports {si5324_int}]
set_input_delay 0 [get_ports {si5324_int}]
set_false_path -from [get_ports {sfp_mod_detect[*] sfp_los[*] sfp_tx_fault[*]}]
set_input_delay 0 [get_ports {sfp_mod_detect[*] sfp_los[*] sfp_tx_fault[*]}]
set_false_path -to [get_ports {sfp_rs[*][*] sfp_tx_disable[*]}]
set_output_delay 0 [get_ports {sfp_rs[*][*] sfp_tx_disable[*]}]
# PCIe Interface
#set_property -dict {LOC Y4 } [get_ports {pcie_rx_p[0]}] ;# MGTHTXP3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC Y3 } [get_ports {pcie_rx_n[0]}] ;# MGTHTXN3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC W2 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC W1 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC AA6 } [get_ports {pcie_rx_p[1]}] ;# MGTHTXP2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC AA5 } [get_ports {pcie_rx_n[1]}] ;# MGTHTXN2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC AA2 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC AA1 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC AB4 } [get_ports {pcie_rx_p[2]}] ;# MGTHTXP1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC AB3 } [get_ports {pcie_rx_n[2]}] ;# MGTHTXN1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC AC2 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC AC1 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC AC6 } [get_ports {pcie_rx_p[3]}] ;# MGTHTXP0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC AC5 } [get_ports {pcie_rx_n[3]}] ;# MGTHTXN0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC AE2 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC AE1 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
#set_property -dict {LOC AD4 } [get_ports {pcie_rx_p[4]}] ;# MGTHTXP3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AD3 } [get_ports {pcie_rx_n[4]}] ;# MGTHTXN3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AG2 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AG1 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AE6 } [get_ports {pcie_rx_p[5]}] ;# MGTHTXP2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AE5 } [get_ports {pcie_rx_n[5]}] ;# MGTHTXN2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AH4 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AH3 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AF4 } [get_ports {pcie_rx_p[6]}] ;# MGTHTXP1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AF3 } [get_ports {pcie_rx_n[6]}] ;# MGTHTXN1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AJ2 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AJ1 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AG6 } [get_ports {pcie_rx_p[7]}] ;# MGTHTXP0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AG5 } [get_ports {pcie_rx_n[7]}] ;# MGTHTXN0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AK4 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AK3 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
#set_property -dict {LOC AB8 } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK1P_115
#set_property -dict {LOC AB7 } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK1N_115
#set_property -dict {LOC AY35 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
# 100 MHz MGT reference clock
#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
#set_false_path -from [get_ports {pcie_reset_n}]
#set_input_delay 0 [get_ports {pcie_reset_n}]

5
src/eth/example/NetFPGA_SUME/fpga/fpga/Makefile
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@@ -31,7 +31,10 @@ SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
# XDC files # XDC files
XDC_FILES = ../fpga.xdc XDC_FILES += ../syn/fpga.xdc
XDC_FILES += ../syn/gpio.xdc
XDC_FILES += ../syn/i2c.xdc
XDC_FILES += ../syn/sfp.xdc
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_phy_10g_7_gt.tcl XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_phy_10g_7_gt.tcl
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl

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src/eth/example/NetFPGA_SUME/fpga/syn/fpga.xdc Normal file
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@@ -0,0 +1,36 @@
# SPDX-License-Identifier: MIT
#
# Copyright (c) 2014-2026 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# XDC constraints for the Xilinx VC709
# part: xc7vx690tffg1761-2
# General configuration
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
# 200 MHz system clock
set_property -dict {LOC H19 IOSTANDARD LVDS} [get_ports clk_200mhz_p]
set_property -dict {LOC G18 IOSTANDARD LVDS} [get_ports clk_200mhz_n]
create_clock -period 5 -name clk_200mhz [get_ports clk_200mhz_p]
# 200 MHz QDRII A/B MIG clock
#set_property -dict {LOC AD32 IOSTANDARD LVDS} [get_ports clk_qdrii_200mhz_p]
#set_property -dict {LOC AD33 IOSTANDARD LVDS} [get_ports clk_qdrii_200mhz_n]
#create_clock -period 5 -name clk_qdrii_200mhz [get_ports clk_qdrii_200mhz_p]
# 200 MHz QDRII C MIG clock
#set_property -dict {LOC AU14 IOSTANDARD LVDS} [get_ports clk_qdriic_200mhz_p]
#set_property -dict {LOC AU13 IOSTANDARD LVDS} [get_ports clk_qdriic_200mhz_n]
#create_clock -period 5 -name clk_qdriic_200mhz [get_ports clk_qdriic_200mhz_p]
# 233.33 MHz DDR3 MIG clock
#set_property -dict {LOC E34 IOSTANDARD LVDS} [get_ports clk_ddr_233mhz_p]
#set_property -dict {LOC E35 IOSTANDARD LVDS} [get_ports clk_ddr_233mhz_n]
#create_clock -period 4.286 -name clk_ddr_233mhz [get_ports clk_ddr_233mhz_p]

43
src/eth/example/NetFPGA_SUME/fpga/syn/gpio.xdc Normal file
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@@ -0,0 +1,43 @@
# SPDX-License-Identifier: MIT
#
# Copyright (c) 2014-2026 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# XDC constraints for the Xilinx VC709
# part: xc7vx690tffg1761-2
# LEDs
set_property -dict {LOC G13 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0][0]}]
set_property -dict {LOC L15 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[0][1]}]
set_property -dict {LOC AL22 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1][0]}]
set_property -dict {LOC BA20 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[1][1]}]
set_property -dict {LOC AY18 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[2][0]}]
set_property -dict {LOC AY17 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[2][1]}]
set_property -dict {LOC P31 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[3][0]}]
set_property -dict {LOC K32 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_led[3][1]}]
set_property -dict {LOC AR22 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {led[0]}]
set_property -dict {LOC AR23 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {led[1]}]
set_false_path -to [get_ports {sfp_led[*][*] led[*]}]
set_output_delay 0 [get_ports {sfp_led[*][*] led[*]}]
# Push buttons
set_property -dict {LOC AR13 IOSTANDARD LVCMOS15} [get_ports {btn[0]}]
set_property -dict {LOC BB12 IOSTANDARD LVCMOS15} [get_ports {btn[1]}]
set_false_path -from [get_ports {btn[*]}]
set_input_delay 0 [get_ports {btn[*]}]
# UART (IC47 FT2232HQ)
set_property -dict {LOC BA19 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# IC47.38 RXD_I
set_property -dict {LOC AY19 IOSTANDARD LVCMOS15} [get_ports {uart_rxd}] ;# IC47.39 TXD_O
set_property -dict {LOC BB16 IOSTANDARD LVCMOS15} [get_ports {uart_rts}] ;# IC47.40 RTS_O_B
set_property -dict {LOC BA16 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# IC47.41 CTS_I_B
set_false_path -to [get_ports {uart_txd uart_cts}]
set_output_delay 0 [get_ports {uart_txd uart_cts}]
set_false_path -from [get_ports {uart_rxd uart_rts}]
set_input_delay 0 [get_ports {uart_rxd uart_rts}]

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src/eth/example/NetFPGA_SUME/fpga/syn/i2c.xdc Normal file
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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2014-2026 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# XDC constraints for the Xilinx VC709
# part: xc7vx690tffg1761-2
# I2C interface
set_property -dict {LOC AK24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports i2c_scl]
set_property -dict {LOC AK25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports i2c_sda]
set_property -dict {LOC AM39 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports i2c_mux_reset]
set_false_path -to [get_ports {i2c_sda i2c_scl i2c_mux_reset}]
set_output_delay 0 [get_ports {i2c_sda i2c_scl i2c_mux_reset}]
set_false_path -from [get_ports {i2c_sda i2c_scl}]
set_input_delay 0 [get_ports {i2c_sda i2c_scl}]

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src/eth/example/NetFPGA_SUME/fpga/syn/pcie.xdc Normal file
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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2014-2026 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# XDC constraints for the Xilinx VC709
# part: xc7vx690tffg1761-2
# PCIe Interface
set_property -dict {LOC Y4 } [get_ports {pcie_rx_p[0]}] ;# MGTHTXP3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
set_property -dict {LOC Y3 } [get_ports {pcie_rx_n[0]}] ;# MGTHTXN3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
set_property -dict {LOC W2 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
set_property -dict {LOC W1 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
set_property -dict {LOC AA6 } [get_ports {pcie_rx_p[1]}] ;# MGTHTXP2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
set_property -dict {LOC AA5 } [get_ports {pcie_rx_n[1]}] ;# MGTHTXN2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
set_property -dict {LOC AA2 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
set_property -dict {LOC AA1 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
set_property -dict {LOC AB4 } [get_ports {pcie_rx_p[2]}] ;# MGTHTXP1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
set_property -dict {LOC AB3 } [get_ports {pcie_rx_n[2]}] ;# MGTHTXN1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
set_property -dict {LOC AC2 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
set_property -dict {LOC AC1 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
set_property -dict {LOC AC6 } [get_ports {pcie_rx_p[3]}] ;# MGTHTXP0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
set_property -dict {LOC AC5 } [get_ports {pcie_rx_n[3]}] ;# MGTHTXN0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
set_property -dict {LOC AE2 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
set_property -dict {LOC AE1 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
set_property -dict {LOC AD4 } [get_ports {pcie_rx_p[4]}] ;# MGTHTXP3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AD3 } [get_ports {pcie_rx_n[4]}] ;# MGTHTXN3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AG2 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AG1 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AE6 } [get_ports {pcie_rx_p[5]}] ;# MGTHTXP2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AE5 } [get_ports {pcie_rx_n[5]}] ;# MGTHTXN2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AH4 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AH3 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AF4 } [get_ports {pcie_rx_p[6]}] ;# MGTHTXP1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AF3 } [get_ports {pcie_rx_n[6]}] ;# MGTHTXN1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AJ2 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AJ1 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AG6 } [get_ports {pcie_rx_p[7]}] ;# MGTHTXP0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AG5 } [get_ports {pcie_rx_n[7]}] ;# MGTHTXN0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AK4 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AK3 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
set_property -dict {LOC AB8 } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK1P_115
set_property -dict {LOC AB7 } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK1N_115
set_property -dict {LOC AY35 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
# 100 MHz MGT reference clock
create_clock -period 10.000 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
set_false_path -from [get_ports {pcie_reset_n}]
set_input_delay 0 [get_ports {pcie_reset_n}]

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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2014-2026 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# XDC constraints for the Xilinx VC709
# part: xc7vx690tffg1761-2
# SFP+ Interfaces
set_property -dict {LOC A6 } [get_ports {sfp_rx_p[0]}] ;# MGTHRXP3_119 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
set_property -dict {LOC A5 } [get_ports {sfp_rx_n[0]}] ;# MGTHRXN3_119 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
set_property -dict {LOC B4 } [get_ports {sfp_tx_p[0]}] ;# MGTHTXP3_119 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
set_property -dict {LOC B3 } [get_ports {sfp_tx_n[0]}] ;# MGTHTXN3_119 GTHE2_CHANNEL_X1Y39 / GTHE2_COMMON_X1Y9
set_property -dict {LOC B8 } [get_ports {sfp_rx_p[1]}] ;# MGTHRXP2_119 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
set_property -dict {LOC B7 } [get_ports {sfp_rx_n[1]}] ;# MGTHRXN2_119 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
set_property -dict {LOC C2 } [get_ports {sfp_tx_p[1]}] ;# MGTHTXP2_119 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
set_property -dict {LOC C1 } [get_ports {sfp_tx_n[1]}] ;# MGTHTXN2_119 GTHE2_CHANNEL_X1Y38 / GTHE2_COMMON_X1Y9
set_property -dict {LOC C6 } [get_ports {sfp_rx_p[2]}] ;# MGTHRXP1_119 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
set_property -dict {LOC C5 } [get_ports {sfp_rx_n[2]}] ;# MGTHRXN1_119 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
set_property -dict {LOC D4 } [get_ports {sfp_tx_p[2]}] ;# MGTHTXP1_119 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
set_property -dict {LOC D3 } [get_ports {sfp_tx_n[2]}] ;# MGTHTXN1_119 GTHE2_CHANNEL_X1Y37 / GTHE2_COMMON_X1Y9
set_property -dict {LOC D8 } [get_ports {sfp_rx_p[3]}] ;# MGTHRXP0_119 GTHE2_CHANNEL_X1Y36 / GTHE2_COMMON_X1Y9
set_property -dict {LOC D7 } [get_ports {sfp_rx_n[3]}] ;# MGTHRXN0_119 GTHE2_CHANNEL_X1Y36 / GTHE2_COMMON_X1Y9
set_property -dict {LOC E2 } [get_ports {sfp_tx_p[3]}] ;# MGTHTXP0_119 GTHE2_CHANNEL_X1Y36 / GTHE2_COMMON_X1Y9
set_property -dict {LOC E1 } [get_ports {sfp_tx_n[3]}] ;# MGTHTXN0_119 GTHE2_CHANNEL_X1Y36 / GTHE2_COMMON_X1Y9
set_property -dict {LOC E10 } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_118 from IC20.28
set_property -dict {LOC E9 } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_118 from IC20.29
#set_property -dict {LOC AW32 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to IC20.16
#set_property -dict {LOC AW33 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to IC20.17
set_property -dict {LOC BA29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5324_rst]
set_property -dict {LOC AM29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports si5324_int]
set_property -dict {LOC N18 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_mod_detect[0]}]
set_property -dict {LOC L19 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_mod_detect[1]}]
set_property -dict {LOC J37 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_mod_detect[2]}]
set_property -dict {LOC H36 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_mod_detect[3]}]
set_property -dict {LOC N19 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0][0]}]
set_property -dict {LOC P18 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0][1]}]
set_property -dict {LOC P20 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1][0]}]
set_property -dict {LOC N20 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1][1]}]
set_property -dict {LOC F39 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[2][0]}]
set_property -dict {LOC G36 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[2][1]}]
set_property -dict {LOC H38 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[3][0]}]
set_property -dict {LOC G38 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[3][1]}]
set_property -dict {LOC L17 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_los[0]}]
set_property -dict {LOC L20 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_los[1]}]
set_property -dict {LOC G37 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_los[2]}]
set_property -dict {LOC J36 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_los[3]}]
set_property -dict {LOC M18 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[0]}]
set_property -dict {LOC B31 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[1]}]
set_property -dict {LOC J38 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[2]}]
set_property -dict {LOC L21 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[3]}]
set_property -dict {LOC M19 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_tx_fault[0]}]
set_property -dict {LOC C26 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_tx_fault[1]}]
set_property -dict {LOC E39 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_tx_fault[2]}]
set_property -dict {LOC J26 IOSTANDARD LVCMOS15 PULLUP true} [get_ports {sfp_tx_fault[3]}]
# 156.25 MHz MGT reference clock
create_clock -period 6.4 -name sfp_mgt_refclk [get_ports sfp_mgt_refclk_p]
set_false_path -to [get_ports {si5324_rst}]
set_output_delay 0 [get_ports {si5324_rst}]
set_false_path -from [get_ports {si5324_int}]
set_input_delay 0 [get_ports {si5324_int}]
set_false_path -from [get_ports {sfp_mod_detect[*] sfp_los[*] sfp_tx_fault[*]}]
set_input_delay 0 [get_ports {sfp_mod_detect[*] sfp_los[*] sfp_tx_fault[*]}]
set_false_path -to [get_ports {sfp_rs[*][*] sfp_tx_disable[*]}]
set_output_delay 0 [get_ports {sfp_rs[*][*] sfp_tx_disable[*]}]