diff --git a/src/eth/example/HTG9200/fpga/README.md b/src/eth/example/HTG9200/fpga/README.md index 93fc0d8..02a65da 100644 --- a/src/eth/example/HTG9200/fpga/README.md +++ b/src/eth/example/HTG9200/fpga/README.md @@ -2,7 +2,7 @@ ## Introduction -This example design targets the HiTech Global HTG-9200 FPGA board. +This example design targets the HiTech Global HTG-9200 FPGA board. Design variants are provided for both the bare HTG-9200, as well as the HTG-9200 with the HiTech Global HTG-FMC-X6QSFP28 FMC+ board installed on J9. The design places looped-back MACs on the Ethernet ports, as well as XFCP on the USB UART for monitoring and control. @@ -63,4 +63,6 @@ The table below contains the power rail test points and feedback resistor values Run `make program` to program the board with Vivado. +LED D46 on the HTG-9200 indicates that the Si5341 PLL is locked and providing stable reference clocks to the transceivers. On the HTG-FMC-X6QSFP28 FMC+ board, LED D10 indicates that the Si5341 PLL is locked. + To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. diff --git a/src/eth/example/HTG9200/fpga/fmc_6qsfp.xdc b/src/eth/example/HTG9200/fpga/fmc_6qsfp.xdc new file mode 100644 index 0000000..989ffb9 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fmc_6qsfp.xdc @@ -0,0 +1,326 @@ +# XDC constraints for the HiTech Global HTG-9200 board with HTG-FMC-X6QSFP28 FMC+ +# part: xcvu9p-flgb2104-2-e +# part: xcvu13p-fhgb2104-2-e + +# FMC+ J9 +set_property -dict {LOC BA15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_lpmode] ;# J9.G9 LA00_P_CC +set_property -dict {LOC BA14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_resetl] ;# J9.G10 LA00_N_CC +set_property -dict {LOC AY13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_modprsl] ;# J9.D8 LA01_P_CC +set_property -dict {LOC BA13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_intl] ;# J9.D9 LA01_N_CC +set_property -dict {LOC AL15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_modsell] ;# J9.H7 LA02_P +set_property -dict {LOC AM15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_modprsl] ;# J9.H8 LA02_N +set_property -dict {LOC AN14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_intl] ;# J9.G12 LA03_P +set_property -dict {LOC AN13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_modsell] ;# J9.G13 LA03_N +set_property -dict {LOC AL14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_lpmode] ;# J9.H10 LA04_P +set_property -dict {LOC AM14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_resetl] ;# J9.H11 LA04_N +set_property -dict {LOC AP13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_modsell] ;# J9.D11 LA05_P +set_property -dict {LOC AR13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_intl] ;# J9.D12 LA05_N +set_property -dict {LOC AP15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_resetl] ;# J9.C10 LA06_P +set_property -dict {LOC AP14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_lpmode] ;# J9.C11 LA06_N +set_property -dict {LOC AU16 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_modprsl] ;# J9.H13 LA07_P +set_property -dict {LOC AV16 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_modsell] ;# J9.H14 LA07_N +set_property -dict {LOC AR16 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_lpmode] ;# J9.G12 LA08_P +set_property -dict {LOC AR15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_intl] ;# J9.G13 LA08_N +set_property -dict {LOC AT15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_modprsl] ;# J9.D14 LA09_P +set_property -dict {LOC AU15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_modsell] ;# J9.D15 LA09_N +set_property -dict {LOC AU14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_resetl] ;# J9.C14 LA10_P +set_property -dict {LOC AV14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_lpmode] ;# J9.C15 LA10_N +set_property -dict {LOC BD15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_intl] ;# J9.H16 LA11_P +set_property -dict {LOC BD14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_modprsl] ;# J9.H17 LA11_N +set_property -dict {LOC AY12 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_resetl] ;# J9.G15 LA12_P +set_property -dict {LOC AY11 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_lpmode] ;# J9.G16 LA12_N +set_property -dict {LOC BA12 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_intl] ;# J9.D17 LA13_P +set_property -dict {LOC BB12 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_modprsl] ;# J9.D18 LA13_N +set_property -dict {LOC BB15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_modsell] ;# J9.C18 LA14_P +set_property -dict {LOC BB14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_resetl] ;# J9.C19 LA14_N +set_property -dict {LOC BF14 IOSTANDARD LVCMOS18} [get_ports fmc_clk_finc] ;# J9.H19 LA15_P +set_property -dict {LOC BF13 IOSTANDARD LVCMOS18} [get_ports fmc_clk_fdec] ;# J9.H20 LA15_N +set_property -dict {LOC BD16 IOSTANDARD LVCMOS18} [get_ports fmc_clk_rst_n] ;# J9.G18 LA16_P +set_property -dict {LOC BE16 IOSTANDARD LVCMOS18} [get_ports fmc_clk_lol_n] ;# J9.G19 LA16_N +set_property -dict {LOC AT20 IOSTANDARD LVCMOS18} [get_ports fmc_clk_sync_n] ;# J9.D20 LA17_P_CC +set_property -dict {LOC AU20 IOSTANDARD LVCMOS18} [get_ports fmc_clk_intr_n] ;# J9.D21 LA17_N_CC +#set_property -dict {LOC AV19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[18]}] ;# J9.C22 LA18_P_CC +#set_property -dict {LOC AW19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[18]}] ;# J9.C23 LA18_N_CC +#set_property -dict {LOC AR17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[19]}] ;# J9.H22 LA19_P +#set_property -dict {LOC AT17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[19]}] ;# J9.H23 LA19_N +#set_property -dict {LOC AN18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[20]}] ;# J9.G21 LA20_P +#set_property -dict {LOC AN17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[20]}] ;# J9.G22 LA20_N +#set_property -dict {LOC AW20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[21]}] ;# J9.H25 LA21_P +#set_property -dict {LOC AY20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[21]}] ;# J9.H26 LA21_N +#set_property -dict {LOC AT19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[22]}] ;# J9.G24 LA22_P +#set_property -dict {LOC AU19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[22]}] ;# J9.G25 LA22_N +#set_property -dict {LOC AL17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[23]}] ;# J9.D23 LA23_P +#set_property -dict {LOC AM17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[23]}] ;# J9.D24 LA23_N +#set_property -dict {LOC AY17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[24]}] ;# J9.H28 LA24_P +#set_property -dict {LOC BA17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[24]}] ;# J9.H29 LA24_N +#set_property -dict {LOC AY18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[25]}] ;# J9.G27 LA25_P +#set_property -dict {LOC BA18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[25]}] ;# J9.G28 LA25_N +#set_property -dict {LOC AP20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[26]}] ;# J9.D26 LA26_P +#set_property -dict {LOC AP20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[26]}] ;# J9.D27 LA26_N +#set_property -dict {LOC AN19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[27]}] ;# J9.C26 LA27_P +#set_property -dict {LOC AP19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[27]}] ;# J9.C27 LA27_N +#set_property -dict {LOC BB17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[28]}] ;# J9.H31 LA28_P +#set_property -dict {LOC BC17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[28]}] ;# J9.H32 LA28_N +#set_property -dict {LOC BB19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[29]}] ;# J9.G30 LA29_P +#set_property -dict {LOC BC18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[29]}] ;# J9.G31 LA29_N +#set_property -dict {LOC BD18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[30]}] ;# J9.H34 LA30_P +#set_property -dict {LOC BE18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[30]}] ;# J9.H35 LA30_N +#set_property -dict {LOC BC19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[31]}] ;# J9.G33 LA31_P +#set_property -dict {LOC BD19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[31]}] ;# J9.G34 LA31_N +#set_property -dict {LOC BF19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[32]}] ;# J9.H37 LA32_P +#set_property -dict {LOC BF18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[32]}] ;# J9.H38 LA32_N +#set_property -dict {LOC BE17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[33]}] ;# J9.G36 LA33_P +#set_property -dict {LOC BF17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[33]}] ;# J9.G37 LA33_N + +#set_property -dict {LOC G14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[0]}] ;# J9.F4 HA00_P_CC +#set_property -dict {LOC F14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[0]}] ;# J9.F5 HA00_N_CC +#set_property -dict {LOC G15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[1]}] ;# J9.E2 HA01_P_CC +#set_property -dict {LOC F15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[1]}] ;# J9.E3 HA01_N_CC +#set_property -dict {LOC A14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[2]}] ;# J9.K7 HA02_P +#set_property -dict {LOC A13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[2]}] ;# J9.K8 HA02_N +#set_property -dict {LOC B17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[3]}] ;# J9.J6 HA03_P +#set_property -dict {LOC A17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[3]}] ;# J9.J7 HA03_N +#set_property -dict {LOC C16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[4]}] ;# J9.F7 HA04_P +#set_property -dict {LOC B16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[4]}] ;# J9.F8 HA04_N +#set_property -dict {LOC B15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[5]}] ;# J9.E6 HA05_P +#set_property -dict {LOC A15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[5]}] ;# J9.E7 HA05_N +#set_property -dict {LOC G17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[6]}] ;# J9.K10 HA06_P +#set_property -dict {LOC G16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[6]}] ;# J9.K11 HA06_N +#set_property -dict {LOC D13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[7]}] ;# J9.J9 HA07_P +#set_property -dict {LOC C13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[7]}] ;# J9.J10 HA07_N +#set_property -dict {LOC E15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[8]}] ;# J9.F10 HA08_P +#set_property -dict {LOC D15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[8]}] ;# J9.F11 HA08_N +#set_property -dict {LOC E16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[9]}] ;# J9.E9 HA09_P +#set_property -dict {LOC D16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[9]}] ;# J9.E10 HA09_N +#set_property -dict {LOC R16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[10]}] ;# J9.K13 HA10_P +#set_property -dict {LOC P16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[10]}] ;# J9.K14 HA10_N +#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[11]}] ;# J9.J12 HA11_P +#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[11]}] ;# J9.J13 HA11_N +#set_property -dict {LOC H17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[12]}] ;# J9.F13 HA12_P +#set_property -dict {LOC H16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[12]}] ;# J9.F14 HA12_N +#set_property -dict {LOC J13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[13]}] ;# J9.E12 HA13_P +#set_property -dict {LOC H13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[13]}] ;# J9.E13 HA13_N +#set_property -dict {LOC P14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[14]}] ;# J9.J15 HA14_P +#set_property -dict {LOC N14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[14]}] ;# J9.J16 HA14_N +#set_property -dict {LOC N16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[15]}] ;# J9.F14 HA15_P +#set_property -dict {LOC M16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[15]}] ;# J9.F16 HA15_N +#set_property -dict {LOC M14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[16]}] ;# J9.E15 HA16_P +#set_property -dict {LOC L14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[16]}] ;# J9.E16 HA16_N +#set_property -dict {LOC J14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[17]}] ;# J9.K16 HA17_P_CC +#set_property -dict {LOC H14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[17]}] ;# J9.K17 HA17_N_CC +#set_property -dict {LOC J16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[18]}] ;# J9.J18 HA18_P_CC +#set_property -dict {LOC J15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[18]}] ;# J9.J19 HA18_N_CC +#set_property -dict {LOC F13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[19]}] ;# J9.F19 HA19_P +#set_property -dict {LOC E13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[19]}] ;# J9.F20 HA19_N +#set_property -dict {LOC K16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[20]}] ;# J9.E18 HA20_P +#set_property -dict {LOC K15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[20]}] ;# J9.E19 HA20_N +#set_property -dict {LOC C14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[21]}] ;# J9.K19 HA21_P +#set_property -dict {LOC B14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[21]}] ;# J9.K20 HA21_N +#set_property -dict {LOC R15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[22]}] ;# J9.J21 HA22_P +#set_property -dict {LOC P15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[22]}] ;# J9.J22 HA22_N +#set_property -dict {LOC P13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[23]}] ;# J9.K22 HA23_P +#set_property -dict {LOC N13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[23]}] ;# J9.K23 HA23_N + +#set_property -dict {LOC H19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[0]}] ;# J9.K25 HB00_P_CC +#set_property -dict {LOC H18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[0]}] ;# J9.K26 HB00_N_CC +#set_property -dict {LOC D18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[1]}] ;# J9.J24 HB01_P +#set_property -dict {LOC C18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[1]}] ;# J9.J25 HB01_N +#set_property -dict {LOC D19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[2]}] ;# J9.F22 HB02_P +#set_property -dict {LOC C19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[2]}] ;# J9.F23 HB02_N +#set_property -dict {LOC B20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[3]}] ;# J9.E21 HB03_P +#set_property -dict {LOC A20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[3]}] ;# J9.E22 HB03_N +#set_property -dict {LOC F18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[4]}] ;# J9.F25 HB04_P +#set_property -dict {LOC F17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[4]}] ;# J9.F26 HB04_N +#set_property -dict {LOC E18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[5]}] ;# J9.E24 HB05_P +#set_property -dict {LOC E17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[5]}] ;# J9.E25 HB05_N +#set_property -dict {LOC J20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[6]}] ;# J9.K28 HB06_P_CC +#set_property -dict {LOC J19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[6]}] ;# J9.K29 HB06_N_CC +#set_property -dict {LOC F20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[7]}] ;# J9.J27 HB07_P +#set_property -dict {LOC F19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[7]}] ;# J9.J28 HB07_N +#set_property -dict {LOC J21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[8]}] ;# J9.F28 HB08_P +#set_property -dict {LOC H21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[8]}] ;# J9.F29 HB08_N +#set_property -dict {LOC G20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[9]}] ;# J9.E27 HB09_P +#set_property -dict {LOC G19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[9]}] ;# J9.E28 HB09_N +#set_property -dict {LOC P19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[10]}] ;# J9.K31 HB10_P +#set_property -dict {LOC N19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[10]}] ;# J9.K32 HB10_N +#set_property -dict {LOC L17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[11]}] ;# J9.J30 HB11_P +#set_property -dict {LOC K17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[11]}] ;# J9.J31 HB11_N +#set_property -dict {LOC L19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[12]}] ;# J9.F31 HB12_P +#set_property -dict {LOC L18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[12]}] ;# J9.F32 HB12_N +#set_property -dict {LOC N17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[13]}] ;# J9.E30 HB13_P +#set_property -dict {LOC M17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[13]}] ;# J9.E31 HB13_N +#set_property -dict {LOC N21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[14]}] ;# J9.K34 HB14_P +#set_property -dict {LOC M21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[14]}] ;# J9.K35 HB14_N +#set_property -dict {LOC R20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[15]}] ;# J9.J33 HB15_P +#set_property -dict {LOC P20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[15]}] ;# J9.J34 HB15_N +#set_property -dict {LOC L20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[16]}] ;# J9.F34 HB16_P +#set_property -dict {LOC K20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[16]}] ;# J9.F35 HB16_N +#set_property -dict {LOC K18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[17]}] ;# J9.K37 HB17_P_CC +#set_property -dict {LOC J18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[17]}] ;# J9.K38 HB17_N_CC +#set_property -dict {LOC C21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[18]}] ;# J9.J36 HB18_P +#set_property -dict {LOC B21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[18]}] ;# J9.J37 HB18_N +#set_property -dict {LOC E21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[19]}] ;# J9.E33 HB19_P +#set_property -dict {LOC E20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[19]}] ;# J9.E34 HB19_N +#set_property -dict {LOC B19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[20]}] ;# J9.F37 HB20_P +#set_property -dict {LOC A19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[20]}] ;# J9.F38 HB20_N +#set_property -dict {LOC D21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[21]}] ;# J9.E36 HB21_P +#set_property -dict {LOC D20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[21]}] ;# J9.E37 HB21_N + +#set_property -dict {LOC AW14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk0_m2c_p}] ;# J9.H4 CLK0_M2C_P +#set_property -dict {LOC AW13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk0_m2c_n}] ;# J9.H5 CLK0_M2C_N +#set_property -dict {LOC AV18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk1_m2c_p}] ;# J9.G2 CLK1_M2C_P +#set_property -dict {LOC AW18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk1_m2c_n}] ;# J9.G3 CLK1_M2C_N + +#set_property -dict {LOC G25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_user_def0_p}] ;# J9.L32 USER_DEF0_P +#set_property -dict {LOC G24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_user_def0_n}] ;# J9.L33 USER_DEF0_N +#set_property -dict {LOC F24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_refclk_m2c_p}] ;# J9.L24 REFCLK_M2C_P +#set_property -dict {LOC F23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_refclk_m2c_n}] ;# J9.L25 REFCLK_M2C_N +set_property -dict {LOC E23 IOSTANDARD LVDS } [get_ports {fmc_sync_c2m_p}] ;# J9.L16 SYNC_C2M_P +set_property -dict {LOC E22 IOSTANDARD LVDS } [get_ports {fmc_sync_c2m_n}] ;# J9.L17 SYNC_C2M_N +#set_property -dict {LOC J24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_sync_m2c_p}] ;# J9.L28 SYNC_M2C_P +#set_property -dict {LOC H24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_sync_m2c_n}] ;# J9.L29 SYNC_M2C_N + +#set_property -dict {LOC AV23 IOSTANDARD LVCMOS18} [get_ports {fmc_pg_m2c}] ;# J9.F1 PG_M2C +#set_property -dict {LOC AW23 IOSTANDARD LVCMOS18} [get_ports {fmc_prsnt_m2c_l}] ;# J9.H2 PRSNT_M2C_L +#set_property -dict {LOC BC23 IOSTANDARD LVCMOS18} [get_ports {fmc_hspc_prsnt_m2c_l}] ;# J9.Z1 HSPC_PRSNT_M2C_L + +set_property -dict {LOC Y7 } [get_ports {fmc_qsfp_1_tx_p[0]}] ;# MGTYTXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C2 DP0_C2M_P +set_property -dict {LOC Y6 } [get_ports {fmc_qsfp_1_tx_n[0]}] ;# MGTYTXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C3 DP0_C2M_N +set_property -dict {LOC Y2 } [get_ports {fmc_qsfp_1_rx_p[0]}] ;# MGTYRXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C6 DP0_M2C_P +set_property -dict {LOC Y1 } [get_ports {fmc_qsfp_1_rx_n[0]}] ;# MGTYRXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C7 DP0_M2C_N +set_property -dict {LOC V7 } [get_ports {fmc_qsfp_1_tx_p[2]}] ;# MGTYTXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A22 DP1_C2M_P +set_property -dict {LOC V6 } [get_ports {fmc_qsfp_1_tx_n[2]}] ;# MGTYTXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A23 DP1_C2M_N +set_property -dict {LOC V2 } [get_ports {fmc_qsfp_1_rx_p[2]}] ;# MGTYRXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A2 DP1_M2C_P +set_property -dict {LOC V1 } [get_ports {fmc_qsfp_1_rx_n[2]}] ;# MGTYRXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A3 DP1_M2C_N +set_property -dict {LOC W9 } [get_ports {fmc_qsfp_1_tx_p[1]}] ;# MGTYTXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A26 DP2_C2M_P +set_property -dict {LOC W8 } [get_ports {fmc_qsfp_1_tx_n[1]}] ;# MGTYTXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A27 DP2_C2M_N +set_property -dict {LOC W4 } [get_ports {fmc_qsfp_1_rx_p[1]}] ;# MGTYRXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A6 DP2_M2C_P +set_property -dict {LOC W3 } [get_ports {fmc_qsfp_1_rx_n[1]}] ;# MGTYRXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A7 DP2_M2C_N +set_property -dict {LOC AA9 } [get_ports {fmc_qsfp_1_tx_p[3]}] ;# MGTYTXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A30 DP3_C2M_P +set_property -dict {LOC AA8 } [get_ports {fmc_qsfp_1_tx_n[3]}] ;# MGTYTXN0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A31 DP3_C2M_N +set_property -dict {LOC AA4 } [get_ports {fmc_qsfp_1_rx_p[3]}] ;# MGTYRXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A10 DP3_M2C_P +set_property -dict {LOC AA3 } [get_ports {fmc_qsfp_1_rx_n[3]}] ;# MGTYRXN0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A11 DP3_M2C_N +set_property -dict {LOC Y11 } [get_ports fmc_qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_229 from J9.D4 GBTCLK0_M2C_P +set_property -dict {LOC Y10 } [get_ports fmc_qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_229 from J9.D5 GBTCLK0_M2C_N +#set_property -dict {LOC V11 } [get_ports fmc_mgt_refclk_0_1_p] ;# MGTREFCLK1P_229 from U27.14 OUT3 +#set_property -dict {LOC V10 } [get_ports fmc_mgt_refclk_0_1_n] ;# MGTREFCLK1N_229 from U27.13 OUT3B + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_1_mgt_refclk [get_ports fmc_qsfp_1_mgt_refclk_p] +#create_clock -period 6.206 -name fmc_mgt_refclk_0_1 [get_ports fmc_mgt_refclk_0_1_p] + +set_property -dict {LOC AC9 } [get_ports {fmc_qsfp_6_tx_p[1]}] ;# MGTYTXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A34 DP4_C2M_P +set_property -dict {LOC AC8 } [get_ports {fmc_qsfp_6_tx_n[1]}] ;# MGTYTXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A35 DP4_C2M_N +set_property -dict {LOC AC4 } [get_ports {fmc_qsfp_6_rx_p[1]}] ;# MGTYRXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A14 DP4_M2C_P +set_property -dict {LOC AC3 } [get_ports {fmc_qsfp_6_rx_n[1]}] ;# MGTYRXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A15 DP4_M2C_N +set_property -dict {LOC AE9 } [get_ports {fmc_qsfp_6_tx_p[0]}] ;# MGTYTXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A38 DP5_C2M_P +set_property -dict {LOC AE8 } [get_ports {fmc_qsfp_6_tx_n[0]}] ;# MGTYTXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A39 DP5_C2M_N +set_property -dict {LOC AE4 } [get_ports {fmc_qsfp_6_rx_p[0]}] ;# MGTYRXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A18 DP5_M2C_P +set_property -dict {LOC AE3 } [get_ports {fmc_qsfp_6_rx_n[0]}] ;# MGTYRXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A19 DP5_M2C_N +set_property -dict {LOC AD7 } [get_ports {fmc_qsfp_6_tx_p[2]}] ;# MGTYTXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B36 DP6_C2M_P +set_property -dict {LOC AD6 } [get_ports {fmc_qsfp_6_tx_n[2]}] ;# MGTYTXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B37 DP6_C2M_N +set_property -dict {LOC AD2 } [get_ports {fmc_qsfp_6_rx_p[2]}] ;# MGTYRXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B16 DP6_M2C_P +set_property -dict {LOC AD1 } [get_ports {fmc_qsfp_6_rx_n[2]}] ;# MGTYRXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B17 DP6_M2C_N +set_property -dict {LOC AB7 } [get_ports {fmc_qsfp_6_tx_p[3]}] ;# MGTYTXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B32 DP7_C2M_P +set_property -dict {LOC AB6 } [get_ports {fmc_qsfp_6_tx_n[3]}] ;# MGTYTXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B33 DP7_C2M_N +set_property -dict {LOC AB2 } [get_ports {fmc_qsfp_6_rx_p[3]}] ;# MGTYRXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B12 DP7_M2C_P +set_property -dict {LOC AB1 } [get_ports {fmc_qsfp_6_rx_n[3]}] ;# MGTYRXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B13 DP7_M2C_N +set_property -dict {LOC AD11} [get_ports fmc_qsfp_6_mgt_refclk_p] ;# MGTREFCLK0P_228 from J9.B20 GBTCLK1_M2C_P +set_property -dict {LOC AD10} [get_ports fmc_qsfp_6_mgt_refclk_n] ;# MGTREFCLK0N_228 from J9.B21 GBTCLK1_M2C_N + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_6_mgt_refclk [get_ports fmc_qsfp_6_mgt_refclk_p] + +set_property -dict {LOC L9 } [get_ports {fmc_qsfp_4_tx_p[3]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B28 DP8_C2M_P +set_property -dict {LOC L8 } [get_ports {fmc_qsfp_4_tx_n[3]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B29 DP8_C2M_N +set_property -dict {LOC L4 } [get_ports {fmc_qsfp_4_rx_p[3]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B8 DP8_M2C_P +set_property -dict {LOC L3 } [get_ports {fmc_qsfp_4_rx_n[3]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B9 DP8_M2C_N +set_property -dict {LOC K7 } [get_ports {fmc_qsfp_4_tx_p[2]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B24 DP9_C2M_P +set_property -dict {LOC K6 } [get_ports {fmc_qsfp_4_tx_n[2]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B25 DP9_C2M_N +set_property -dict {LOC K2 } [get_ports {fmc_qsfp_4_rx_p[2]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B4 DP9_M2C_P +set_property -dict {LOC K1 } [get_ports {fmc_qsfp_4_rx_n[2]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B5 DP9_M2C_N +set_property -dict {LOC M7 } [get_ports {fmc_qsfp_4_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Z24 DP10_C2M_P +set_property -dict {LOC M6 } [get_ports {fmc_qsfp_4_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Z25 DP10_C2M_N +set_property -dict {LOC M2 } [get_ports {fmc_qsfp_4_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Y10 DP10_M2C_P +set_property -dict {LOC M1 } [get_ports {fmc_qsfp_4_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Y11 DP10_M2C_N +set_property -dict {LOC N9 } [get_ports {fmc_qsfp_4_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Y26 DP11_C2M_P +set_property -dict {LOC N8 } [get_ports {fmc_qsfp_4_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Y27 DP11_C2M_N +set_property -dict {LOC N4 } [get_ports {fmc_qsfp_4_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Z12 DP11_M2C_P +set_property -dict {LOC N3 } [get_ports {fmc_qsfp_4_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Z13 DP11_M2C_N +set_property -dict {LOC M11 } [get_ports fmc_qsfp_4_mgt_refclk_p] ;# MGTREFCLK0P_231 from J9.L12 GBTCLK2_M2C_P +set_property -dict {LOC M10 } [get_ports fmc_qsfp_4_mgt_refclk_n] ;# MGTREFCLK0N_231 from J9.L13 GBTCLK2_M2C_N +#set_property -dict {LOC K11 } [get_ports fmc_mgt_refclk_2_1_p] ;# MGTREFCLK1P_231 from U27.17 OUT2 +#set_property -dict {LOC K10 } [get_ports fmc_mgt_refclk_2_1_n] ;# MGTREFCLK1N_231 from U27.16 OUT2B + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_4_mgt_refclk [get_ports fmc_qsfp_4_mgt_refclk_p] +#create_clock -period 6.206 -name fmc_mgt_refclk_2_1 [get_ports fmc_mgt_refclk_2_1_p] + +set_property -dict {LOC P7 } [get_ports {fmc_qsfp_3_tx_p[2]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Z28 DP12_C2M_P +set_property -dict {LOC P6 } [get_ports {fmc_qsfp_3_tx_n[2]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Z29 DP12_C2M_N +set_property -dict {LOC P2 } [get_ports {fmc_qsfp_3_rx_p[2]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Y14 DP12_M2C_P +set_property -dict {LOC P1 } [get_ports {fmc_qsfp_3_rx_n[2]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Y15 DP12_M2C_N +set_property -dict {LOC R9 } [get_ports {fmc_qsfp_3_tx_p[3]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Y30 DP13_C2M_P +set_property -dict {LOC R8 } [get_ports {fmc_qsfp_3_tx_n[3]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Y31 DP13_C2M_N +set_property -dict {LOC R4 } [get_ports {fmc_qsfp_3_rx_p[3]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Z16 DP13_M2C_P +set_property -dict {LOC R3 } [get_ports {fmc_qsfp_3_rx_n[3]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Z17 DP13_M2C_N +set_property -dict {LOC T7 } [get_ports {fmc_qsfp_3_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.M18 DP14_C2M_P +set_property -dict {LOC T6 } [get_ports {fmc_qsfp_3_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.M19 DP14_C2M_N +set_property -dict {LOC T2 } [get_ports {fmc_qsfp_3_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.Y18 DP14_M2C_P +set_property -dict {LOC T1 } [get_ports {fmc_qsfp_3_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.Y19 DP14_M2C_N +set_property -dict {LOC U9 } [get_ports {fmc_qsfp_3_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.M22 DP15_C2M_P +set_property -dict {LOC U8 } [get_ports {fmc_qsfp_3_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.M23 DP15_C2M_N +set_property -dict {LOC U4 } [get_ports {fmc_qsfp_3_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.Y22 DP15_M2C_P +set_property -dict {LOC U3 } [get_ports {fmc_qsfp_3_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.Y23 DP15_M2C_N +set_property -dict {LOC T11 } [get_ports fmc_qsfp_3_mgt_refclk_p] ;# MGTREFCLK0P_230 from J9.L8 GBTCLK3_M2C_P +set_property -dict {LOC T10 } [get_ports fmc_qsfp_3_mgt_refclk_n] ;# MGTREFCLK0N_230 from J9.L9 GBTCLK3_M2C_N + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_3_mgt_refclk [get_ports fmc_qsfp_3_mgt_refclk_p] + +set_property -dict {LOC AF7 } [get_ports {fmc_qsfp_5_tx_p[3]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.M26 DP16_C2M_P +set_property -dict {LOC AF6 } [get_ports {fmc_qsfp_5_tx_n[3]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.M27 DP16_C2M_N +set_property -dict {LOC AF2 } [get_ports {fmc_qsfp_5_rx_p[3]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.Z32 DP16_M2C_P +set_property -dict {LOC AF1 } [get_ports {fmc_qsfp_5_rx_n[3]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.Z33 DP16_M2C_N +set_property -dict {LOC AG9 } [get_ports {fmc_qsfp_5_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.M30 DP17_C2M_P +set_property -dict {LOC AG8 } [get_ports {fmc_qsfp_5_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.M31 DP17_C2M_N +set_property -dict {LOC AG4 } [get_ports {fmc_qsfp_5_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.Y34 DP17_M2C_P +set_property -dict {LOC AG3 } [get_ports {fmc_qsfp_5_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.Y35 DP17_M2C_N +set_property -dict {LOC AH7 } [get_ports {fmc_qsfp_5_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.M34 DP18_C2M_P +set_property -dict {LOC AH6 } [get_ports {fmc_qsfp_5_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.M35 DP18_C2M_N +set_property -dict {LOC AH2 } [get_ports {fmc_qsfp_5_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.Z36 DP18_M2C_P +set_property -dict {LOC AH1 } [get_ports {fmc_qsfp_5_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.Z37 DP18_M2C_N +set_property -dict {LOC AJ9 } [get_ports {fmc_qsfp_5_tx_p[0]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.M38 DP19_C2M_P +set_property -dict {LOC AJ8 } [get_ports {fmc_qsfp_5_tx_n[0]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.M39 DP19_C2M_N +set_property -dict {LOC AJ4 } [get_ports {fmc_qsfp_5_rx_p[0]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.Y38 DP19_M2C_P +set_property -dict {LOC AJ3 } [get_ports {fmc_qsfp_5_rx_n[0]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.Y39 DP19_M2C_N +set_property -dict {LOC AH11} [get_ports fmc_qsfp_5_mgt_refclk_p] ;# MGTREFCLK0P_227 from J9.L4 GBTCLK4_M2C_P +set_property -dict {LOC AH10} [get_ports fmc_qsfp_5_mgt_refclk_n] ;# MGTREFCLK0N_227 from J9.L5 GBTCLK4_M2C_N +#set_property -dict {LOC AF11} [get_ports fmc_mgt_refclk_4_1_p] ;# MGTREFCLK1P_227 from U27.11 OUT4 +#set_property -dict {LOC AF10} [get_ports fmc_mgt_refclk_4_1_n] ;# MGTREFCLK1N_227 from U27.12 OUT4B + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_5_mgt_refclk [get_ports fmc_qsfp_5_mgt_refclk_p] +#create_clock -period 6.206 -name fmc_mgt_refclk_4_1 [get_ports fmc_mgt_refclk_4_1_p] + +set_property -dict {LOC J9 } [get_ports {fmc_qsfp_2_tx_p[3]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.Z8 DP20_C2M_P +set_property -dict {LOC J8 } [get_ports {fmc_qsfp_2_tx_n[3]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.Z9 DP20_C2M_N +set_property -dict {LOC J4 } [get_ports {fmc_qsfp_2_rx_p[3]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.M14 DP20_M2C_P +set_property -dict {LOC J3 } [get_ports {fmc_qsfp_2_rx_n[3]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.M15 DP20_M2C_N +set_property -dict {LOC H7 } [get_ports {fmc_qsfp_2_tx_p[2]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.Y6 DP21_C2M_P +set_property -dict {LOC H6 } [get_ports {fmc_qsfp_2_tx_n[2]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.Y7 DP21_C2M_N +set_property -dict {LOC H2 } [get_ports {fmc_qsfp_2_rx_p[2]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.M10 DP21_M2C_P +set_property -dict {LOC H1 } [get_ports {fmc_qsfp_2_rx_n[2]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.M11 DP21_M2C_N +set_property -dict {LOC G9 } [get_ports {fmc_qsfp_2_tx_p[0]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.Z4 DP22_C2M_P +set_property -dict {LOC G8 } [get_ports {fmc_qsfp_2_tx_n[0]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.Z5 DP22_C2M_N +set_property -dict {LOC G4 } [get_ports {fmc_qsfp_2_rx_p[0]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.M6 DP22_M2C_P +set_property -dict {LOC G3 } [get_ports {fmc_qsfp_2_rx_n[0]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.M7 DP22_M2C_N +set_property -dict {LOC F7 } [get_ports {fmc_qsfp_2_tx_p[1]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.Y2 DP23_C2M_P +set_property -dict {LOC F6 } [get_ports {fmc_qsfp_2_tx_n[1]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.Y3 DP23_C2M_N +set_property -dict {LOC F2 } [get_ports {fmc_qsfp_2_rx_p[1]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.M2 DP23_M2C_P +set_property -dict {LOC F1 } [get_ports {fmc_qsfp_2_rx_n[1]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.M3 DP23_M2C_N +set_property -dict {LOC H11 } [get_ports fmc_qsfp_2_mgt_refclk_p] ;# MGTREFCLK0P_232 from J9.Z20 GBTCLK5_M2C_P +set_property -dict {LOC H10 } [get_ports fmc_qsfp_2_mgt_refclk_n] ;# MGTREFCLK0N_232 from J9.Z21 GBTCLK5_M2C_N + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_2_mgt_refclk [get_ports fmc_qsfp_2_mgt_refclk_p] diff --git a/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu13p/Makefile b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu13p/Makefile new file mode 100644 index 0000000..7a92539 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu13p/Makefile @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcvu13p-fhgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga_6qsfp.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init_6qsfp.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += ../fmc_6qsfp.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl + +# Configuration +# CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu9p/Makefile b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu9p/Makefile new file mode 100644 index 0000000..dfd2e8e --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu9p/Makefile @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga_6qsfp.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init_6qsfp.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += ../fmc_6qsfp.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl + +# Configuration +# CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/eth/example/HTG9200/fpga/fpga_6q_vu13p/Makefile b/src/eth/example/HTG9200/fpga/fpga_6q_vu13p/Makefile new file mode 100644 index 0000000..5e6e5d8 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_6q_vu13p/Makefile @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcvu13p-fhgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga_6qsfp.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init_6qsfp.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += ../fmc_6qsfp.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl + +# Configuration +# CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/eth/example/HTG9200/fpga/fpga_6q_vu9p/Makefile b/src/eth/example/HTG9200/fpga/fpga_6q_vu9p/Makefile new file mode 100644 index 0000000..85bd9b7 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_6q_vu9p/Makefile @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga_6qsfp.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init_6qsfp.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += ../fmc_6qsfp.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl + +# Configuration +# CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/eth/example/HTG9200/fpga/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt b/src/eth/example/HTG9200/fpga/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt new file mode 100644 index 0000000..ac46ab6 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt @@ -0,0 +1,412 @@ +# Si534x/7x/8x/9x Registers Script +# +# Part: Si5341 +# Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_fmc_htg_6qsfp_25g\pll\HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj +# Design ID: HTG6Q161 +# Includes Pre/Post Download Control Register Writes: Yes +# Die Revision: B1 +# Creator: ClockBuilder Pro v4.1 [2021-09-22] +# Created On: 2023-07-19 01:56:52 GMT-07:00 +Address,Data +# +# Start configuration preamble +0x0B24,0xC0 +0x0B25,0x00 +# Rev D stuck divider fix +0x0502,0x01 +0x0505,0x03 +0x0957,0x17 +0x0B4E,0x1A +# End configuration preamble +# +# Delay 300 msec +# Delay is worst case time for device to complete any calibration +# that is running due to device state change previous to this script +# being processed. +# +# Start configuration registers +0x0006,0x00 +0x0007,0x00 +0x0008,0x00 +0x000B,0x74 +0x0017,0xD0 +0x0018,0xFF +0x0021,0x0D +0x0022,0x00 +0x002B,0x02 +0x002C,0x34 +0x002D,0x10 +0x002E,0x00 +0x002F,0x00 +0x0030,0x00 +0x0031,0x00 +0x0032,0xA8 +0x0033,0x00 +0x0034,0x00 +0x0035,0x00 +0x0036,0x00 +0x0037,0x00 +0x0038,0x00 +0x0039,0x00 +0x003A,0xA8 +0x003B,0x00 +0x003C,0x00 +0x003D,0x00 +0x0041,0x00 +0x0042,0x00 +0x0043,0x07 +0x0044,0x00 +0x009E,0x00 +0x0102,0x01 +0x0108,0x06 +0x0109,0x09 +0x010A,0x33 +0x010B,0x08 +0x010D,0x06 +0x010E,0x09 +0x010F,0x33 +0x0110,0x08 +0x0112,0x06 +0x0113,0x09 +0x0114,0x33 +0x0115,0x08 +0x0117,0x06 +0x0118,0x09 +0x0119,0x33 +0x011A,0x08 +0x011C,0x06 +0x011D,0x09 +0x011E,0x33 +0x011F,0x08 +0x0121,0x06 +0x0122,0x09 +0x0123,0x33 +0x0124,0x08 +0x0126,0x06 +0x0127,0x09 +0x0128,0x33 +0x0129,0x08 +0x012B,0x06 +0x012C,0x09 +0x012D,0x33 +0x012E,0x08 +0x0130,0x06 +0x0131,0x09 +0x0132,0x33 +0x0133,0x08 +0x013A,0x01 +0x013B,0x09 +0x013C,0x3B +0x013D,0x28 +0x013F,0x00 +0x0140,0x00 +0x0141,0x40 +0x0206,0x00 +0x0208,0x00 +0x0209,0x00 +0x020A,0x00 +0x020B,0x00 +0x020C,0x00 +0x020D,0x00 +0x020E,0x00 +0x020F,0x00 +0x0210,0x00 +0x0211,0x00 +0x0212,0x00 +0x0213,0x00 +0x0214,0x00 +0x0215,0x00 +0x0216,0x00 +0x0217,0x00 +0x0218,0x00 +0x0219,0x00 +0x021A,0x00 +0x021B,0x00 +0x021C,0x02 +0x021D,0x00 +0x021E,0x00 +0x021F,0x00 +0x0220,0x00 +0x0221,0x00 +0x0222,0x01 +0x0223,0x00 +0x0224,0x00 +0x0225,0x00 +0x0226,0x00 +0x0227,0x00 +0x0228,0x00 +0x0229,0x00 +0x022A,0x00 +0x022B,0x00 +0x022C,0x00 +0x022D,0x00 +0x022E,0x00 +0x022F,0x00 +0x0235,0x00 +0x0236,0x00 +0x0237,0x00 +0x0238,0x00 +0x0239,0x52 +0x023A,0x00 +0x023B,0x00 +0x023C,0x00 +0x023D,0x00 +0x023E,0x80 +0x024A,0x00 +0x024B,0x00 +0x024C,0x00 +0x024D,0x00 +0x024E,0x00 +0x024F,0x00 +0x0250,0x00 +0x0251,0x00 +0x0252,0x00 +0x0253,0x00 +0x0254,0x00 +0x0255,0x00 +0x0256,0x00 +0x0257,0x00 +0x0258,0x00 +0x0259,0x00 +0x025A,0x00 +0x025B,0x00 +0x025C,0x00 +0x025D,0x00 +0x025E,0x00 +0x025F,0x00 +0x0260,0x00 +0x0261,0x00 +0x0262,0x00 +0x0263,0x00 +0x0264,0x00 +0x0268,0x00 +0x0269,0x00 +0x026A,0x00 +0x026B,0x48 +0x026C,0x54 +0x026D,0x47 +0x026E,0x36 +0x026F,0x51 +0x0270,0x31 +0x0271,0x36 +0x0272,0x31 +0x0302,0x00 +0x0303,0x00 +0x0304,0x00 +0x0305,0x80 +0x0306,0x14 +0x0307,0x00 +0x0308,0x00 +0x0309,0x00 +0x030A,0x00 +0x030B,0x80 +0x030C,0x00 +0x030D,0x00 +0x030E,0x00 +0x030F,0x00 +0x0310,0x00 +0x0311,0x00 +0x0312,0x00 +0x0313,0x00 +0x0314,0x00 +0x0315,0x00 +0x0316,0x00 +0x0317,0x00 +0x0318,0x00 +0x0319,0x00 +0x031A,0x00 +0x031B,0x00 +0x031C,0x00 +0x031D,0x00 +0x031E,0x00 +0x031F,0x00 +0x0320,0x00 +0x0321,0x00 +0x0322,0x00 +0x0323,0x00 +0x0324,0x00 +0x0325,0x00 +0x0326,0x00 +0x0327,0x00 +0x0328,0x00 +0x0329,0x00 +0x032A,0x00 +0x032B,0x00 +0x032C,0x00 +0x032D,0x00 +0x032E,0x00 +0x032F,0x00 +0x0330,0x00 +0x0331,0x00 +0x0332,0x00 +0x0333,0x00 +0x0334,0x00 +0x0335,0x00 +0x0336,0x00 +0x0337,0x00 +0x0338,0x00 +0x0339,0x1F +0x033B,0x00 +0x033C,0x00 +0x033D,0x00 +0x033E,0x00 +0x033F,0x00 +0x0340,0x00 +0x0341,0x00 +0x0342,0x00 +0x0343,0x00 +0x0344,0x00 +0x0345,0x00 +0x0346,0x00 +0x0347,0x00 +0x0348,0x00 +0x0349,0x00 +0x034A,0x00 +0x034B,0x00 +0x034C,0x00 +0x034D,0x00 +0x034E,0x00 +0x034F,0x00 +0x0350,0x00 +0x0351,0x00 +0x0352,0x00 +0x0353,0x00 +0x0354,0x00 +0x0355,0x00 +0x0356,0x00 +0x0357,0x00 +0x0358,0x00 +0x0359,0x00 +0x035A,0x00 +0x035B,0x00 +0x035C,0x00 +0x035D,0x00 +0x035E,0x00 +0x035F,0x00 +0x0360,0x00 +0x0361,0x00 +0x0362,0x00 +0x0802,0x00 +0x0803,0x00 +0x0804,0x00 +0x0805,0x00 +0x0806,0x00 +0x0807,0x00 +0x0808,0x00 +0x0809,0x00 +0x080A,0x00 +0x080B,0x00 +0x080C,0x00 +0x080D,0x00 +0x080E,0x00 +0x080F,0x00 +0x0810,0x00 +0x0811,0x00 +0x0812,0x00 +0x0813,0x00 +0x0814,0x00 +0x0815,0x00 +0x0816,0x00 +0x0817,0x00 +0x0818,0x00 +0x0819,0x00 +0x081A,0x00 +0x081B,0x00 +0x081C,0x00 +0x081D,0x00 +0x081E,0x00 +0x081F,0x00 +0x0820,0x00 +0x0821,0x00 +0x0822,0x00 +0x0823,0x00 +0x0824,0x00 +0x0825,0x00 +0x0826,0x00 +0x0827,0x00 +0x0828,0x00 +0x0829,0x00 +0x082A,0x00 +0x082B,0x00 +0x082C,0x00 +0x082D,0x00 +0x082E,0x00 +0x082F,0x00 +0x0830,0x00 +0x0831,0x00 +0x0832,0x00 +0x0833,0x00 +0x0834,0x00 +0x0835,0x00 +0x0836,0x00 +0x0837,0x00 +0x0838,0x00 +0x0839,0x00 +0x083A,0x00 +0x083B,0x00 +0x083C,0x00 +0x083D,0x00 +0x083E,0x00 +0x083F,0x00 +0x0840,0x00 +0x0841,0x00 +0x0842,0x00 +0x0843,0x00 +0x0844,0x00 +0x0845,0x00 +0x0846,0x00 +0x0847,0x00 +0x0848,0x00 +0x0849,0x00 +0x084A,0x00 +0x084B,0x00 +0x084C,0x00 +0x084D,0x00 +0x084E,0x00 +0x084F,0x00 +0x0850,0x00 +0x0851,0x00 +0x0852,0x00 +0x0853,0x00 +0x0854,0x00 +0x0855,0x00 +0x0856,0x00 +0x0857,0x00 +0x0858,0x00 +0x0859,0x00 +0x085A,0x00 +0x085B,0x00 +0x085C,0x00 +0x085D,0x00 +0x085E,0x00 +0x085F,0x00 +0x0860,0x00 +0x0861,0x00 +0x090E,0x00 +0x091C,0x04 +0x0943,0x00 +0x0949,0x04 +0x094A,0x40 +0x094E,0x49 +0x094F,0x02 +0x095E,0x00 +0x0A02,0x00 +0x0A03,0x01 +0x0A04,0x01 +0x0A05,0x01 +0x0A14,0x00 +0x0A1A,0x00 +0x0A20,0x00 +0x0A26,0x00 +0x0A2C,0x00 +0x0B44,0x0F +0x0B4A,0x1E +0x0B57,0xA0 +0x0B58,0x00 +# End configuration registers +# +# Start configuration postamble +0x001C,0x01 +0x0B24,0xC3 +0x0B25,0x02 +# End configuration postamble diff --git a/src/eth/example/HTG9200/fpga/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj b/src/eth/example/HTG9200/fpga/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj new file mode 100644 index 0000000..3af140b Binary files /dev/null and b/src/eth/example/HTG9200/fpga/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj differ diff --git a/src/eth/example/HTG9200/fpga/pll/si5341_i2c_init.py b/src/eth/example/HTG9200/fpga/pll/si5341_i2c_init.py index 2a1aa96..0ec7715 100755 --- a/src/eth/example/HTG9200/fpga/pll/si5341_i2c_init.py +++ b/src/eth/example/HTG9200/fpga/pll/si5341_i2c_init.py @@ -71,7 +71,17 @@ def main(): cmds.extend(mux_cmds(0x04, 0x71)) cmds.extend(si5341_cmds("HTG9200_161-9k2_161-Registers.txt", 0x77)) - generate(cmds) + + generate(cmds, output="si5341_i2c_init.sv") + + # Si5341 on FMC+ + cmds.append("// Set muxes to select U7 Si5341 on HTG-FMC-x6-QSFP28") + cmds.extend(mux_cmds(0x00, 0x70)) + cmds.extend(mux_cmds(0x02, 0x71)) + + cmds.extend(si5341_cmds("HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt", 0x77)) + + generate(cmds, output="si5341_i2c_init_6qsfp.sv") def generate(cmds=None, name=None, output=None): @@ -86,6 +96,7 @@ def generate(cmds=None, name=None, output=None): print(f"Generating Si5341 I2C init module {name}...") + cmds = cmds.copy() cmds.append("cmd_halt(); // end") cmd_str = "" diff --git a/src/eth/example/HTG9200/fpga/pll/si5341_i2c_init_6qsfp.sv b/src/eth/example/HTG9200/fpga/pll/si5341_i2c_init_6qsfp.sv new file mode 100644 index 0000000..e9fe658 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/pll/si5341_i2c_init_6qsfp.sv @@ -0,0 +1,1647 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2015-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * si5341_i2c_init + */ +module si5341_i2c_init # +( + parameter logic SIM_SPEEDUP = 1'b0 +) +( + input wire logic clk, + input wire logic rst, + + /* + * I2C master interface + */ + taxi_axis_if.src m_axis_cmd, + taxi_axis_if.src m_axis_tx, + + /* + * Status + */ + output wire logic busy, + + /* + * Configuration + */ + input wire logic start +); + +/* + +Generic module for I2C bus initialization. Good for use when multiple devices +on an I2C bus must be initialized on system start without intervention of a +general-purpose processor. + +Copy this file and change init_data and INIT_DATA_LEN as needed. + +This module can be used in two modes: simple device initialization, or multiple +device initialization. In multiple device mode, the same initialization sequence +can be performed on multiple different device addresses. + +To use single device mode, only use the start write to address and write data commands. +The module will generate the I2C commands in sequential order. Terminate the list +with a 0 entry. + +To use the multiple device mode, use the start data and start address block commands +to set up lists of initialization data and device addresses. The module enters +multiple device mode upon seeing a start data block command. The module stores the +offset of the start of the data block and then skips ahead until it reaches a start +address block command. The module will store the offset to the address block and +read the first address in the block. Then it will jump back to the data block +and execute it, substituting the stored address for each current address write +command. Upon reaching the start address block command, the module will read out the +next address and start again at the top of the data block. If the module encounters +a start data block command while looking for an address, then it will store a new data +offset and then look for a start address block command. Terminate the list with a 0 +entry. Normal address commands will operate normally inside a data block. + +Commands: + +00 0000000 : stop +00 0000001 : exit multiple device mode +00 0000011 : start write to current address +00 0001000 : start address block +00 0001001 : start data block +00 001dddd : delay 2**(16+d) cycles +00 1000001 : send I2C stop +01 aaaaaaa : start write to address +1 dddddddd : write 8-bit data + +Examples + +write 0x11223344 to register 0x0004 on device at 0x50 + +01 1010000 start write to 0x50 +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +0 00000000 stop + +write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53 + +00 0001001 start data block +00 0000011 start write to current address +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +00 0001000 start address block +01 1010000 address 0x50 +01 1010001 address 0x51 +01 1010010 address 0x52 +01 1010011 address 0x53 +00 0000001 exit multi-dev mode +00 0000000 stop + +*/ + +// check configuration +if (m_axis_cmd.DATA_W < 12) + $fatal(0, "Command interface width must be at least 12 bits (instance %m)"); + +if (m_axis_tx.DATA_W != 8) + $fatal(0, "Data interface width must be 8 bits (instance %m)"); + +function [8:0] cmd_start(input [6:0] addr); + cmd_start = {2'b01, addr}; +endfunction + +function [8:0] cmd_wr(input [7:0] data); + cmd_wr = {1'b1, data}; +endfunction + +function [8:0] cmd_stop(); + cmd_stop = {2'b00, 7'b1000001}; +endfunction + +function [8:0] cmd_delay(input [3:0] d); + cmd_delay = {2'b00, 3'b001, d}; +endfunction + +function [8:0] cmd_halt(); + cmd_halt = 9'd0; +endfunction + +function [8:0] blk_start_data(); + blk_start_data = {2'b00, 7'b0001001}; +endfunction + +function [8:0] blk_start_addr(); + blk_start_addr = {2'b00, 7'b0001000}; +endfunction + +function [8:0] cmd_start_cur(); + cmd_start_cur = {2'b00, 7'b0000011}; +endfunction + +function [8:0] cmd_exit(); + cmd_exit = {2'b00, 7'b0000001}; +endfunction + +// init_data ROM +localparam INIT_DATA_LEN = 1070; + +reg [8:0] init_data [INIT_DATA_LEN-1:0]; + +initial begin + // Initial delay + init_data[0] = cmd_delay(6); // delay 30 ms + // Set muxes to select U48 Si5341 on HTG-9200 + init_data[1] = cmd_start(7'h70); + init_data[2] = cmd_wr(8'h00); + init_data[3] = cmd_stop(); // I2C stop + init_data[4] = cmd_start(7'h71); + init_data[5] = cmd_wr(8'h04); + init_data[6] = cmd_stop(); // I2C stop + // Si534x/7x/8x/9x Registers Script + // + // Part: Si5341 + // Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_25g\pll\HTG9200_161-9k2_161.slabtimeproj + // Design ID: 9k2_161 + // Includes Pre/Post Download Control Register Writes: Yes + // Die Revision: B1 + // Creator: ClockBuilder Pro v4.1 [2021-09-22] + // Created On: 2023-07-19 01:51:06 GMT-07:00 + // + // Start configuration preamble + init_data[7] = cmd_start(7'h77); + init_data[8] = cmd_wr(8'h01); + init_data[9] = cmd_wr(8'h0b); // set page 0x0b + init_data[10] = cmd_start(7'h77); + init_data[11] = cmd_wr(8'h24); + init_data[12] = cmd_wr(8'hc0); // write 0xc0 to 0x0b24 + init_data[13] = cmd_wr(8'h00); // write 0x00 to 0x0b25 + // Rev D stuck divider fix + init_data[14] = cmd_start(7'h77); + init_data[15] = cmd_wr(8'h01); + init_data[16] = cmd_wr(8'h05); // set page 0x05 + init_data[17] = cmd_start(7'h77); + init_data[18] = cmd_wr(8'h02); + init_data[19] = cmd_wr(8'h01); // write 0x01 to 0x0502 + init_data[20] = cmd_start(7'h77); + init_data[21] = cmd_wr(8'h05); + init_data[22] = cmd_wr(8'h03); // write 0x03 to 0x0505 + init_data[23] = cmd_start(7'h77); + init_data[24] = cmd_wr(8'h01); + init_data[25] = cmd_wr(8'h09); // set page 0x09 + init_data[26] = cmd_start(7'h77); + init_data[27] = cmd_wr(8'h57); + init_data[28] = cmd_wr(8'h17); // write 0x17 to 0x0957 + init_data[29] = cmd_start(7'h77); + init_data[30] = cmd_wr(8'h01); + init_data[31] = cmd_wr(8'h0b); // set page 0x0b + init_data[32] = cmd_start(7'h77); + init_data[33] = cmd_wr(8'h4e); + init_data[34] = cmd_wr(8'h1a); // write 0x1a to 0x0b4e + // End configuration preamble + // + // Delay 300 msec + init_data[35] = cmd_delay(10); // delay 300 ms + // Delay is worst case time for device to complete any calibration + // that is running due to device state change previous to this script + // being processed. + // + // Start configuration registers + init_data[36] = cmd_start(7'h77); + init_data[37] = cmd_wr(8'h01); + init_data[38] = cmd_wr(8'h00); // set page 0x00 + init_data[39] = cmd_start(7'h77); + init_data[40] = cmd_wr(8'h06); + init_data[41] = cmd_wr(8'h00); // write 0x00 to 0x0006 + init_data[42] = cmd_wr(8'h00); // write 0x00 to 0x0007 + init_data[43] = cmd_wr(8'h00); // write 0x00 to 0x0008 + init_data[44] = cmd_start(7'h77); + init_data[45] = cmd_wr(8'h0b); + init_data[46] = cmd_wr(8'h74); // write 0x74 to 0x000b + init_data[47] = cmd_start(7'h77); + init_data[48] = cmd_wr(8'h17); + init_data[49] = cmd_wr(8'hd0); // write 0xd0 to 0x0017 + init_data[50] = cmd_wr(8'hff); // write 0xff to 0x0018 + init_data[51] = cmd_start(7'h77); + init_data[52] = cmd_wr(8'h21); + init_data[53] = cmd_wr(8'h0b); // write 0x0b to 0x0021 + init_data[54] = cmd_wr(8'h00); // write 0x00 to 0x0022 + init_data[55] = cmd_start(7'h77); + init_data[56] = cmd_wr(8'h2b); + init_data[57] = cmd_wr(8'h02); // write 0x02 to 0x002b + init_data[58] = cmd_wr(8'h33); // write 0x33 to 0x002c + init_data[59] = cmd_wr(8'h05); // write 0x05 to 0x002d + init_data[60] = cmd_wr(8'hae); // write 0xae to 0x002e + init_data[61] = cmd_wr(8'h00); // write 0x00 to 0x002f + init_data[62] = cmd_wr(8'hae); // write 0xae to 0x0030 + init_data[63] = cmd_wr(8'h00); // write 0x00 to 0x0031 + init_data[64] = cmd_wr(8'h00); // write 0x00 to 0x0032 + init_data[65] = cmd_wr(8'h00); // write 0x00 to 0x0033 + init_data[66] = cmd_wr(8'h00); // write 0x00 to 0x0034 + init_data[67] = cmd_wr(8'h00); // write 0x00 to 0x0035 + init_data[68] = cmd_wr(8'hae); // write 0xae to 0x0036 + init_data[69] = cmd_wr(8'h00); // write 0x00 to 0x0037 + init_data[70] = cmd_wr(8'hae); // write 0xae to 0x0038 + init_data[71] = cmd_wr(8'h00); // write 0x00 to 0x0039 + init_data[72] = cmd_wr(8'h00); // write 0x00 to 0x003a + init_data[73] = cmd_wr(8'h00); // write 0x00 to 0x003b + init_data[74] = cmd_wr(8'h00); // write 0x00 to 0x003c + init_data[75] = cmd_wr(8'h00); // write 0x00 to 0x003d + init_data[76] = cmd_start(7'h77); + init_data[77] = cmd_wr(8'h41); + init_data[78] = cmd_wr(8'h07); // write 0x07 to 0x0041 + init_data[79] = cmd_wr(8'h07); // write 0x07 to 0x0042 + init_data[80] = cmd_wr(8'h00); // write 0x00 to 0x0043 + init_data[81] = cmd_wr(8'h00); // write 0x00 to 0x0044 + init_data[82] = cmd_start(7'h77); + init_data[83] = cmd_wr(8'h9e); + init_data[84] = cmd_wr(8'h00); // write 0x00 to 0x009e + init_data[85] = cmd_start(7'h77); + init_data[86] = cmd_wr(8'h01); + init_data[87] = cmd_wr(8'h01); // set page 0x01 + init_data[88] = cmd_start(7'h77); + init_data[89] = cmd_wr(8'h02); + init_data[90] = cmd_wr(8'h01); // write 0x01 to 0x0102 + init_data[91] = cmd_start(7'h77); + init_data[92] = cmd_wr(8'h08); + init_data[93] = cmd_wr(8'h06); // write 0x06 to 0x0108 + init_data[94] = cmd_wr(8'h09); // write 0x09 to 0x0109 + init_data[95] = cmd_wr(8'h3b); // write 0x3b to 0x010a + init_data[96] = cmd_wr(8'h28); // write 0x28 to 0x010b + init_data[97] = cmd_start(7'h77); + init_data[98] = cmd_wr(8'h0d); + init_data[99] = cmd_wr(8'h06); // write 0x06 to 0x010d + init_data[100] = cmd_wr(8'h09); // write 0x09 to 0x010e + init_data[101] = cmd_wr(8'h3b); // write 0x3b to 0x010f + init_data[102] = cmd_wr(8'h28); // write 0x28 to 0x0110 + init_data[103] = cmd_start(7'h77); + init_data[104] = cmd_wr(8'h12); + init_data[105] = cmd_wr(8'h02); // write 0x02 to 0x0112 + init_data[106] = cmd_wr(8'h09); // write 0x09 to 0x0113 + init_data[107] = cmd_wr(8'h3b); // write 0x3b to 0x0114 + init_data[108] = cmd_wr(8'h29); // write 0x29 to 0x0115 + init_data[109] = cmd_start(7'h77); + init_data[110] = cmd_wr(8'h17); + init_data[111] = cmd_wr(8'h06); // write 0x06 to 0x0117 + init_data[112] = cmd_wr(8'h09); // write 0x09 to 0x0118 + init_data[113] = cmd_wr(8'h3b); // write 0x3b to 0x0119 + init_data[114] = cmd_wr(8'h28); // write 0x28 to 0x011a + init_data[115] = cmd_start(7'h77); + init_data[116] = cmd_wr(8'h1c); + init_data[117] = cmd_wr(8'h06); // write 0x06 to 0x011c + init_data[118] = cmd_wr(8'h09); // write 0x09 to 0x011d + init_data[119] = cmd_wr(8'h3b); // write 0x3b to 0x011e + init_data[120] = cmd_wr(8'h28); // write 0x28 to 0x011f + init_data[121] = cmd_start(7'h77); + init_data[122] = cmd_wr(8'h21); + init_data[123] = cmd_wr(8'h06); // write 0x06 to 0x0121 + init_data[124] = cmd_wr(8'h09); // write 0x09 to 0x0122 + init_data[125] = cmd_wr(8'h3b); // write 0x3b to 0x0123 + init_data[126] = cmd_wr(8'h28); // write 0x28 to 0x0124 + init_data[127] = cmd_start(7'h77); + init_data[128] = cmd_wr(8'h26); + init_data[129] = cmd_wr(8'h06); // write 0x06 to 0x0126 + init_data[130] = cmd_wr(8'h09); // write 0x09 to 0x0127 + init_data[131] = cmd_wr(8'h3b); // write 0x3b to 0x0128 + init_data[132] = cmd_wr(8'h28); // write 0x28 to 0x0129 + init_data[133] = cmd_start(7'h77); + init_data[134] = cmd_wr(8'h2b); + init_data[135] = cmd_wr(8'h06); // write 0x06 to 0x012b + init_data[136] = cmd_wr(8'h09); // write 0x09 to 0x012c + init_data[137] = cmd_wr(8'h3b); // write 0x3b to 0x012d + init_data[138] = cmd_wr(8'h28); // write 0x28 to 0x012e + init_data[139] = cmd_start(7'h77); + init_data[140] = cmd_wr(8'h30); + init_data[141] = cmd_wr(8'h06); // write 0x06 to 0x0130 + init_data[142] = cmd_wr(8'h09); // write 0x09 to 0x0131 + init_data[143] = cmd_wr(8'h3b); // write 0x3b to 0x0132 + init_data[144] = cmd_wr(8'h28); // write 0x28 to 0x0133 + init_data[145] = cmd_start(7'h77); + init_data[146] = cmd_wr(8'h3a); + init_data[147] = cmd_wr(8'h06); // write 0x06 to 0x013a + init_data[148] = cmd_wr(8'h09); // write 0x09 to 0x013b + init_data[149] = cmd_wr(8'h3b); // write 0x3b to 0x013c + init_data[150] = cmd_wr(8'h28); // write 0x28 to 0x013d + init_data[151] = cmd_start(7'h77); + init_data[152] = cmd_wr(8'h3f); + init_data[153] = cmd_wr(8'h00); // write 0x00 to 0x013f + init_data[154] = cmd_wr(8'h00); // write 0x00 to 0x0140 + init_data[155] = cmd_wr(8'h40); // write 0x40 to 0x0141 + init_data[156] = cmd_start(7'h77); + init_data[157] = cmd_wr(8'h01); + init_data[158] = cmd_wr(8'h02); // set page 0x02 + init_data[159] = cmd_start(7'h77); + init_data[160] = cmd_wr(8'h06); + init_data[161] = cmd_wr(8'h00); // write 0x00 to 0x0206 + init_data[162] = cmd_start(7'h77); + init_data[163] = cmd_wr(8'h08); + init_data[164] = cmd_wr(8'h02); // write 0x02 to 0x0208 + init_data[165] = cmd_wr(8'h00); // write 0x00 to 0x0209 + init_data[166] = cmd_wr(8'h00); // write 0x00 to 0x020a + init_data[167] = cmd_wr(8'h00); // write 0x00 to 0x020b + init_data[168] = cmd_wr(8'h00); // write 0x00 to 0x020c + init_data[169] = cmd_wr(8'h00); // write 0x00 to 0x020d + init_data[170] = cmd_wr(8'h01); // write 0x01 to 0x020e + init_data[171] = cmd_wr(8'h00); // write 0x00 to 0x020f + init_data[172] = cmd_wr(8'h00); // write 0x00 to 0x0210 + init_data[173] = cmd_wr(8'h00); // write 0x00 to 0x0211 + init_data[174] = cmd_wr(8'h02); // write 0x02 to 0x0212 + init_data[175] = cmd_wr(8'h00); // write 0x00 to 0x0213 + init_data[176] = cmd_wr(8'h00); // write 0x00 to 0x0214 + init_data[177] = cmd_wr(8'h00); // write 0x00 to 0x0215 + init_data[178] = cmd_wr(8'h00); // write 0x00 to 0x0216 + init_data[179] = cmd_wr(8'h00); // write 0x00 to 0x0217 + init_data[180] = cmd_wr(8'h01); // write 0x01 to 0x0218 + init_data[181] = cmd_wr(8'h00); // write 0x00 to 0x0219 + init_data[182] = cmd_wr(8'h00); // write 0x00 to 0x021a + init_data[183] = cmd_wr(8'h00); // write 0x00 to 0x021b + init_data[184] = cmd_wr(8'h00); // write 0x00 to 0x021c + init_data[185] = cmd_wr(8'h00); // write 0x00 to 0x021d + init_data[186] = cmd_wr(8'h00); // write 0x00 to 0x021e + init_data[187] = cmd_wr(8'h00); // write 0x00 to 0x021f + init_data[188] = cmd_wr(8'h00); // write 0x00 to 0x0220 + init_data[189] = cmd_wr(8'h00); // write 0x00 to 0x0221 + init_data[190] = cmd_wr(8'h00); // write 0x00 to 0x0222 + init_data[191] = cmd_wr(8'h00); // write 0x00 to 0x0223 + init_data[192] = cmd_wr(8'h00); // write 0x00 to 0x0224 + init_data[193] = cmd_wr(8'h00); // write 0x00 to 0x0225 + init_data[194] = cmd_wr(8'h00); // write 0x00 to 0x0226 + init_data[195] = cmd_wr(8'h00); // write 0x00 to 0x0227 + init_data[196] = cmd_wr(8'h00); // write 0x00 to 0x0228 + init_data[197] = cmd_wr(8'h00); // write 0x00 to 0x0229 + init_data[198] = cmd_wr(8'h00); // write 0x00 to 0x022a + init_data[199] = cmd_wr(8'h00); // write 0x00 to 0x022b + init_data[200] = cmd_wr(8'h00); // write 0x00 to 0x022c + init_data[201] = cmd_wr(8'h00); // write 0x00 to 0x022d + init_data[202] = cmd_wr(8'h00); // write 0x00 to 0x022e + init_data[203] = cmd_wr(8'h00); // write 0x00 to 0x022f + init_data[204] = cmd_start(7'h77); + init_data[205] = cmd_wr(8'h35); + init_data[206] = cmd_wr(8'h00); // write 0x00 to 0x0235 + init_data[207] = cmd_wr(8'h00); // write 0x00 to 0x0236 + init_data[208] = cmd_wr(8'h00); // write 0x00 to 0x0237 + init_data[209] = cmd_wr(8'h90); // write 0x90 to 0x0238 + init_data[210] = cmd_wr(8'h54); // write 0x54 to 0x0239 + init_data[211] = cmd_wr(8'h00); // write 0x00 to 0x023a + init_data[212] = cmd_wr(8'h00); // write 0x00 to 0x023b + init_data[213] = cmd_wr(8'h00); // write 0x00 to 0x023c + init_data[214] = cmd_wr(8'h00); // write 0x00 to 0x023d + init_data[215] = cmd_wr(8'h80); // write 0x80 to 0x023e + init_data[216] = cmd_start(7'h77); + init_data[217] = cmd_wr(8'h4a); + init_data[218] = cmd_wr(8'h00); // write 0x00 to 0x024a + init_data[219] = cmd_wr(8'h00); // write 0x00 to 0x024b + init_data[220] = cmd_wr(8'h00); // write 0x00 to 0x024c + init_data[221] = cmd_wr(8'h00); // write 0x00 to 0x024d + init_data[222] = cmd_wr(8'h00); // write 0x00 to 0x024e + init_data[223] = cmd_wr(8'h00); // write 0x00 to 0x024f + init_data[224] = cmd_wr(8'h03); // write 0x03 to 0x0250 + init_data[225] = cmd_wr(8'h00); // write 0x00 to 0x0251 + init_data[226] = cmd_wr(8'h00); // write 0x00 to 0x0252 + init_data[227] = cmd_wr(8'h00); // write 0x00 to 0x0253 + init_data[228] = cmd_wr(8'h00); // write 0x00 to 0x0254 + init_data[229] = cmd_wr(8'h00); // write 0x00 to 0x0255 + init_data[230] = cmd_wr(8'h00); // write 0x00 to 0x0256 + init_data[231] = cmd_wr(8'h00); // write 0x00 to 0x0257 + init_data[232] = cmd_wr(8'h00); // write 0x00 to 0x0258 + init_data[233] = cmd_wr(8'h00); // write 0x00 to 0x0259 + init_data[234] = cmd_wr(8'h00); // write 0x00 to 0x025a + init_data[235] = cmd_wr(8'h00); // write 0x00 to 0x025b + init_data[236] = cmd_wr(8'h00); // write 0x00 to 0x025c + init_data[237] = cmd_wr(8'h00); // write 0x00 to 0x025d + init_data[238] = cmd_wr(8'h00); // write 0x00 to 0x025e + init_data[239] = cmd_wr(8'h00); // write 0x00 to 0x025f + init_data[240] = cmd_wr(8'h00); // write 0x00 to 0x0260 + init_data[241] = cmd_wr(8'h00); // write 0x00 to 0x0261 + init_data[242] = cmd_wr(8'h00); // write 0x00 to 0x0262 + init_data[243] = cmd_wr(8'h00); // write 0x00 to 0x0263 + init_data[244] = cmd_wr(8'h00); // write 0x00 to 0x0264 + init_data[245] = cmd_start(7'h77); + init_data[246] = cmd_wr(8'h68); + init_data[247] = cmd_wr(8'h00); // write 0x00 to 0x0268 + init_data[248] = cmd_wr(8'h00); // write 0x00 to 0x0269 + init_data[249] = cmd_wr(8'h00); // write 0x00 to 0x026a + init_data[250] = cmd_wr(8'h39); // write 0x39 to 0x026b + init_data[251] = cmd_wr(8'h6b); // write 0x6b to 0x026c + init_data[252] = cmd_wr(8'h32); // write 0x32 to 0x026d + init_data[253] = cmd_wr(8'h5f); // write 0x5f to 0x026e + init_data[254] = cmd_wr(8'h31); // write 0x31 to 0x026f + init_data[255] = cmd_wr(8'h36); // write 0x36 to 0x0270 + init_data[256] = cmd_wr(8'h31); // write 0x31 to 0x0271 + init_data[257] = cmd_wr(8'h00); // write 0x00 to 0x0272 + init_data[258] = cmd_start(7'h77); + init_data[259] = cmd_wr(8'h01); + init_data[260] = cmd_wr(8'h03); // set page 0x03 + init_data[261] = cmd_start(7'h77); + init_data[262] = cmd_wr(8'h02); + init_data[263] = cmd_wr(8'h00); // write 0x00 to 0x0302 + init_data[264] = cmd_wr(8'h00); // write 0x00 to 0x0303 + init_data[265] = cmd_wr(8'h00); // write 0x00 to 0x0304 + init_data[266] = cmd_wr(8'h80); // write 0x80 to 0x0305 + init_data[267] = cmd_wr(8'h14); // write 0x14 to 0x0306 + init_data[268] = cmd_wr(8'h00); // write 0x00 to 0x0307 + init_data[269] = cmd_wr(8'h00); // write 0x00 to 0x0308 + init_data[270] = cmd_wr(8'h00); // write 0x00 to 0x0309 + init_data[271] = cmd_wr(8'h00); // write 0x00 to 0x030a + init_data[272] = cmd_wr(8'h80); // write 0x80 to 0x030b + init_data[273] = cmd_wr(8'h00); // write 0x00 to 0x030c + init_data[274] = cmd_wr(8'h00); // write 0x00 to 0x030d + init_data[275] = cmd_wr(8'h00); // write 0x00 to 0x030e + init_data[276] = cmd_wr(8'h10); // write 0x10 to 0x030f + init_data[277] = cmd_wr(8'h42); // write 0x42 to 0x0310 + init_data[278] = cmd_wr(8'h08); // write 0x08 to 0x0311 + init_data[279] = cmd_wr(8'h00); // write 0x00 to 0x0312 + init_data[280] = cmd_wr(8'h00); // write 0x00 to 0x0313 + init_data[281] = cmd_wr(8'h00); // write 0x00 to 0x0314 + init_data[282] = cmd_wr(8'h00); // write 0x00 to 0x0315 + init_data[283] = cmd_wr(8'h80); // write 0x80 to 0x0316 + init_data[284] = cmd_wr(8'h00); // write 0x00 to 0x0317 + init_data[285] = cmd_wr(8'h00); // write 0x00 to 0x0318 + init_data[286] = cmd_wr(8'h00); // write 0x00 to 0x0319 + init_data[287] = cmd_wr(8'h00); // write 0x00 to 0x031a + init_data[288] = cmd_wr(8'h00); // write 0x00 to 0x031b + init_data[289] = cmd_wr(8'h00); // write 0x00 to 0x031c + init_data[290] = cmd_wr(8'h00); // write 0x00 to 0x031d + init_data[291] = cmd_wr(8'h00); // write 0x00 to 0x031e + init_data[292] = cmd_wr(8'h00); // write 0x00 to 0x031f + init_data[293] = cmd_wr(8'h00); // write 0x00 to 0x0320 + init_data[294] = cmd_wr(8'h00); // write 0x00 to 0x0321 + init_data[295] = cmd_wr(8'h00); // write 0x00 to 0x0322 + init_data[296] = cmd_wr(8'h00); // write 0x00 to 0x0323 + init_data[297] = cmd_wr(8'h00); // write 0x00 to 0x0324 + init_data[298] = cmd_wr(8'h00); // write 0x00 to 0x0325 + init_data[299] = cmd_wr(8'h00); // write 0x00 to 0x0326 + init_data[300] = cmd_wr(8'h00); // write 0x00 to 0x0327 + init_data[301] = cmd_wr(8'h00); // write 0x00 to 0x0328 + init_data[302] = cmd_wr(8'h00); // write 0x00 to 0x0329 + init_data[303] = cmd_wr(8'h00); // write 0x00 to 0x032a + init_data[304] = cmd_wr(8'h00); // write 0x00 to 0x032b + init_data[305] = cmd_wr(8'h00); // write 0x00 to 0x032c + init_data[306] = cmd_wr(8'h00); // write 0x00 to 0x032d + init_data[307] = cmd_wr(8'h00); // write 0x00 to 0x032e + init_data[308] = cmd_wr(8'h00); // write 0x00 to 0x032f + init_data[309] = cmd_wr(8'h00); // write 0x00 to 0x0330 + init_data[310] = cmd_wr(8'h00); // write 0x00 to 0x0331 + init_data[311] = cmd_wr(8'h00); // write 0x00 to 0x0332 + init_data[312] = cmd_wr(8'h00); // write 0x00 to 0x0333 + init_data[313] = cmd_wr(8'h00); // write 0x00 to 0x0334 + init_data[314] = cmd_wr(8'h00); // write 0x00 to 0x0335 + init_data[315] = cmd_wr(8'h00); // write 0x00 to 0x0336 + init_data[316] = cmd_wr(8'h00); // write 0x00 to 0x0337 + init_data[317] = cmd_wr(8'h00); // write 0x00 to 0x0338 + init_data[318] = cmd_wr(8'h1f); // write 0x1f to 0x0339 + init_data[319] = cmd_start(7'h77); + init_data[320] = cmd_wr(8'h3b); + init_data[321] = cmd_wr(8'h00); // write 0x00 to 0x033b + init_data[322] = cmd_wr(8'h00); // write 0x00 to 0x033c + init_data[323] = cmd_wr(8'h00); // write 0x00 to 0x033d + init_data[324] = cmd_wr(8'h00); // write 0x00 to 0x033e + init_data[325] = cmd_wr(8'h00); // write 0x00 to 0x033f + init_data[326] = cmd_wr(8'h00); // write 0x00 to 0x0340 + init_data[327] = cmd_wr(8'h00); // write 0x00 to 0x0341 + init_data[328] = cmd_wr(8'h00); // write 0x00 to 0x0342 + init_data[329] = cmd_wr(8'h00); // write 0x00 to 0x0343 + init_data[330] = cmd_wr(8'h00); // write 0x00 to 0x0344 + init_data[331] = cmd_wr(8'h00); // write 0x00 to 0x0345 + init_data[332] = cmd_wr(8'h00); // write 0x00 to 0x0346 + init_data[333] = cmd_wr(8'h00); // write 0x00 to 0x0347 + init_data[334] = cmd_wr(8'h00); // write 0x00 to 0x0348 + init_data[335] = cmd_wr(8'h00); // write 0x00 to 0x0349 + init_data[336] = cmd_wr(8'h00); // write 0x00 to 0x034a + init_data[337] = cmd_wr(8'h00); // write 0x00 to 0x034b + init_data[338] = cmd_wr(8'h00); // write 0x00 to 0x034c + init_data[339] = cmd_wr(8'h00); // write 0x00 to 0x034d + init_data[340] = cmd_wr(8'h00); // write 0x00 to 0x034e + init_data[341] = cmd_wr(8'h00); // write 0x00 to 0x034f + init_data[342] = cmd_wr(8'h00); // write 0x00 to 0x0350 + init_data[343] = cmd_wr(8'h00); // write 0x00 to 0x0351 + init_data[344] = cmd_wr(8'h00); // write 0x00 to 0x0352 + init_data[345] = cmd_wr(8'h00); // write 0x00 to 0x0353 + init_data[346] = cmd_wr(8'h00); // write 0x00 to 0x0354 + init_data[347] = cmd_wr(8'h00); // write 0x00 to 0x0355 + init_data[348] = cmd_wr(8'h00); // write 0x00 to 0x0356 + init_data[349] = cmd_wr(8'h00); // write 0x00 to 0x0357 + init_data[350] = cmd_wr(8'h00); // write 0x00 to 0x0358 + init_data[351] = cmd_wr(8'h00); // write 0x00 to 0x0359 + init_data[352] = cmd_wr(8'h00); // write 0x00 to 0x035a + init_data[353] = cmd_wr(8'h00); // write 0x00 to 0x035b + init_data[354] = cmd_wr(8'h00); // write 0x00 to 0x035c + init_data[355] = cmd_wr(8'h00); // write 0x00 to 0x035d + init_data[356] = cmd_wr(8'h00); // write 0x00 to 0x035e + init_data[357] = cmd_wr(8'h00); // write 0x00 to 0x035f + init_data[358] = cmd_wr(8'h00); // write 0x00 to 0x0360 + init_data[359] = cmd_wr(8'h00); // write 0x00 to 0x0361 + init_data[360] = cmd_wr(8'h00); // write 0x00 to 0x0362 + init_data[361] = cmd_start(7'h77); + init_data[362] = cmd_wr(8'h01); + init_data[363] = cmd_wr(8'h08); // set page 0x08 + init_data[364] = cmd_start(7'h77); + init_data[365] = cmd_wr(8'h02); + init_data[366] = cmd_wr(8'h00); // write 0x00 to 0x0802 + init_data[367] = cmd_wr(8'h00); // write 0x00 to 0x0803 + init_data[368] = cmd_wr(8'h00); // write 0x00 to 0x0804 + init_data[369] = cmd_wr(8'h00); // write 0x00 to 0x0805 + init_data[370] = cmd_wr(8'h00); // write 0x00 to 0x0806 + init_data[371] = cmd_wr(8'h00); // write 0x00 to 0x0807 + init_data[372] = cmd_wr(8'h00); // write 0x00 to 0x0808 + init_data[373] = cmd_wr(8'h00); // write 0x00 to 0x0809 + init_data[374] = cmd_wr(8'h00); // write 0x00 to 0x080a + init_data[375] = cmd_wr(8'h00); // write 0x00 to 0x080b + init_data[376] = cmd_wr(8'h00); // write 0x00 to 0x080c + init_data[377] = cmd_wr(8'h00); // write 0x00 to 0x080d + init_data[378] = cmd_wr(8'h00); // write 0x00 to 0x080e + init_data[379] = cmd_wr(8'h00); // write 0x00 to 0x080f + init_data[380] = cmd_wr(8'h00); // write 0x00 to 0x0810 + init_data[381] = cmd_wr(8'h00); // write 0x00 to 0x0811 + init_data[382] = cmd_wr(8'h00); // write 0x00 to 0x0812 + init_data[383] = cmd_wr(8'h00); // write 0x00 to 0x0813 + init_data[384] = cmd_wr(8'h00); // write 0x00 to 0x0814 + init_data[385] = cmd_wr(8'h00); // write 0x00 to 0x0815 + init_data[386] = cmd_wr(8'h00); // write 0x00 to 0x0816 + init_data[387] = cmd_wr(8'h00); // write 0x00 to 0x0817 + init_data[388] = cmd_wr(8'h00); // write 0x00 to 0x0818 + init_data[389] = cmd_wr(8'h00); // write 0x00 to 0x0819 + init_data[390] = cmd_wr(8'h00); // write 0x00 to 0x081a + init_data[391] = cmd_wr(8'h00); // write 0x00 to 0x081b + init_data[392] = cmd_wr(8'h00); // write 0x00 to 0x081c + init_data[393] = cmd_wr(8'h00); // write 0x00 to 0x081d + init_data[394] = cmd_wr(8'h00); // write 0x00 to 0x081e + init_data[395] = cmd_wr(8'h00); // write 0x00 to 0x081f + init_data[396] = cmd_wr(8'h00); // write 0x00 to 0x0820 + init_data[397] = cmd_wr(8'h00); // write 0x00 to 0x0821 + init_data[398] = cmd_wr(8'h00); // write 0x00 to 0x0822 + init_data[399] = cmd_wr(8'h00); // write 0x00 to 0x0823 + init_data[400] = cmd_wr(8'h00); // write 0x00 to 0x0824 + init_data[401] = cmd_wr(8'h00); // write 0x00 to 0x0825 + init_data[402] = cmd_wr(8'h00); // write 0x00 to 0x0826 + init_data[403] = cmd_wr(8'h00); // write 0x00 to 0x0827 + init_data[404] = cmd_wr(8'h00); // write 0x00 to 0x0828 + init_data[405] = cmd_wr(8'h00); // write 0x00 to 0x0829 + init_data[406] = cmd_wr(8'h00); // write 0x00 to 0x082a + init_data[407] = cmd_wr(8'h00); // write 0x00 to 0x082b + init_data[408] = cmd_wr(8'h00); // write 0x00 to 0x082c + init_data[409] = cmd_wr(8'h00); // write 0x00 to 0x082d + init_data[410] = cmd_wr(8'h00); // write 0x00 to 0x082e + init_data[411] = cmd_wr(8'h00); // write 0x00 to 0x082f + init_data[412] = cmd_wr(8'h00); // write 0x00 to 0x0830 + init_data[413] = cmd_wr(8'h00); // write 0x00 to 0x0831 + init_data[414] = cmd_wr(8'h00); // write 0x00 to 0x0832 + init_data[415] = cmd_wr(8'h00); // write 0x00 to 0x0833 + init_data[416] = cmd_wr(8'h00); // write 0x00 to 0x0834 + init_data[417] = cmd_wr(8'h00); // write 0x00 to 0x0835 + init_data[418] = cmd_wr(8'h00); // write 0x00 to 0x0836 + init_data[419] = cmd_wr(8'h00); // write 0x00 to 0x0837 + init_data[420] = cmd_wr(8'h00); // write 0x00 to 0x0838 + init_data[421] = cmd_wr(8'h00); // write 0x00 to 0x0839 + init_data[422] = cmd_wr(8'h00); // write 0x00 to 0x083a + init_data[423] = cmd_wr(8'h00); // write 0x00 to 0x083b + init_data[424] = cmd_wr(8'h00); // write 0x00 to 0x083c + init_data[425] = cmd_wr(8'h00); // write 0x00 to 0x083d + init_data[426] = cmd_wr(8'h00); // write 0x00 to 0x083e + init_data[427] = cmd_wr(8'h00); // write 0x00 to 0x083f + init_data[428] = cmd_wr(8'h00); // write 0x00 to 0x0840 + init_data[429] = cmd_wr(8'h00); // write 0x00 to 0x0841 + init_data[430] = cmd_wr(8'h00); // write 0x00 to 0x0842 + init_data[431] = cmd_wr(8'h00); // write 0x00 to 0x0843 + init_data[432] = cmd_wr(8'h00); // write 0x00 to 0x0844 + init_data[433] = cmd_wr(8'h00); // write 0x00 to 0x0845 + init_data[434] = cmd_wr(8'h00); // write 0x00 to 0x0846 + init_data[435] = cmd_wr(8'h00); // write 0x00 to 0x0847 + init_data[436] = cmd_wr(8'h00); // write 0x00 to 0x0848 + init_data[437] = cmd_wr(8'h00); // write 0x00 to 0x0849 + init_data[438] = cmd_wr(8'h00); // write 0x00 to 0x084a + init_data[439] = cmd_wr(8'h00); // write 0x00 to 0x084b + init_data[440] = cmd_wr(8'h00); // write 0x00 to 0x084c + init_data[441] = cmd_wr(8'h00); // write 0x00 to 0x084d + init_data[442] = cmd_wr(8'h00); // write 0x00 to 0x084e + init_data[443] = cmd_wr(8'h00); // write 0x00 to 0x084f + init_data[444] = cmd_wr(8'h00); // write 0x00 to 0x0850 + init_data[445] = cmd_wr(8'h00); // write 0x00 to 0x0851 + init_data[446] = cmd_wr(8'h00); // write 0x00 to 0x0852 + init_data[447] = cmd_wr(8'h00); // write 0x00 to 0x0853 + init_data[448] = cmd_wr(8'h00); // write 0x00 to 0x0854 + init_data[449] = cmd_wr(8'h00); // write 0x00 to 0x0855 + init_data[450] = cmd_wr(8'h00); // write 0x00 to 0x0856 + init_data[451] = cmd_wr(8'h00); // write 0x00 to 0x0857 + init_data[452] = cmd_wr(8'h00); // write 0x00 to 0x0858 + init_data[453] = cmd_wr(8'h00); // write 0x00 to 0x0859 + init_data[454] = cmd_wr(8'h00); // write 0x00 to 0x085a + init_data[455] = cmd_wr(8'h00); // write 0x00 to 0x085b + init_data[456] = cmd_wr(8'h00); // write 0x00 to 0x085c + init_data[457] = cmd_wr(8'h00); // write 0x00 to 0x085d + init_data[458] = cmd_wr(8'h00); // write 0x00 to 0x085e + init_data[459] = cmd_wr(8'h00); // write 0x00 to 0x085f + init_data[460] = cmd_wr(8'h00); // write 0x00 to 0x0860 + init_data[461] = cmd_wr(8'h00); // write 0x00 to 0x0861 + init_data[462] = cmd_start(7'h77); + init_data[463] = cmd_wr(8'h01); + init_data[464] = cmd_wr(8'h09); // set page 0x09 + init_data[465] = cmd_start(7'h77); + init_data[466] = cmd_wr(8'h0e); + init_data[467] = cmd_wr(8'h00); // write 0x00 to 0x090e + init_data[468] = cmd_start(7'h77); + init_data[469] = cmd_wr(8'h1c); + init_data[470] = cmd_wr(8'h04); // write 0x04 to 0x091c + init_data[471] = cmd_start(7'h77); + init_data[472] = cmd_wr(8'h43); + init_data[473] = cmd_wr(8'h00); // write 0x00 to 0x0943 + init_data[474] = cmd_start(7'h77); + init_data[475] = cmd_wr(8'h49); + init_data[476] = cmd_wr(8'h03); // write 0x03 to 0x0949 + init_data[477] = cmd_wr(8'h30); // write 0x30 to 0x094a + init_data[478] = cmd_start(7'h77); + init_data[479] = cmd_wr(8'h4e); + init_data[480] = cmd_wr(8'h49); // write 0x49 to 0x094e + init_data[481] = cmd_wr(8'h02); // write 0x02 to 0x094f + init_data[482] = cmd_start(7'h77); + init_data[483] = cmd_wr(8'h5e); + init_data[484] = cmd_wr(8'h00); // write 0x00 to 0x095e + init_data[485] = cmd_start(7'h77); + init_data[486] = cmd_wr(8'h01); + init_data[487] = cmd_wr(8'h0a); // set page 0x0a + init_data[488] = cmd_start(7'h77); + init_data[489] = cmd_wr(8'h02); + init_data[490] = cmd_wr(8'h00); // write 0x00 to 0x0a02 + init_data[491] = cmd_wr(8'h03); // write 0x03 to 0x0a03 + init_data[492] = cmd_wr(8'h01); // write 0x01 to 0x0a04 + init_data[493] = cmd_wr(8'h03); // write 0x03 to 0x0a05 + init_data[494] = cmd_start(7'h77); + init_data[495] = cmd_wr(8'h14); + init_data[496] = cmd_wr(8'h00); // write 0x00 to 0x0a14 + init_data[497] = cmd_start(7'h77); + init_data[498] = cmd_wr(8'h1a); + init_data[499] = cmd_wr(8'h00); // write 0x00 to 0x0a1a + init_data[500] = cmd_start(7'h77); + init_data[501] = cmd_wr(8'h20); + init_data[502] = cmd_wr(8'h00); // write 0x00 to 0x0a20 + init_data[503] = cmd_start(7'h77); + init_data[504] = cmd_wr(8'h26); + init_data[505] = cmd_wr(8'h00); // write 0x00 to 0x0a26 + init_data[506] = cmd_start(7'h77); + init_data[507] = cmd_wr(8'h2c); + init_data[508] = cmd_wr(8'h00); // write 0x00 to 0x0a2c + init_data[509] = cmd_start(7'h77); + init_data[510] = cmd_wr(8'h01); + init_data[511] = cmd_wr(8'h0b); // set page 0x0b + init_data[512] = cmd_start(7'h77); + init_data[513] = cmd_wr(8'h44); + init_data[514] = cmd_wr(8'h0f); // write 0x0f to 0x0b44 + init_data[515] = cmd_start(7'h77); + init_data[516] = cmd_wr(8'h4a); + init_data[517] = cmd_wr(8'h1c); // write 0x1c to 0x0b4a + init_data[518] = cmd_start(7'h77); + init_data[519] = cmd_wr(8'h57); + init_data[520] = cmd_wr(8'ha5); // write 0xa5 to 0x0b57 + init_data[521] = cmd_wr(8'h00); // write 0x00 to 0x0b58 + // End configuration registers + // + // Start configuration postamble + init_data[522] = cmd_start(7'h77); + init_data[523] = cmd_wr(8'h01); + init_data[524] = cmd_wr(8'h00); // set page 0x00 + init_data[525] = cmd_start(7'h77); + init_data[526] = cmd_wr(8'h1c); + init_data[527] = cmd_wr(8'h01); // write 0x01 to 0x001c + init_data[528] = cmd_start(7'h77); + init_data[529] = cmd_wr(8'h01); + init_data[530] = cmd_wr(8'h0b); // set page 0x0b + init_data[531] = cmd_start(7'h77); + init_data[532] = cmd_wr(8'h24); + init_data[533] = cmd_wr(8'hc3); // write 0xc3 to 0x0b24 + init_data[534] = cmd_wr(8'h02); // write 0x02 to 0x0b25 + // End configuration postamble + // Set muxes to select U7 Si5341 on HTG-FMC-x6-QSFP28 + init_data[535] = cmd_start(7'h70); + init_data[536] = cmd_wr(8'h00); + init_data[537] = cmd_stop(); // I2C stop + init_data[538] = cmd_start(7'h71); + init_data[539] = cmd_wr(8'h02); + init_data[540] = cmd_stop(); // I2C stop + // Si534x/7x/8x/9x Registers Script + // + // Part: Si5341 + // Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_fmc_htg_6qsfp_25g\pll\HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj + // Design ID: HTG6Q161 + // Includes Pre/Post Download Control Register Writes: Yes + // Die Revision: B1 + // Creator: ClockBuilder Pro v4.1 [2021-09-22] + // Created On: 2023-07-19 01:56:52 GMT-07:00 + // + // Start configuration preamble + init_data[541] = cmd_start(7'h77); + init_data[542] = cmd_wr(8'h01); + init_data[543] = cmd_wr(8'h0b); // set page 0x0b + init_data[544] = cmd_start(7'h77); + init_data[545] = cmd_wr(8'h24); + init_data[546] = cmd_wr(8'hc0); // write 0xc0 to 0x0b24 + init_data[547] = cmd_wr(8'h00); // write 0x00 to 0x0b25 + // Rev D stuck divider fix + init_data[548] = cmd_start(7'h77); + init_data[549] = cmd_wr(8'h01); + init_data[550] = cmd_wr(8'h05); // set page 0x05 + init_data[551] = cmd_start(7'h77); + init_data[552] = cmd_wr(8'h02); + init_data[553] = cmd_wr(8'h01); // write 0x01 to 0x0502 + init_data[554] = cmd_start(7'h77); + init_data[555] = cmd_wr(8'h05); + init_data[556] = cmd_wr(8'h03); // write 0x03 to 0x0505 + init_data[557] = cmd_start(7'h77); + init_data[558] = cmd_wr(8'h01); + init_data[559] = cmd_wr(8'h09); // set page 0x09 + init_data[560] = cmd_start(7'h77); + init_data[561] = cmd_wr(8'h57); + init_data[562] = cmd_wr(8'h17); // write 0x17 to 0x0957 + init_data[563] = cmd_start(7'h77); + init_data[564] = cmd_wr(8'h01); + init_data[565] = cmd_wr(8'h0b); // set page 0x0b + init_data[566] = cmd_start(7'h77); + init_data[567] = cmd_wr(8'h4e); + init_data[568] = cmd_wr(8'h1a); // write 0x1a to 0x0b4e + // End configuration preamble + // + // Delay 300 msec + init_data[569] = cmd_delay(10); // delay 300 ms + // Delay is worst case time for device to complete any calibration + // that is running due to device state change previous to this script + // being processed. + // + // Start configuration registers + init_data[570] = cmd_start(7'h77); + init_data[571] = cmd_wr(8'h01); + init_data[572] = cmd_wr(8'h00); // set page 0x00 + init_data[573] = cmd_start(7'h77); + init_data[574] = cmd_wr(8'h06); + init_data[575] = cmd_wr(8'h00); // write 0x00 to 0x0006 + init_data[576] = cmd_wr(8'h00); // write 0x00 to 0x0007 + init_data[577] = cmd_wr(8'h00); // write 0x00 to 0x0008 + init_data[578] = cmd_start(7'h77); + init_data[579] = cmd_wr(8'h0b); + init_data[580] = cmd_wr(8'h74); // write 0x74 to 0x000b + init_data[581] = cmd_start(7'h77); + init_data[582] = cmd_wr(8'h17); + init_data[583] = cmd_wr(8'hd0); // write 0xd0 to 0x0017 + init_data[584] = cmd_wr(8'hff); // write 0xff to 0x0018 + init_data[585] = cmd_start(7'h77); + init_data[586] = cmd_wr(8'h21); + init_data[587] = cmd_wr(8'h0d); // write 0x0d to 0x0021 + init_data[588] = cmd_wr(8'h00); // write 0x00 to 0x0022 + init_data[589] = cmd_start(7'h77); + init_data[590] = cmd_wr(8'h2b); + init_data[591] = cmd_wr(8'h02); // write 0x02 to 0x002b + init_data[592] = cmd_wr(8'h34); // write 0x34 to 0x002c + init_data[593] = cmd_wr(8'h10); // write 0x10 to 0x002d + init_data[594] = cmd_wr(8'h00); // write 0x00 to 0x002e + init_data[595] = cmd_wr(8'h00); // write 0x00 to 0x002f + init_data[596] = cmd_wr(8'h00); // write 0x00 to 0x0030 + init_data[597] = cmd_wr(8'h00); // write 0x00 to 0x0031 + init_data[598] = cmd_wr(8'ha8); // write 0xa8 to 0x0032 + init_data[599] = cmd_wr(8'h00); // write 0x00 to 0x0033 + init_data[600] = cmd_wr(8'h00); // write 0x00 to 0x0034 + init_data[601] = cmd_wr(8'h00); // write 0x00 to 0x0035 + init_data[602] = cmd_wr(8'h00); // write 0x00 to 0x0036 + init_data[603] = cmd_wr(8'h00); // write 0x00 to 0x0037 + init_data[604] = cmd_wr(8'h00); // write 0x00 to 0x0038 + init_data[605] = cmd_wr(8'h00); // write 0x00 to 0x0039 + init_data[606] = cmd_wr(8'ha8); // write 0xa8 to 0x003a + init_data[607] = cmd_wr(8'h00); // write 0x00 to 0x003b + init_data[608] = cmd_wr(8'h00); // write 0x00 to 0x003c + init_data[609] = cmd_wr(8'h00); // write 0x00 to 0x003d + init_data[610] = cmd_start(7'h77); + init_data[611] = cmd_wr(8'h41); + init_data[612] = cmd_wr(8'h00); // write 0x00 to 0x0041 + init_data[613] = cmd_wr(8'h00); // write 0x00 to 0x0042 + init_data[614] = cmd_wr(8'h07); // write 0x07 to 0x0043 + init_data[615] = cmd_wr(8'h00); // write 0x00 to 0x0044 + init_data[616] = cmd_start(7'h77); + init_data[617] = cmd_wr(8'h9e); + init_data[618] = cmd_wr(8'h00); // write 0x00 to 0x009e + init_data[619] = cmd_start(7'h77); + init_data[620] = cmd_wr(8'h01); + init_data[621] = cmd_wr(8'h01); // set page 0x01 + init_data[622] = cmd_start(7'h77); + init_data[623] = cmd_wr(8'h02); + init_data[624] = cmd_wr(8'h01); // write 0x01 to 0x0102 + init_data[625] = cmd_start(7'h77); + init_data[626] = cmd_wr(8'h08); + init_data[627] = cmd_wr(8'h06); // write 0x06 to 0x0108 + init_data[628] = cmd_wr(8'h09); // write 0x09 to 0x0109 + init_data[629] = cmd_wr(8'h33); // write 0x33 to 0x010a + init_data[630] = cmd_wr(8'h08); // write 0x08 to 0x010b + init_data[631] = cmd_start(7'h77); + init_data[632] = cmd_wr(8'h0d); + init_data[633] = cmd_wr(8'h06); // write 0x06 to 0x010d + init_data[634] = cmd_wr(8'h09); // write 0x09 to 0x010e + init_data[635] = cmd_wr(8'h33); // write 0x33 to 0x010f + init_data[636] = cmd_wr(8'h08); // write 0x08 to 0x0110 + init_data[637] = cmd_start(7'h77); + init_data[638] = cmd_wr(8'h12); + init_data[639] = cmd_wr(8'h06); // write 0x06 to 0x0112 + init_data[640] = cmd_wr(8'h09); // write 0x09 to 0x0113 + init_data[641] = cmd_wr(8'h33); // write 0x33 to 0x0114 + init_data[642] = cmd_wr(8'h08); // write 0x08 to 0x0115 + init_data[643] = cmd_start(7'h77); + init_data[644] = cmd_wr(8'h17); + init_data[645] = cmd_wr(8'h06); // write 0x06 to 0x0117 + init_data[646] = cmd_wr(8'h09); // write 0x09 to 0x0118 + init_data[647] = cmd_wr(8'h33); // write 0x33 to 0x0119 + init_data[648] = cmd_wr(8'h08); // write 0x08 to 0x011a + init_data[649] = cmd_start(7'h77); + init_data[650] = cmd_wr(8'h1c); + init_data[651] = cmd_wr(8'h06); // write 0x06 to 0x011c + init_data[652] = cmd_wr(8'h09); // write 0x09 to 0x011d + init_data[653] = cmd_wr(8'h33); // write 0x33 to 0x011e + init_data[654] = cmd_wr(8'h08); // write 0x08 to 0x011f + init_data[655] = cmd_start(7'h77); + init_data[656] = cmd_wr(8'h21); + init_data[657] = cmd_wr(8'h06); // write 0x06 to 0x0121 + init_data[658] = cmd_wr(8'h09); // write 0x09 to 0x0122 + init_data[659] = cmd_wr(8'h33); // write 0x33 to 0x0123 + init_data[660] = cmd_wr(8'h08); // write 0x08 to 0x0124 + init_data[661] = cmd_start(7'h77); + init_data[662] = cmd_wr(8'h26); + init_data[663] = cmd_wr(8'h06); // write 0x06 to 0x0126 + init_data[664] = cmd_wr(8'h09); // write 0x09 to 0x0127 + init_data[665] = cmd_wr(8'h33); // write 0x33 to 0x0128 + init_data[666] = cmd_wr(8'h08); // write 0x08 to 0x0129 + init_data[667] = cmd_start(7'h77); + init_data[668] = cmd_wr(8'h2b); + init_data[669] = cmd_wr(8'h06); // write 0x06 to 0x012b + init_data[670] = cmd_wr(8'h09); // write 0x09 to 0x012c + init_data[671] = cmd_wr(8'h33); // write 0x33 to 0x012d + init_data[672] = cmd_wr(8'h08); // write 0x08 to 0x012e + init_data[673] = cmd_start(7'h77); + init_data[674] = cmd_wr(8'h30); + init_data[675] = cmd_wr(8'h06); // write 0x06 to 0x0130 + init_data[676] = cmd_wr(8'h09); // write 0x09 to 0x0131 + init_data[677] = cmd_wr(8'h33); // write 0x33 to 0x0132 + init_data[678] = cmd_wr(8'h08); // write 0x08 to 0x0133 + init_data[679] = cmd_start(7'h77); + init_data[680] = cmd_wr(8'h3a); + init_data[681] = cmd_wr(8'h01); // write 0x01 to 0x013a + init_data[682] = cmd_wr(8'h09); // write 0x09 to 0x013b + init_data[683] = cmd_wr(8'h3b); // write 0x3b to 0x013c + init_data[684] = cmd_wr(8'h28); // write 0x28 to 0x013d + init_data[685] = cmd_start(7'h77); + init_data[686] = cmd_wr(8'h3f); + init_data[687] = cmd_wr(8'h00); // write 0x00 to 0x013f + init_data[688] = cmd_wr(8'h00); // write 0x00 to 0x0140 + init_data[689] = cmd_wr(8'h40); // write 0x40 to 0x0141 + init_data[690] = cmd_start(7'h77); + init_data[691] = cmd_wr(8'h01); + init_data[692] = cmd_wr(8'h02); // set page 0x02 + init_data[693] = cmd_start(7'h77); + init_data[694] = cmd_wr(8'h06); + init_data[695] = cmd_wr(8'h00); // write 0x00 to 0x0206 + init_data[696] = cmd_start(7'h77); + init_data[697] = cmd_wr(8'h08); + init_data[698] = cmd_wr(8'h00); // write 0x00 to 0x0208 + init_data[699] = cmd_wr(8'h00); // write 0x00 to 0x0209 + init_data[700] = cmd_wr(8'h00); // write 0x00 to 0x020a + init_data[701] = cmd_wr(8'h00); // write 0x00 to 0x020b + init_data[702] = cmd_wr(8'h00); // write 0x00 to 0x020c + init_data[703] = cmd_wr(8'h00); // write 0x00 to 0x020d + init_data[704] = cmd_wr(8'h00); // write 0x00 to 0x020e + init_data[705] = cmd_wr(8'h00); // write 0x00 to 0x020f + init_data[706] = cmd_wr(8'h00); // write 0x00 to 0x0210 + init_data[707] = cmd_wr(8'h00); // write 0x00 to 0x0211 + init_data[708] = cmd_wr(8'h00); // write 0x00 to 0x0212 + init_data[709] = cmd_wr(8'h00); // write 0x00 to 0x0213 + init_data[710] = cmd_wr(8'h00); // write 0x00 to 0x0214 + init_data[711] = cmd_wr(8'h00); // write 0x00 to 0x0215 + init_data[712] = cmd_wr(8'h00); // write 0x00 to 0x0216 + init_data[713] = cmd_wr(8'h00); // write 0x00 to 0x0217 + init_data[714] = cmd_wr(8'h00); // write 0x00 to 0x0218 + init_data[715] = cmd_wr(8'h00); // write 0x00 to 0x0219 + init_data[716] = cmd_wr(8'h00); // write 0x00 to 0x021a + init_data[717] = cmd_wr(8'h00); // write 0x00 to 0x021b + init_data[718] = cmd_wr(8'h02); // write 0x02 to 0x021c + init_data[719] = cmd_wr(8'h00); // write 0x00 to 0x021d + init_data[720] = cmd_wr(8'h00); // write 0x00 to 0x021e + init_data[721] = cmd_wr(8'h00); // write 0x00 to 0x021f + init_data[722] = cmd_wr(8'h00); // write 0x00 to 0x0220 + init_data[723] = cmd_wr(8'h00); // write 0x00 to 0x0221 + init_data[724] = cmd_wr(8'h01); // write 0x01 to 0x0222 + init_data[725] = cmd_wr(8'h00); // write 0x00 to 0x0223 + init_data[726] = cmd_wr(8'h00); // write 0x00 to 0x0224 + init_data[727] = cmd_wr(8'h00); // write 0x00 to 0x0225 + init_data[728] = cmd_wr(8'h00); // write 0x00 to 0x0226 + init_data[729] = cmd_wr(8'h00); // write 0x00 to 0x0227 + init_data[730] = cmd_wr(8'h00); // write 0x00 to 0x0228 + init_data[731] = cmd_wr(8'h00); // write 0x00 to 0x0229 + init_data[732] = cmd_wr(8'h00); // write 0x00 to 0x022a + init_data[733] = cmd_wr(8'h00); // write 0x00 to 0x022b + init_data[734] = cmd_wr(8'h00); // write 0x00 to 0x022c + init_data[735] = cmd_wr(8'h00); // write 0x00 to 0x022d + init_data[736] = cmd_wr(8'h00); // write 0x00 to 0x022e + init_data[737] = cmd_wr(8'h00); // write 0x00 to 0x022f + init_data[738] = cmd_start(7'h77); + init_data[739] = cmd_wr(8'h35); + init_data[740] = cmd_wr(8'h00); // write 0x00 to 0x0235 + init_data[741] = cmd_wr(8'h00); // write 0x00 to 0x0236 + init_data[742] = cmd_wr(8'h00); // write 0x00 to 0x0237 + init_data[743] = cmd_wr(8'h00); // write 0x00 to 0x0238 + init_data[744] = cmd_wr(8'h52); // write 0x52 to 0x0239 + init_data[745] = cmd_wr(8'h00); // write 0x00 to 0x023a + init_data[746] = cmd_wr(8'h00); // write 0x00 to 0x023b + init_data[747] = cmd_wr(8'h00); // write 0x00 to 0x023c + init_data[748] = cmd_wr(8'h00); // write 0x00 to 0x023d + init_data[749] = cmd_wr(8'h80); // write 0x80 to 0x023e + init_data[750] = cmd_start(7'h77); + init_data[751] = cmd_wr(8'h4a); + init_data[752] = cmd_wr(8'h00); // write 0x00 to 0x024a + init_data[753] = cmd_wr(8'h00); // write 0x00 to 0x024b + init_data[754] = cmd_wr(8'h00); // write 0x00 to 0x024c + init_data[755] = cmd_wr(8'h00); // write 0x00 to 0x024d + init_data[756] = cmd_wr(8'h00); // write 0x00 to 0x024e + init_data[757] = cmd_wr(8'h00); // write 0x00 to 0x024f + init_data[758] = cmd_wr(8'h00); // write 0x00 to 0x0250 + init_data[759] = cmd_wr(8'h00); // write 0x00 to 0x0251 + init_data[760] = cmd_wr(8'h00); // write 0x00 to 0x0252 + init_data[761] = cmd_wr(8'h00); // write 0x00 to 0x0253 + init_data[762] = cmd_wr(8'h00); // write 0x00 to 0x0254 + init_data[763] = cmd_wr(8'h00); // write 0x00 to 0x0255 + init_data[764] = cmd_wr(8'h00); // write 0x00 to 0x0256 + init_data[765] = cmd_wr(8'h00); // write 0x00 to 0x0257 + init_data[766] = cmd_wr(8'h00); // write 0x00 to 0x0258 + init_data[767] = cmd_wr(8'h00); // write 0x00 to 0x0259 + init_data[768] = cmd_wr(8'h00); // write 0x00 to 0x025a + init_data[769] = cmd_wr(8'h00); // write 0x00 to 0x025b + init_data[770] = cmd_wr(8'h00); // write 0x00 to 0x025c + init_data[771] = cmd_wr(8'h00); // write 0x00 to 0x025d + init_data[772] = cmd_wr(8'h00); // write 0x00 to 0x025e + init_data[773] = cmd_wr(8'h00); // write 0x00 to 0x025f + init_data[774] = cmd_wr(8'h00); // write 0x00 to 0x0260 + init_data[775] = cmd_wr(8'h00); // write 0x00 to 0x0261 + init_data[776] = cmd_wr(8'h00); // write 0x00 to 0x0262 + init_data[777] = cmd_wr(8'h00); // write 0x00 to 0x0263 + init_data[778] = cmd_wr(8'h00); // write 0x00 to 0x0264 + init_data[779] = cmd_start(7'h77); + init_data[780] = cmd_wr(8'h68); + init_data[781] = cmd_wr(8'h00); // write 0x00 to 0x0268 + init_data[782] = cmd_wr(8'h00); // write 0x00 to 0x0269 + init_data[783] = cmd_wr(8'h00); // write 0x00 to 0x026a + init_data[784] = cmd_wr(8'h48); // write 0x48 to 0x026b + init_data[785] = cmd_wr(8'h54); // write 0x54 to 0x026c + init_data[786] = cmd_wr(8'h47); // write 0x47 to 0x026d + init_data[787] = cmd_wr(8'h36); // write 0x36 to 0x026e + init_data[788] = cmd_wr(8'h51); // write 0x51 to 0x026f + init_data[789] = cmd_wr(8'h31); // write 0x31 to 0x0270 + init_data[790] = cmd_wr(8'h36); // write 0x36 to 0x0271 + init_data[791] = cmd_wr(8'h31); // write 0x31 to 0x0272 + init_data[792] = cmd_start(7'h77); + init_data[793] = cmd_wr(8'h01); + init_data[794] = cmd_wr(8'h03); // set page 0x03 + init_data[795] = cmd_start(7'h77); + init_data[796] = cmd_wr(8'h02); + init_data[797] = cmd_wr(8'h00); // write 0x00 to 0x0302 + init_data[798] = cmd_wr(8'h00); // write 0x00 to 0x0303 + init_data[799] = cmd_wr(8'h00); // write 0x00 to 0x0304 + init_data[800] = cmd_wr(8'h80); // write 0x80 to 0x0305 + init_data[801] = cmd_wr(8'h14); // write 0x14 to 0x0306 + init_data[802] = cmd_wr(8'h00); // write 0x00 to 0x0307 + init_data[803] = cmd_wr(8'h00); // write 0x00 to 0x0308 + init_data[804] = cmd_wr(8'h00); // write 0x00 to 0x0309 + init_data[805] = cmd_wr(8'h00); // write 0x00 to 0x030a + init_data[806] = cmd_wr(8'h80); // write 0x80 to 0x030b + init_data[807] = cmd_wr(8'h00); // write 0x00 to 0x030c + init_data[808] = cmd_wr(8'h00); // write 0x00 to 0x030d + init_data[809] = cmd_wr(8'h00); // write 0x00 to 0x030e + init_data[810] = cmd_wr(8'h00); // write 0x00 to 0x030f + init_data[811] = cmd_wr(8'h00); // write 0x00 to 0x0310 + init_data[812] = cmd_wr(8'h00); // write 0x00 to 0x0311 + init_data[813] = cmd_wr(8'h00); // write 0x00 to 0x0312 + init_data[814] = cmd_wr(8'h00); // write 0x00 to 0x0313 + init_data[815] = cmd_wr(8'h00); // write 0x00 to 0x0314 + init_data[816] = cmd_wr(8'h00); // write 0x00 to 0x0315 + init_data[817] = cmd_wr(8'h00); // write 0x00 to 0x0316 + init_data[818] = cmd_wr(8'h00); // write 0x00 to 0x0317 + init_data[819] = cmd_wr(8'h00); // write 0x00 to 0x0318 + init_data[820] = cmd_wr(8'h00); // write 0x00 to 0x0319 + init_data[821] = cmd_wr(8'h00); // write 0x00 to 0x031a + init_data[822] = cmd_wr(8'h00); // write 0x00 to 0x031b + init_data[823] = cmd_wr(8'h00); // write 0x00 to 0x031c + init_data[824] = cmd_wr(8'h00); // write 0x00 to 0x031d + init_data[825] = cmd_wr(8'h00); // write 0x00 to 0x031e + init_data[826] = cmd_wr(8'h00); // write 0x00 to 0x031f + init_data[827] = cmd_wr(8'h00); // write 0x00 to 0x0320 + init_data[828] = cmd_wr(8'h00); // write 0x00 to 0x0321 + init_data[829] = cmd_wr(8'h00); // write 0x00 to 0x0322 + init_data[830] = cmd_wr(8'h00); // write 0x00 to 0x0323 + init_data[831] = cmd_wr(8'h00); // write 0x00 to 0x0324 + init_data[832] = cmd_wr(8'h00); // write 0x00 to 0x0325 + init_data[833] = cmd_wr(8'h00); // write 0x00 to 0x0326 + init_data[834] = cmd_wr(8'h00); // write 0x00 to 0x0327 + init_data[835] = cmd_wr(8'h00); // write 0x00 to 0x0328 + init_data[836] = cmd_wr(8'h00); // write 0x00 to 0x0329 + init_data[837] = cmd_wr(8'h00); // write 0x00 to 0x032a + init_data[838] = cmd_wr(8'h00); // write 0x00 to 0x032b + init_data[839] = cmd_wr(8'h00); // write 0x00 to 0x032c + init_data[840] = cmd_wr(8'h00); // write 0x00 to 0x032d + init_data[841] = cmd_wr(8'h00); // write 0x00 to 0x032e + init_data[842] = cmd_wr(8'h00); // write 0x00 to 0x032f + init_data[843] = cmd_wr(8'h00); // write 0x00 to 0x0330 + init_data[844] = cmd_wr(8'h00); // write 0x00 to 0x0331 + init_data[845] = cmd_wr(8'h00); // write 0x00 to 0x0332 + init_data[846] = cmd_wr(8'h00); // write 0x00 to 0x0333 + init_data[847] = cmd_wr(8'h00); // write 0x00 to 0x0334 + init_data[848] = cmd_wr(8'h00); // write 0x00 to 0x0335 + init_data[849] = cmd_wr(8'h00); // write 0x00 to 0x0336 + init_data[850] = cmd_wr(8'h00); // write 0x00 to 0x0337 + init_data[851] = cmd_wr(8'h00); // write 0x00 to 0x0338 + init_data[852] = cmd_wr(8'h1f); // write 0x1f to 0x0339 + init_data[853] = cmd_start(7'h77); + init_data[854] = cmd_wr(8'h3b); + init_data[855] = cmd_wr(8'h00); // write 0x00 to 0x033b + init_data[856] = cmd_wr(8'h00); // write 0x00 to 0x033c + init_data[857] = cmd_wr(8'h00); // write 0x00 to 0x033d + init_data[858] = cmd_wr(8'h00); // write 0x00 to 0x033e + init_data[859] = cmd_wr(8'h00); // write 0x00 to 0x033f + init_data[860] = cmd_wr(8'h00); // write 0x00 to 0x0340 + init_data[861] = cmd_wr(8'h00); // write 0x00 to 0x0341 + init_data[862] = cmd_wr(8'h00); // write 0x00 to 0x0342 + init_data[863] = cmd_wr(8'h00); // write 0x00 to 0x0343 + init_data[864] = cmd_wr(8'h00); // write 0x00 to 0x0344 + init_data[865] = cmd_wr(8'h00); // write 0x00 to 0x0345 + init_data[866] = cmd_wr(8'h00); // write 0x00 to 0x0346 + init_data[867] = cmd_wr(8'h00); // write 0x00 to 0x0347 + init_data[868] = cmd_wr(8'h00); // write 0x00 to 0x0348 + init_data[869] = cmd_wr(8'h00); // write 0x00 to 0x0349 + init_data[870] = cmd_wr(8'h00); // write 0x00 to 0x034a + init_data[871] = cmd_wr(8'h00); // write 0x00 to 0x034b + init_data[872] = cmd_wr(8'h00); // write 0x00 to 0x034c + init_data[873] = cmd_wr(8'h00); // write 0x00 to 0x034d + init_data[874] = cmd_wr(8'h00); // write 0x00 to 0x034e + init_data[875] = cmd_wr(8'h00); // write 0x00 to 0x034f + init_data[876] = cmd_wr(8'h00); // write 0x00 to 0x0350 + init_data[877] = cmd_wr(8'h00); // write 0x00 to 0x0351 + init_data[878] = cmd_wr(8'h00); // write 0x00 to 0x0352 + init_data[879] = cmd_wr(8'h00); // write 0x00 to 0x0353 + init_data[880] = cmd_wr(8'h00); // write 0x00 to 0x0354 + init_data[881] = cmd_wr(8'h00); // write 0x00 to 0x0355 + init_data[882] = cmd_wr(8'h00); // write 0x00 to 0x0356 + init_data[883] = cmd_wr(8'h00); // write 0x00 to 0x0357 + init_data[884] = cmd_wr(8'h00); // write 0x00 to 0x0358 + init_data[885] = cmd_wr(8'h00); // write 0x00 to 0x0359 + init_data[886] = cmd_wr(8'h00); // write 0x00 to 0x035a + init_data[887] = cmd_wr(8'h00); // write 0x00 to 0x035b + init_data[888] = cmd_wr(8'h00); // write 0x00 to 0x035c + init_data[889] = cmd_wr(8'h00); // write 0x00 to 0x035d + init_data[890] = cmd_wr(8'h00); // write 0x00 to 0x035e + init_data[891] = cmd_wr(8'h00); // write 0x00 to 0x035f + init_data[892] = cmd_wr(8'h00); // write 0x00 to 0x0360 + init_data[893] = cmd_wr(8'h00); // write 0x00 to 0x0361 + init_data[894] = cmd_wr(8'h00); // write 0x00 to 0x0362 + init_data[895] = cmd_start(7'h77); + init_data[896] = cmd_wr(8'h01); + init_data[897] = cmd_wr(8'h08); // set page 0x08 + init_data[898] = cmd_start(7'h77); + init_data[899] = cmd_wr(8'h02); + init_data[900] = cmd_wr(8'h00); // write 0x00 to 0x0802 + init_data[901] = cmd_wr(8'h00); // write 0x00 to 0x0803 + init_data[902] = cmd_wr(8'h00); // write 0x00 to 0x0804 + init_data[903] = cmd_wr(8'h00); // write 0x00 to 0x0805 + init_data[904] = cmd_wr(8'h00); // write 0x00 to 0x0806 + init_data[905] = cmd_wr(8'h00); // write 0x00 to 0x0807 + init_data[906] = cmd_wr(8'h00); // write 0x00 to 0x0808 + init_data[907] = cmd_wr(8'h00); // write 0x00 to 0x0809 + init_data[908] = cmd_wr(8'h00); // write 0x00 to 0x080a + init_data[909] = cmd_wr(8'h00); // write 0x00 to 0x080b + init_data[910] = cmd_wr(8'h00); // write 0x00 to 0x080c + init_data[911] = cmd_wr(8'h00); // write 0x00 to 0x080d + init_data[912] = cmd_wr(8'h00); // write 0x00 to 0x080e + init_data[913] = cmd_wr(8'h00); // write 0x00 to 0x080f + init_data[914] = cmd_wr(8'h00); // write 0x00 to 0x0810 + init_data[915] = cmd_wr(8'h00); // write 0x00 to 0x0811 + init_data[916] = cmd_wr(8'h00); // write 0x00 to 0x0812 + init_data[917] = cmd_wr(8'h00); // write 0x00 to 0x0813 + init_data[918] = cmd_wr(8'h00); // write 0x00 to 0x0814 + init_data[919] = cmd_wr(8'h00); // write 0x00 to 0x0815 + init_data[920] = cmd_wr(8'h00); // write 0x00 to 0x0816 + init_data[921] = cmd_wr(8'h00); // write 0x00 to 0x0817 + init_data[922] = cmd_wr(8'h00); // write 0x00 to 0x0818 + init_data[923] = cmd_wr(8'h00); // write 0x00 to 0x0819 + init_data[924] = cmd_wr(8'h00); // write 0x00 to 0x081a + init_data[925] = cmd_wr(8'h00); // write 0x00 to 0x081b + init_data[926] = cmd_wr(8'h00); // write 0x00 to 0x081c + init_data[927] = cmd_wr(8'h00); // write 0x00 to 0x081d + init_data[928] = cmd_wr(8'h00); // write 0x00 to 0x081e + init_data[929] = cmd_wr(8'h00); // write 0x00 to 0x081f + init_data[930] = cmd_wr(8'h00); // write 0x00 to 0x0820 + init_data[931] = cmd_wr(8'h00); // write 0x00 to 0x0821 + init_data[932] = cmd_wr(8'h00); // write 0x00 to 0x0822 + init_data[933] = cmd_wr(8'h00); // write 0x00 to 0x0823 + init_data[934] = cmd_wr(8'h00); // write 0x00 to 0x0824 + init_data[935] = cmd_wr(8'h00); // write 0x00 to 0x0825 + init_data[936] = cmd_wr(8'h00); // write 0x00 to 0x0826 + init_data[937] = cmd_wr(8'h00); // write 0x00 to 0x0827 + init_data[938] = cmd_wr(8'h00); // write 0x00 to 0x0828 + init_data[939] = cmd_wr(8'h00); // write 0x00 to 0x0829 + init_data[940] = cmd_wr(8'h00); // write 0x00 to 0x082a + init_data[941] = cmd_wr(8'h00); // write 0x00 to 0x082b + init_data[942] = cmd_wr(8'h00); // write 0x00 to 0x082c + init_data[943] = cmd_wr(8'h00); // write 0x00 to 0x082d + init_data[944] = cmd_wr(8'h00); // write 0x00 to 0x082e + init_data[945] = cmd_wr(8'h00); // write 0x00 to 0x082f + init_data[946] = cmd_wr(8'h00); // write 0x00 to 0x0830 + init_data[947] = cmd_wr(8'h00); // write 0x00 to 0x0831 + init_data[948] = cmd_wr(8'h00); // write 0x00 to 0x0832 + init_data[949] = cmd_wr(8'h00); // write 0x00 to 0x0833 + init_data[950] = cmd_wr(8'h00); // write 0x00 to 0x0834 + init_data[951] = cmd_wr(8'h00); // write 0x00 to 0x0835 + init_data[952] = cmd_wr(8'h00); // write 0x00 to 0x0836 + init_data[953] = cmd_wr(8'h00); // write 0x00 to 0x0837 + init_data[954] = cmd_wr(8'h00); // write 0x00 to 0x0838 + init_data[955] = cmd_wr(8'h00); // write 0x00 to 0x0839 + init_data[956] = cmd_wr(8'h00); // write 0x00 to 0x083a + init_data[957] = cmd_wr(8'h00); // write 0x00 to 0x083b + init_data[958] = cmd_wr(8'h00); // write 0x00 to 0x083c + init_data[959] = cmd_wr(8'h00); // write 0x00 to 0x083d + init_data[960] = cmd_wr(8'h00); // write 0x00 to 0x083e + init_data[961] = cmd_wr(8'h00); // write 0x00 to 0x083f + init_data[962] = cmd_wr(8'h00); // write 0x00 to 0x0840 + init_data[963] = cmd_wr(8'h00); // write 0x00 to 0x0841 + init_data[964] = cmd_wr(8'h00); // write 0x00 to 0x0842 + init_data[965] = cmd_wr(8'h00); // write 0x00 to 0x0843 + init_data[966] = cmd_wr(8'h00); // write 0x00 to 0x0844 + init_data[967] = cmd_wr(8'h00); // write 0x00 to 0x0845 + init_data[968] = cmd_wr(8'h00); // write 0x00 to 0x0846 + init_data[969] = cmd_wr(8'h00); // write 0x00 to 0x0847 + init_data[970] = cmd_wr(8'h00); // write 0x00 to 0x0848 + init_data[971] = cmd_wr(8'h00); // write 0x00 to 0x0849 + init_data[972] = cmd_wr(8'h00); // write 0x00 to 0x084a + init_data[973] = cmd_wr(8'h00); // write 0x00 to 0x084b + init_data[974] = cmd_wr(8'h00); // write 0x00 to 0x084c + init_data[975] = cmd_wr(8'h00); // write 0x00 to 0x084d + init_data[976] = cmd_wr(8'h00); // write 0x00 to 0x084e + init_data[977] = cmd_wr(8'h00); // write 0x00 to 0x084f + init_data[978] = cmd_wr(8'h00); // write 0x00 to 0x0850 + init_data[979] = cmd_wr(8'h00); // write 0x00 to 0x0851 + init_data[980] = cmd_wr(8'h00); // write 0x00 to 0x0852 + init_data[981] = cmd_wr(8'h00); // write 0x00 to 0x0853 + init_data[982] = cmd_wr(8'h00); // write 0x00 to 0x0854 + init_data[983] = cmd_wr(8'h00); // write 0x00 to 0x0855 + init_data[984] = cmd_wr(8'h00); // write 0x00 to 0x0856 + init_data[985] = cmd_wr(8'h00); // write 0x00 to 0x0857 + init_data[986] = cmd_wr(8'h00); // write 0x00 to 0x0858 + init_data[987] = cmd_wr(8'h00); // write 0x00 to 0x0859 + init_data[988] = cmd_wr(8'h00); // write 0x00 to 0x085a + init_data[989] = cmd_wr(8'h00); // write 0x00 to 0x085b + init_data[990] = cmd_wr(8'h00); // write 0x00 to 0x085c + init_data[991] = cmd_wr(8'h00); // write 0x00 to 0x085d + init_data[992] = cmd_wr(8'h00); // write 0x00 to 0x085e + init_data[993] = cmd_wr(8'h00); // write 0x00 to 0x085f + init_data[994] = cmd_wr(8'h00); // write 0x00 to 0x0860 + init_data[995] = cmd_wr(8'h00); // write 0x00 to 0x0861 + init_data[996] = cmd_start(7'h77); + init_data[997] = cmd_wr(8'h01); + init_data[998] = cmd_wr(8'h09); // set page 0x09 + init_data[999] = cmd_start(7'h77); + init_data[1000] = cmd_wr(8'h0e); + init_data[1001] = cmd_wr(8'h00); // write 0x00 to 0x090e + init_data[1002] = cmd_start(7'h77); + init_data[1003] = cmd_wr(8'h1c); + init_data[1004] = cmd_wr(8'h04); // write 0x04 to 0x091c + init_data[1005] = cmd_start(7'h77); + init_data[1006] = cmd_wr(8'h43); + init_data[1007] = cmd_wr(8'h00); // write 0x00 to 0x0943 + init_data[1008] = cmd_start(7'h77); + init_data[1009] = cmd_wr(8'h49); + init_data[1010] = cmd_wr(8'h04); // write 0x04 to 0x0949 + init_data[1011] = cmd_wr(8'h40); // write 0x40 to 0x094a + init_data[1012] = cmd_start(7'h77); + init_data[1013] = cmd_wr(8'h4e); + init_data[1014] = cmd_wr(8'h49); // write 0x49 to 0x094e + init_data[1015] = cmd_wr(8'h02); // write 0x02 to 0x094f + init_data[1016] = cmd_start(7'h77); + init_data[1017] = cmd_wr(8'h5e); + init_data[1018] = cmd_wr(8'h00); // write 0x00 to 0x095e + init_data[1019] = cmd_start(7'h77); + init_data[1020] = cmd_wr(8'h01); + init_data[1021] = cmd_wr(8'h0a); // set page 0x0a + init_data[1022] = cmd_start(7'h77); + init_data[1023] = cmd_wr(8'h02); + init_data[1024] = cmd_wr(8'h00); // write 0x00 to 0x0a02 + init_data[1025] = cmd_wr(8'h01); // write 0x01 to 0x0a03 + init_data[1026] = cmd_wr(8'h01); // write 0x01 to 0x0a04 + init_data[1027] = cmd_wr(8'h01); // write 0x01 to 0x0a05 + init_data[1028] = cmd_start(7'h77); + init_data[1029] = cmd_wr(8'h14); + init_data[1030] = cmd_wr(8'h00); // write 0x00 to 0x0a14 + init_data[1031] = cmd_start(7'h77); + init_data[1032] = cmd_wr(8'h1a); + init_data[1033] = cmd_wr(8'h00); // write 0x00 to 0x0a1a + init_data[1034] = cmd_start(7'h77); + init_data[1035] = cmd_wr(8'h20); + init_data[1036] = cmd_wr(8'h00); // write 0x00 to 0x0a20 + init_data[1037] = cmd_start(7'h77); + init_data[1038] = cmd_wr(8'h26); + init_data[1039] = cmd_wr(8'h00); // write 0x00 to 0x0a26 + init_data[1040] = cmd_start(7'h77); + init_data[1041] = cmd_wr(8'h2c); + init_data[1042] = cmd_wr(8'h00); // write 0x00 to 0x0a2c + init_data[1043] = cmd_start(7'h77); + init_data[1044] = cmd_wr(8'h01); + init_data[1045] = cmd_wr(8'h0b); // set page 0x0b + init_data[1046] = cmd_start(7'h77); + init_data[1047] = cmd_wr(8'h44); + init_data[1048] = cmd_wr(8'h0f); // write 0x0f to 0x0b44 + init_data[1049] = cmd_start(7'h77); + init_data[1050] = cmd_wr(8'h4a); + init_data[1051] = cmd_wr(8'h1e); // write 0x1e to 0x0b4a + init_data[1052] = cmd_start(7'h77); + init_data[1053] = cmd_wr(8'h57); + init_data[1054] = cmd_wr(8'ha0); // write 0xa0 to 0x0b57 + init_data[1055] = cmd_wr(8'h00); // write 0x00 to 0x0b58 + // End configuration registers + // + // Start configuration postamble + init_data[1056] = cmd_start(7'h77); + init_data[1057] = cmd_wr(8'h01); + init_data[1058] = cmd_wr(8'h00); // set page 0x00 + init_data[1059] = cmd_start(7'h77); + init_data[1060] = cmd_wr(8'h1c); + init_data[1061] = cmd_wr(8'h01); // write 0x01 to 0x001c + init_data[1062] = cmd_start(7'h77); + init_data[1063] = cmd_wr(8'h01); + init_data[1064] = cmd_wr(8'h0b); // set page 0x0b + init_data[1065] = cmd_start(7'h77); + init_data[1066] = cmd_wr(8'h24); + init_data[1067] = cmd_wr(8'hc3); // write 0xc3 to 0x0b24 + init_data[1068] = cmd_wr(8'h02); // write 0x02 to 0x0b25 + // End configuration postamble + init_data[1069] = cmd_halt(); // end +end + +localparam [2:0] + STATE_IDLE = 3'd0, + STATE_RUN = 3'd1, + STATE_TABLE_1 = 3'd2, + STATE_TABLE_2 = 3'd3, + STATE_TABLE_3 = 3'd4; + +logic [2:0] state_reg = STATE_IDLE, state_next; + +localparam AW = $clog2(INIT_DATA_LEN); + +logic [8:0] init_data_reg = '0; + +logic [AW-1:0] address_reg = '0, address_next; +logic [AW-1:0] address_ptr_reg = '0, address_ptr_next; +logic [AW-1:0] data_ptr_reg = '0, data_ptr_next; + +logic [6:0] cur_address_reg = '0, cur_address_next; + +logic [31:0] delay_counter_reg = '0, delay_counter_next; + +logic [6:0] m_axis_cmd_address_reg = '0, m_axis_cmd_address_next; +logic m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next; +logic m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next; +logic m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next; +logic m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next; + +logic [7:0] m_axis_tx_tdata_reg = '0, m_axis_tx_tdata_next; +logic m_axis_tx_tvalid_reg = 1'b0, m_axis_tx_tvalid_next; + +logic start_flag_reg = 1'b0, start_flag_next; + +logic busy_reg = 1'b0; + +assign m_axis_cmd.tdata[6:0] = m_axis_cmd_address_reg; +assign m_axis_cmd.tdata[7] = m_axis_cmd_start_reg; +assign m_axis_cmd.tdata[8] = 1'b0; // read +assign m_axis_cmd.tdata[9] = m_axis_cmd_write_reg; +assign m_axis_cmd.tdata[10] = 1'b0; // write multi +assign m_axis_cmd.tdata[11] = m_axis_cmd_stop_reg; +assign m_axis_cmd.tvalid = m_axis_cmd_valid_reg; +assign m_axis_cmd.tlast = 1'b1; +assign m_axis_cmd.tid = '0; +assign m_axis_cmd.tdest = '0; +assign m_axis_cmd.tuser = '0; + +assign m_axis_tx.tdata = m_axis_tx_tdata_reg; +assign m_axis_tx.tvalid = m_axis_tx_tvalid_reg; +assign m_axis_tx.tlast = 1'b1; +assign m_axis_tx.tid = '0; +assign m_axis_tx.tdest = '0; +assign m_axis_tx.tuser = '0; + +assign busy = busy_reg; + +always_comb begin + state_next = STATE_IDLE; + + address_next = address_reg; + address_ptr_next = address_ptr_reg; + data_ptr_next = data_ptr_reg; + + cur_address_next = cur_address_reg; + + delay_counter_next = delay_counter_reg; + + m_axis_cmd_address_next = m_axis_cmd_address_reg; + m_axis_cmd_start_next = m_axis_cmd_start_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready); + m_axis_cmd_write_next = m_axis_cmd_write_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready); + m_axis_cmd_stop_next = m_axis_cmd_stop_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready); + m_axis_cmd_valid_next = m_axis_cmd_valid_reg && !m_axis_cmd.tready; + + m_axis_tx_tdata_next = m_axis_tx_tdata_reg; + m_axis_tx_tvalid_next = m_axis_tx_tvalid_reg && !m_axis_tx.tready; + + start_flag_next = start_flag_reg; + + if (m_axis_cmd.tvalid || m_axis_tx.tvalid) begin + // wait for output registers to clear + state_next = state_reg; + end else if (delay_counter_reg != 0) begin + // delay + delay_counter_next = delay_counter_reg - 1; + state_next = state_reg; + end else begin + case (state_reg) + STATE_IDLE: begin + // wait for start signal + if (!start_flag_reg && start) begin + address_next = '0; + start_flag_next = 1'b1; + state_next = STATE_RUN; + end else begin + state_next = STATE_IDLE; + end + end + STATE_RUN: begin + // process commands + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_tx_tdata_next = init_data_reg[7:0]; + m_axis_tx_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:4] == 5'b00001) begin + // delay + if (SIM_SPEEDUP) begin + delay_counter_next = 32'd1 << (init_data_reg[3:0]); + end else begin + delay_counter_next = 32'd1 << (init_data_reg[3:0]+16); + end + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_RUN; + end + end + STATE_TABLE_1: begin + // find address table start + if (init_data_reg == 9'b000001000) begin + // address table start + address_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end + end + STATE_TABLE_2: begin + // find next address + if (init_data_reg[8:7] == 2'b01) begin + // write address command + // store address and move to data table + cur_address_next = init_data_reg[6:0]; + address_ptr_next = address_reg + 1; + address_next = data_ptr_reg; + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end + end + STATE_TABLE_3: begin + // process data table with selected address + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_tx_tdata_next = init_data_reg[7:0]; + m_axis_tx_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000000011) begin + // write current address + m_axis_cmd_address_next = cur_address_reg; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg[8:4] == 5'b00001) begin + // delay + if (SIM_SPEEDUP) begin + delay_counter_next = 32'd1 << (init_data_reg[3:0]); + end else begin + delay_counter_next = 32'd1 << (init_data_reg[3:0]+16); + end + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'b000001000) begin + // address table start + address_next = address_ptr_reg; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_3; + end + end + default: begin + // invalid state + state_next = STATE_IDLE; + end + endcase + end +end + +always_ff @(posedge clk) begin + state_reg <= state_next; + + // read init_data ROM + init_data_reg <= init_data[address_next]; + + address_reg <= address_next; + address_ptr_reg <= address_ptr_next; + data_ptr_reg <= data_ptr_next; + + cur_address_reg <= cur_address_next; + + delay_counter_reg <= delay_counter_next; + + m_axis_cmd_address_reg <= m_axis_cmd_address_next; + m_axis_cmd_start_reg <= m_axis_cmd_start_next; + m_axis_cmd_write_reg <= m_axis_cmd_write_next; + m_axis_cmd_stop_reg <= m_axis_cmd_stop_next; + m_axis_cmd_valid_reg <= m_axis_cmd_valid_next; + + m_axis_tx_tdata_reg <= m_axis_tx_tdata_next; + m_axis_tx_tvalid_reg <= m_axis_tx_tvalid_next; + + start_flag_reg <= start && start_flag_next; + + busy_reg <= (state_reg != STATE_IDLE); + + if (rst) begin + state_reg <= STATE_IDLE; + + init_data_reg <= '0; + + address_reg <= '0; + address_ptr_reg <= '0; + data_ptr_reg <= '0; + + cur_address_reg <= '0; + + delay_counter_reg <= '0; + + m_axis_cmd_valid_reg <= 1'b0; + + m_axis_tx_tvalid_reg <= 1'b0; + + start_flag_reg <= 1'b0; + + busy_reg <= 1'b0; + end +end + +endmodule + +`resetall \ No newline at end of file diff --git a/src/eth/example/HTG9200/fpga/rtl/fpga_6qsfp.sv b/src/eth/example/HTG9200/fpga/rtl/fpga_6qsfp.sv new file mode 100644 index 0000000..223a7db --- /dev/null +++ b/src/eth/example/HTG9200/fpga/rtl/fpga_6qsfp.sv @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga # +( + parameter logic SIM = 1'b0, + parameter string VENDOR = "XILINX", + parameter string FAMILY = "virtexuplus" +) +( + /* + * Clock: 200 MHz LVDS + */ + input wire logic ref_clk_p, + input wire logic ref_clk_n, + + /* + * GPIO + */ + input wire logic [1:0] btn, + input wire logic [7:0] sw, + output wire logic [7:0] led, + + /* + * I2C for board management + */ + inout wire logic i2c_main_scl, + inout wire logic i2c_main_sda, + output wire logic i2c_main_rst_n, + + /* + * PLL + */ + output wire logic clk_gty2_fdec, + output wire logic clk_gty2_finc, + input wire logic clk_gty2_intr_n, + input wire logic clk_gty2_lol_n, + output wire logic clk_gty2_oe_n, + output wire logic clk_gty2_sync_n, + output wire logic clk_gty2_rst_n, + + /* + * UART: 921600 bps, 8N1 + */ + output wire logic uart_rxd, + input wire logic uart_txd, + input wire logic uart_rts, + output wire logic uart_cts, + output wire logic uart_rst_n, + output wire logic uart_suspend_n, + + /* + * Ethernet: QSFP28 + */ + output wire logic [3:0] qsfp_1_tx_p, + output wire logic [3:0] qsfp_1_tx_n, + input wire logic [3:0] qsfp_1_rx_p, + input wire logic [3:0] qsfp_1_rx_n, + input wire logic qsfp_1_mgt_refclk_p, + input wire logic qsfp_1_mgt_refclk_n, + output wire logic qsfp_1_resetl, + input wire logic qsfp_1_modprsl, + input wire logic qsfp_1_intl, + + output wire logic [3:0] qsfp_2_tx_p, + output wire logic [3:0] qsfp_2_tx_n, + input wire logic [3:0] qsfp_2_rx_p, + input wire logic [3:0] qsfp_2_rx_n, + input wire logic qsfp_2_mgt_refclk_p, + input wire logic qsfp_2_mgt_refclk_n, + output wire logic qsfp_2_resetl, + input wire logic qsfp_2_modprsl, + input wire logic qsfp_2_intl, + + output wire logic [3:0] qsfp_3_tx_p, + output wire logic [3:0] qsfp_3_tx_n, + input wire logic [3:0] qsfp_3_rx_p, + input wire logic [3:0] qsfp_3_rx_n, + input wire logic qsfp_3_mgt_refclk_p, + input wire logic qsfp_3_mgt_refclk_n, + output wire logic qsfp_3_resetl, + input wire logic qsfp_3_modprsl, + input wire logic qsfp_3_intl, + + output wire logic [3:0] qsfp_4_tx_p, + output wire logic [3:0] qsfp_4_tx_n, + input wire logic [3:0] qsfp_4_rx_p, + input wire logic [3:0] qsfp_4_rx_n, + input wire logic qsfp_4_mgt_refclk_p, + input wire logic qsfp_4_mgt_refclk_n, + output wire logic qsfp_4_resetl, + input wire logic qsfp_4_modprsl, + input wire logic qsfp_4_intl, + + output wire logic [3:0] qsfp_5_tx_p, + output wire logic [3:0] qsfp_5_tx_n, + input wire logic [3:0] qsfp_5_rx_p, + input wire logic [3:0] qsfp_5_rx_n, + input wire logic qsfp_5_mgt_refclk_p, + input wire logic qsfp_5_mgt_refclk_n, + output wire logic qsfp_5_resetl, + input wire logic qsfp_5_modprsl, + input wire logic qsfp_5_intl, + + output wire logic [3:0] qsfp_6_tx_p, + output wire logic [3:0] qsfp_6_tx_n, + input wire logic [3:0] qsfp_6_rx_p, + input wire logic [3:0] qsfp_6_rx_n, + input wire logic qsfp_6_mgt_refclk_p, + input wire logic qsfp_6_mgt_refclk_n, + output wire logic qsfp_6_resetl, + input wire logic qsfp_6_modprsl, + input wire logic qsfp_6_intl, + + output wire logic [3:0] qsfp_7_tx_p, + output wire logic [3:0] qsfp_7_tx_n, + input wire logic [3:0] qsfp_7_rx_p, + input wire logic [3:0] qsfp_7_rx_n, + input wire logic qsfp_7_mgt_refclk_p, + input wire logic qsfp_7_mgt_refclk_n, + output wire logic qsfp_7_resetl, + input wire logic qsfp_7_modprsl, + input wire logic qsfp_7_intl, + + output wire logic [3:0] qsfp_8_tx_p, + output wire logic [3:0] qsfp_8_tx_n, + input wire logic [3:0] qsfp_8_rx_p, + input wire logic [3:0] qsfp_8_rx_n, + input wire logic qsfp_8_mgt_refclk_p, + input wire logic qsfp_8_mgt_refclk_n, + output wire logic qsfp_8_resetl, + input wire logic qsfp_8_modprsl, + input wire logic qsfp_8_intl, + + output wire logic [3:0] qsfp_9_tx_p, + output wire logic [3:0] qsfp_9_tx_n, + input wire logic [3:0] qsfp_9_rx_p, + input wire logic [3:0] qsfp_9_rx_n, + input wire logic qsfp_9_mgt_refclk_p, + input wire logic qsfp_9_mgt_refclk_n, + output wire logic qsfp_9_resetl, + input wire logic qsfp_9_modprsl, + input wire logic qsfp_9_intl, + + /* + * Ethernet: QSFP28 via HTG 6x QSFP28 FMC+ adapter + */ + output wire logic [3:0] fmc_qsfp_1_tx_p, + output wire logic [3:0] fmc_qsfp_1_tx_n, + input wire logic [3:0] fmc_qsfp_1_rx_p, + input wire logic [3:0] fmc_qsfp_1_rx_n, + input wire logic fmc_qsfp_1_mgt_refclk_p, + input wire logic fmc_qsfp_1_mgt_refclk_n, + output wire logic fmc_qsfp_1_modsell, + output wire logic fmc_qsfp_1_resetl, + input wire logic fmc_qsfp_1_modprsl, + input wire logic fmc_qsfp_1_intl, + output wire logic fmc_qsfp_1_lpmode, + + output wire logic [3:0] fmc_qsfp_2_tx_p, + output wire logic [3:0] fmc_qsfp_2_tx_n, + input wire logic [3:0] fmc_qsfp_2_rx_p, + input wire logic [3:0] fmc_qsfp_2_rx_n, + input wire logic fmc_qsfp_2_mgt_refclk_p, + input wire logic fmc_qsfp_2_mgt_refclk_n, + output wire logic fmc_qsfp_2_modsell, + output wire logic fmc_qsfp_2_resetl, + input wire logic fmc_qsfp_2_modprsl, + input wire logic fmc_qsfp_2_intl, + output wire logic fmc_qsfp_2_lpmode, + + output wire logic [3:0] fmc_qsfp_3_tx_p, + output wire logic [3:0] fmc_qsfp_3_tx_n, + input wire logic [3:0] fmc_qsfp_3_rx_p, + input wire logic [3:0] fmc_qsfp_3_rx_n, + input wire logic fmc_qsfp_3_mgt_refclk_p, + input wire logic fmc_qsfp_3_mgt_refclk_n, + output wire logic fmc_qsfp_3_modsell, + output wire logic fmc_qsfp_3_resetl, + input wire logic fmc_qsfp_3_modprsl, + input wire logic fmc_qsfp_3_intl, + output wire logic fmc_qsfp_3_lpmode, + + output wire logic [3:0] fmc_qsfp_4_tx_p, + output wire logic [3:0] fmc_qsfp_4_tx_n, + input wire logic [3:0] fmc_qsfp_4_rx_p, + input wire logic [3:0] fmc_qsfp_4_rx_n, + input wire logic fmc_qsfp_4_mgt_refclk_p, + input wire logic fmc_qsfp_4_mgt_refclk_n, + output wire logic fmc_qsfp_4_modsell, + output wire logic fmc_qsfp_4_resetl, + input wire logic fmc_qsfp_4_modprsl, + input wire logic fmc_qsfp_4_intl, + output wire logic fmc_qsfp_4_lpmode, + + output wire logic [3:0] fmc_qsfp_5_tx_p, + output wire logic [3:0] fmc_qsfp_5_tx_n, + input wire logic [3:0] fmc_qsfp_5_rx_p, + input wire logic [3:0] fmc_qsfp_5_rx_n, + input wire logic fmc_qsfp_5_mgt_refclk_p, + input wire logic fmc_qsfp_5_mgt_refclk_n, + output wire logic fmc_qsfp_5_modsell, + output wire logic fmc_qsfp_5_resetl, + input wire logic fmc_qsfp_5_modprsl, + input wire logic fmc_qsfp_5_intl, + output wire logic fmc_qsfp_5_lpmode, + + output wire logic [3:0] fmc_qsfp_6_tx_p, + output wire logic [3:0] fmc_qsfp_6_tx_n, + input wire logic [3:0] fmc_qsfp_6_rx_p, + input wire logic [3:0] fmc_qsfp_6_rx_n, + input wire logic fmc_qsfp_6_mgt_refclk_p, + input wire logic fmc_qsfp_6_mgt_refclk_n, + output wire logic fmc_qsfp_6_modsell, + output wire logic fmc_qsfp_6_resetl, + input wire logic fmc_qsfp_6_modprsl, + input wire logic fmc_qsfp_6_intl, + output wire logic fmc_qsfp_6_lpmode, + + output wire logic fmc_clk_finc, + output wire logic fmc_clk_fdec, + output wire logic fmc_clk_rst_n, + input wire logic fmc_clk_lol_n, + output wire logic fmc_clk_sync_n, + input wire logic fmc_clk_intr_n, + + output wire logic fmc_sync_c2m_p, + output wire logic fmc_sync_c2m_n +); + +// Clock and reset + +wire ref_clk_ibufg; + +// Internal 125 MHz clock +wire clk_125mhz_mmcm_out; +wire clk_125mhz_int; +wire rst_125mhz_int; + +wire mmcm_rst = ~btn[0]; +wire mmcm_locked; +wire mmcm_clkfb; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +ref_clk_ibufg_inst ( + .O (ref_clk_ibufg), + .I (ref_clk_p), + .IB (ref_clk_n) +); + +// MMCM instance +MMCME4_BASE #( + // 200 MHz input + .CLKIN1_PERIOD(5.0), + .REF_JITTER1(0.010), + // 200 MHz input / 1 = 200 MHz PFD (range 10 MHz to 500 MHz) + .DIVCLK_DIVIDE(1), + // 200 MHz PFD * 5 = 1000 MHz VCO (range 800 MHz to 1600 MHz) + .CLKFBOUT_MULT_F(5), + .CLKFBOUT_PHASE(0), + // 1000 MHz / 8 = 125 MHz, 0 degrees + .CLKOUT0_DIVIDE_F(8), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + // Not used + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + // Not used + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + // Not used + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + // Not used + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT4_CASCADE("FALSE"), + // Not used + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + // Not used + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + + // optimized bandwidth + .BANDWIDTH("OPTIMIZED"), + // don't wait for lock during startup + .STARTUP_WAIT("FALSE") +) +clk_mmcm_inst ( + // 200 MHz input + .CLKIN1(ref_clk_ibufg), + // direct clkfb feeback + .CLKFBIN(mmcm_clkfb), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + // 125 MHz, 0 degrees + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + // Not used + .CLKOUT1(), + .CLKOUT1B(), + // Not used + .CLKOUT2(), + .CLKOUT2B(), + // Not used + .CLKOUT3(), + .CLKOUT3B(), + // Not used + .CLKOUT4(), + // Not used + .CLKOUT5(), + // Not used + .CLKOUT6(), + // reset input + .RST(mmcm_rst), + // don't power down + .PWRDWN(1'b0), + // locked output + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +taxi_sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +// GPIO +wire btn_int; +wire [7:0] sw_int; + +taxi_debounce_switch #( + .WIDTH(9), + .N(4), + .RATE(125000) +) +debounce_switch_inst ( + .clk(clk_125mhz_int), + .rst(rst_125mhz_int), + .in({btn[1], + sw}), + .out({btn_int, + sw_int}) +); + +wire uart_txd_int; +wire uart_rts_int; + +taxi_sync_signal #( + .WIDTH(2), + .N(2) +) +sync_signal_inst ( + .clk(clk_125mhz_int), + .in({uart_txd, uart_rts}), + .out({uart_txd_int, uart_rts_int}) +); + +wire i2c_scl_i; +wire i2c_scl_o; +wire i2c_sda_i; +wire i2c_sda_o; + +assign i2c_scl_i = i2c_main_scl; +assign i2c_main_scl = i2c_scl_o ? 1'bz : 1'b0; +assign i2c_sda_i = i2c_main_sda; +assign i2c_main_sda = i2c_sda_o ? 1'bz : 1'b0; +assign i2c_main_rst_n = 1'b1; + +localparam PORT_CNT = 9+6; +localparam GTY_QUAD_CNT = PORT_CNT; +localparam GTY_CNT = GTY_QUAD_CNT*4; +localparam GTY_CLK_CNT = GTY_QUAD_CNT; + +assign clk_gty2_fdec = 1'b0; +assign clk_gty2_finc = 1'b0; +assign clk_gty2_oe_n = 1'b0; +assign clk_gty2_sync_n = 1'b1; +assign clk_gty2_rst_n = !rst_125mhz_int; + +wire [PORT_CNT-1:0] eth_gty_mgt_refclk_out; + +// forward MGT ref clock to PLL on FMC+ board +OBUFDS obufds_fmc_refclk_inst ( + .I(eth_gty_mgt_refclk_out[0]), + .O(fmc_sync_c2m_p), + .OB(fmc_sync_c2m_n) +); + +assign fmc_qsfp_1_lpmode = 1'b0; +assign fmc_qsfp_2_lpmode = 1'b0; +assign fmc_qsfp_3_lpmode = 1'b0; +assign fmc_qsfp_4_lpmode = 1'b0; +assign fmc_qsfp_5_lpmode = 1'b0; +assign fmc_qsfp_6_lpmode = 1'b0; + +assign fmc_clk_finc = 1'b0; +assign fmc_clk_fdec = 1'b0; +assign fmc_clk_sync_n = 1'b1; +assign fmc_clk_rst_n = !rst_125mhz_int; + +wire eth_pll_locked = clk_gty2_lol_n && fmc_clk_lol_n; + +fpga_core #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + .PORT_CNT(PORT_CNT), + .GTY_QUAD_CNT(GTY_QUAD_CNT), + .GTY_CNT(GTY_CNT), + .GTY_CLK_CNT(GTY_CLK_CNT) +) +core_inst ( + /* + * Clock: 125MHz + * Synchronous reset + */ + .clk_125mhz(clk_125mhz_int), + .rst_125mhz(rst_125mhz_int), + + /* + * GPIO + */ + .btn(btn_int), + .sw(sw_int), + .led(led), + + /* + * I2C for board management + */ + .i2c_scl_i(i2c_scl_i), + .i2c_scl_o(i2c_scl_o), + .i2c_sda_i(i2c_sda_i), + .i2c_sda_o(i2c_sda_o), + + /* + * UART: 921600 bps, 8N1 + */ + .uart_rxd(uart_rxd), + .uart_txd(uart_txd_int), + .uart_rts(uart_rts_int), + .uart_cts(uart_cts), + .uart_rst_n(uart_rst_n), + .uart_suspend_n(uart_suspend_n), + + /* + * Ethernet: QSFP28 + */ + .eth_pll_locked(eth_pll_locked), + + .eth_gty_tx_p({fmc_qsfp_6_tx_p, fmc_qsfp_5_tx_p, fmc_qsfp_4_tx_p, fmc_qsfp_3_tx_p, fmc_qsfp_2_tx_p, fmc_qsfp_1_tx_p, qsfp_9_tx_p, qsfp_8_tx_p, qsfp_7_tx_p, qsfp_6_tx_p, qsfp_5_tx_p, qsfp_4_tx_p, qsfp_3_tx_p, qsfp_2_tx_p, qsfp_1_tx_p}), + .eth_gty_tx_n({fmc_qsfp_6_tx_n, fmc_qsfp_5_tx_n, fmc_qsfp_4_tx_n, fmc_qsfp_3_tx_n, fmc_qsfp_2_tx_n, fmc_qsfp_1_tx_n, qsfp_9_tx_n, qsfp_8_tx_n, qsfp_7_tx_n, qsfp_6_tx_n, qsfp_5_tx_n, qsfp_4_tx_n, qsfp_3_tx_n, qsfp_2_tx_n, qsfp_1_tx_n}), + .eth_gty_rx_p({fmc_qsfp_6_rx_p, fmc_qsfp_5_rx_p, fmc_qsfp_4_rx_p, fmc_qsfp_3_rx_p, fmc_qsfp_2_rx_p, fmc_qsfp_1_rx_p, qsfp_9_rx_p, qsfp_8_rx_p, qsfp_7_rx_p, qsfp_6_rx_p, qsfp_5_rx_p, qsfp_4_rx_p, qsfp_3_rx_p, qsfp_2_rx_p, qsfp_1_rx_p}), + .eth_gty_rx_n({fmc_qsfp_6_rx_n, fmc_qsfp_5_rx_n, fmc_qsfp_4_rx_n, fmc_qsfp_3_rx_n, fmc_qsfp_2_rx_n, fmc_qsfp_1_rx_n, qsfp_9_rx_n, qsfp_8_rx_n, qsfp_7_rx_n, qsfp_6_rx_n, qsfp_5_rx_n, qsfp_4_rx_n, qsfp_3_rx_n, qsfp_2_rx_n, qsfp_1_rx_n}), + .eth_gty_mgt_refclk_p({fmc_qsfp_6_mgt_refclk_p, fmc_qsfp_5_mgt_refclk_p, fmc_qsfp_4_mgt_refclk_p, fmc_qsfp_3_mgt_refclk_p, fmc_qsfp_2_mgt_refclk_p, fmc_qsfp_1_mgt_refclk_p, qsfp_9_mgt_refclk_p, qsfp_8_mgt_refclk_p, qsfp_7_mgt_refclk_p, qsfp_6_mgt_refclk_p, qsfp_5_mgt_refclk_p, qsfp_4_mgt_refclk_p, qsfp_3_mgt_refclk_p, qsfp_2_mgt_refclk_p, qsfp_1_mgt_refclk_p}), + .eth_gty_mgt_refclk_n({fmc_qsfp_6_mgt_refclk_n, fmc_qsfp_5_mgt_refclk_n, fmc_qsfp_4_mgt_refclk_n, fmc_qsfp_3_mgt_refclk_n, fmc_qsfp_2_mgt_refclk_n, fmc_qsfp_1_mgt_refclk_n, qsfp_9_mgt_refclk_n, qsfp_8_mgt_refclk_n, qsfp_7_mgt_refclk_n, qsfp_6_mgt_refclk_n, qsfp_5_mgt_refclk_n, qsfp_4_mgt_refclk_n, qsfp_3_mgt_refclk_n, qsfp_2_mgt_refclk_n, qsfp_1_mgt_refclk_n}), + .eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out), + + .eth_port_resetl({fmc_qsfp_6_resetl, fmc_qsfp_5_resetl, fmc_qsfp_4_resetl, fmc_qsfp_3_resetl, fmc_qsfp_2_resetl, fmc_qsfp_1_resetl, qsfp_9_resetl, qsfp_8_resetl, qsfp_7_resetl, qsfp_6_resetl, qsfp_5_resetl, qsfp_4_resetl, qsfp_3_resetl, qsfp_2_resetl, qsfp_1_resetl}), + .eth_port_modprsl({fmc_qsfp_6_modprsl, fmc_qsfp_5_modprsl, fmc_qsfp_4_modprsl, fmc_qsfp_3_modprsl, fmc_qsfp_2_modprsl, fmc_qsfp_1_modprsl, qsfp_9_modprsl, qsfp_8_modprsl, qsfp_7_modprsl, qsfp_6_modprsl, qsfp_5_modprsl, qsfp_4_modprsl, qsfp_3_modprsl, qsfp_2_modprsl, qsfp_1_modprsl}), + .eth_port_intl({fmc_qsfp_6_intl, fmc_qsfp_5_intl, fmc_qsfp_4_intl, fmc_qsfp_3_intl, fmc_qsfp_2_intl, fmc_qsfp_1_intl, qsfp_9_intl, qsfp_8_intl, qsfp_7_intl, qsfp_6_intl, qsfp_5_intl, qsfp_4_intl, qsfp_3_intl, qsfp_2_intl, qsfp_1_intl}) +); + +endmodule + +`resetall diff --git a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv index fc4b1b4..02a3ca7 100644 --- a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv +++ b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv @@ -361,6 +361,12 @@ localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP6[4] = '{"QSFP6.1", "QSFP6.2", "Q localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP7[4] = '{"QSFP7.1", "QSFP7.2", "QSFP7.3", "QSFP7.4"}; localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP8[4] = '{"QSFP8.1", "QSFP8.2", "QSFP8.3", "QSFP8.4"}; localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP9[4] = '{"QSFP9.1", "QSFP9.2", "QSFP9.3", "QSFP9.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP10[4] = '{"QSFP10.1", "QSFP10.2", "QSFP10.3", "QSFP10.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP11[4] = '{"QSFP11.1", "QSFP11.2", "QSFP11.3", "QSFP11.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP12[4] = '{"QSFP12.1", "QSFP12.2", "QSFP12.3", "QSFP12.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP13[4] = '{"QSFP13.1", "QSFP13.2", "QSFP13.3", "QSFP13.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP14[4] = '{"QSFP14.1", "QSFP14.2", "QSFP14.3", "QSFP14.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP15[4] = '{"QSFP15.1", "QSFP15.2", "QSFP15.3", "QSFP15.4"}; for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad @@ -406,7 +412,13 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad n == 5 ? STAT_PREFIX_STR_QSFP6 : n == 6 ? STAT_PREFIX_STR_QSFP7 : n == 7 ? STAT_PREFIX_STR_QSFP8 : - STAT_PREFIX_STR_QSFP9 + n == 8 ? STAT_PREFIX_STR_QSFP9 : + n == 9 ? STAT_PREFIX_STR_QSFP10 : + n == 10 ? STAT_PREFIX_STR_QSFP11 : + n == 11 ? STAT_PREFIX_STR_QSFP12 : + n == 12 ? STAT_PREFIX_STR_QSFP13 : + n == 13 ? STAT_PREFIX_STR_QSFP14 : + STAT_PREFIX_STR_QSFP15 ) ) mac_inst (