From 4c43b68f949e09ced76a5f1fcfa10d56ea81cfc8 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 20 Aug 2025 16:24:39 -0700 Subject: [PATCH] eth: Add 6QSFP FMC support to HTG9200 example design Signed-off-by: Alex Forencich --- src/eth/example/HTG9200/fpga/README.md | 4 +- src/eth/example/HTG9200/fpga/fmc_6qsfp.xdc | 326 ++++ .../HTG9200/fpga/fpga_10g_6q_vu13p/Makefile | 94 + .../HTG9200/fpga/fpga_10g_6q_vu9p/Makefile | 94 + .../HTG9200/fpga/fpga_6q_vu13p/Makefile | 94 + .../HTG9200/fpga/fpga_6q_vu9p/Makefile | 94 + ...0_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt | 412 +++++ ...00_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj | Bin 0 -> 10144 bytes .../HTG9200/fpga/pll/si5341_i2c_init.py | 13 +- .../HTG9200/fpga/pll/si5341_i2c_init_6qsfp.sv | 1647 +++++++++++++++++ .../example/HTG9200/fpga/rtl/fpga_6qsfp.sv | 499 +++++ src/eth/example/HTG9200/fpga/rtl/fpga_core.sv | 14 +- 12 files changed, 3288 insertions(+), 3 deletions(-) create mode 100644 src/eth/example/HTG9200/fpga/fmc_6qsfp.xdc create mode 100644 src/eth/example/HTG9200/fpga/fpga_10g_6q_vu13p/Makefile create mode 100644 src/eth/example/HTG9200/fpga/fpga_10g_6q_vu9p/Makefile create mode 100644 src/eth/example/HTG9200/fpga/fpga_6q_vu13p/Makefile create mode 100644 src/eth/example/HTG9200/fpga/fpga_6q_vu9p/Makefile create mode 100644 src/eth/example/HTG9200/fpga/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt create mode 100644 src/eth/example/HTG9200/fpga/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj create mode 100644 src/eth/example/HTG9200/fpga/pll/si5341_i2c_init_6qsfp.sv create mode 100644 src/eth/example/HTG9200/fpga/rtl/fpga_6qsfp.sv diff --git a/src/eth/example/HTG9200/fpga/README.md b/src/eth/example/HTG9200/fpga/README.md index 93fc0d8..02a65da 100644 --- a/src/eth/example/HTG9200/fpga/README.md +++ b/src/eth/example/HTG9200/fpga/README.md @@ -2,7 +2,7 @@ ## Introduction -This example design targets the HiTech Global HTG-9200 FPGA board. +This example design targets the HiTech Global HTG-9200 FPGA board. Design variants are provided for both the bare HTG-9200, as well as the HTG-9200 with the HiTech Global HTG-FMC-X6QSFP28 FMC+ board installed on J9. The design places looped-back MACs on the Ethernet ports, as well as XFCP on the USB UART for monitoring and control. @@ -63,4 +63,6 @@ The table below contains the power rail test points and feedback resistor values Run `make program` to program the board with Vivado. +LED D46 on the HTG-9200 indicates that the Si5341 PLL is locked and providing stable reference clocks to the transceivers. On the HTG-FMC-X6QSFP28 FMC+ board, LED D10 indicates that the Si5341 PLL is locked. + To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. diff --git a/src/eth/example/HTG9200/fpga/fmc_6qsfp.xdc b/src/eth/example/HTG9200/fpga/fmc_6qsfp.xdc new file mode 100644 index 0000000..989ffb9 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fmc_6qsfp.xdc @@ -0,0 +1,326 @@ +# XDC constraints for the HiTech Global HTG-9200 board with HTG-FMC-X6QSFP28 FMC+ +# part: xcvu9p-flgb2104-2-e +# part: xcvu13p-fhgb2104-2-e + +# FMC+ J9 +set_property -dict {LOC BA15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_lpmode] ;# J9.G9 LA00_P_CC +set_property -dict {LOC BA14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_resetl] ;# J9.G10 LA00_N_CC +set_property -dict {LOC AY13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_modprsl] ;# J9.D8 LA01_P_CC +set_property -dict {LOC BA13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_intl] ;# J9.D9 LA01_N_CC +set_property -dict {LOC AL15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_modsell] ;# J9.H7 LA02_P +set_property -dict {LOC AM15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_modprsl] ;# J9.H8 LA02_N +set_property -dict {LOC AN14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_intl] ;# J9.G12 LA03_P +set_property -dict {LOC AN13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_modsell] ;# J9.G13 LA03_N +set_property -dict {LOC AL14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_lpmode] ;# J9.H10 LA04_P +set_property -dict {LOC AM14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_resetl] ;# J9.H11 LA04_N +set_property -dict {LOC AP13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_modsell] ;# J9.D11 LA05_P +set_property -dict {LOC AR13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_intl] ;# J9.D12 LA05_N +set_property -dict {LOC AP15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_resetl] ;# J9.C10 LA06_P +set_property -dict {LOC AP14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_lpmode] ;# J9.C11 LA06_N +set_property -dict {LOC AU16 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_modprsl] ;# J9.H13 LA07_P +set_property -dict {LOC AV16 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_modsell] ;# J9.H14 LA07_N +set_property -dict {LOC AR16 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_lpmode] ;# J9.G12 LA08_P +set_property -dict {LOC AR15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_intl] ;# J9.G13 LA08_N +set_property -dict {LOC AT15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_modprsl] ;# J9.D14 LA09_P +set_property -dict {LOC AU15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_modsell] ;# J9.D15 LA09_N +set_property -dict {LOC AU14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_resetl] ;# J9.C14 LA10_P +set_property -dict {LOC AV14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_lpmode] ;# J9.C15 LA10_N +set_property -dict {LOC BD15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_intl] ;# J9.H16 LA11_P +set_property -dict {LOC BD14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_modprsl] ;# J9.H17 LA11_N +set_property -dict {LOC AY12 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_resetl] ;# J9.G15 LA12_P +set_property -dict {LOC AY11 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_lpmode] ;# J9.G16 LA12_N +set_property -dict {LOC BA12 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_intl] ;# J9.D17 LA13_P +set_property -dict {LOC BB12 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_modprsl] ;# J9.D18 LA13_N +set_property -dict {LOC BB15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_modsell] ;# J9.C18 LA14_P +set_property -dict {LOC BB14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_resetl] ;# J9.C19 LA14_N +set_property -dict {LOC BF14 IOSTANDARD LVCMOS18} [get_ports fmc_clk_finc] ;# J9.H19 LA15_P +set_property -dict {LOC BF13 IOSTANDARD LVCMOS18} [get_ports fmc_clk_fdec] ;# J9.H20 LA15_N +set_property -dict {LOC BD16 IOSTANDARD LVCMOS18} [get_ports fmc_clk_rst_n] ;# J9.G18 LA16_P +set_property -dict {LOC BE16 IOSTANDARD LVCMOS18} [get_ports fmc_clk_lol_n] ;# J9.G19 LA16_N +set_property -dict {LOC AT20 IOSTANDARD LVCMOS18} [get_ports fmc_clk_sync_n] ;# J9.D20 LA17_P_CC +set_property -dict {LOC AU20 IOSTANDARD LVCMOS18} [get_ports fmc_clk_intr_n] ;# J9.D21 LA17_N_CC +#set_property -dict {LOC AV19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[18]}] ;# J9.C22 LA18_P_CC +#set_property -dict {LOC AW19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[18]}] ;# J9.C23 LA18_N_CC +#set_property -dict {LOC AR17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[19]}] ;# J9.H22 LA19_P +#set_property -dict {LOC AT17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[19]}] ;# J9.H23 LA19_N +#set_property -dict {LOC AN18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[20]}] ;# J9.G21 LA20_P +#set_property -dict {LOC AN17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[20]}] ;# J9.G22 LA20_N +#set_property -dict {LOC AW20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[21]}] ;# J9.H25 LA21_P +#set_property -dict {LOC AY20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[21]}] ;# J9.H26 LA21_N +#set_property -dict {LOC AT19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[22]}] ;# J9.G24 LA22_P +#set_property -dict {LOC AU19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[22]}] ;# J9.G25 LA22_N +#set_property -dict {LOC AL17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[23]}] ;# J9.D23 LA23_P +#set_property -dict {LOC AM17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[23]}] ;# J9.D24 LA23_N +#set_property -dict {LOC AY17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[24]}] ;# J9.H28 LA24_P +#set_property -dict {LOC BA17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[24]}] ;# J9.H29 LA24_N +#set_property -dict {LOC AY18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[25]}] ;# J9.G27 LA25_P +#set_property -dict {LOC BA18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[25]}] ;# J9.G28 LA25_N +#set_property -dict {LOC AP20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[26]}] ;# J9.D26 LA26_P +#set_property -dict {LOC AP20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[26]}] ;# J9.D27 LA26_N +#set_property -dict {LOC AN19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[27]}] ;# J9.C26 LA27_P +#set_property -dict {LOC AP19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[27]}] ;# J9.C27 LA27_N +#set_property -dict {LOC BB17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[28]}] ;# J9.H31 LA28_P +#set_property -dict {LOC BC17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[28]}] ;# J9.H32 LA28_N +#set_property -dict {LOC BB19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[29]}] ;# J9.G30 LA29_P +#set_property -dict {LOC BC18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[29]}] ;# J9.G31 LA29_N +#set_property -dict {LOC BD18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[30]}] ;# J9.H34 LA30_P +#set_property -dict {LOC BE18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[30]}] ;# J9.H35 LA30_N +#set_property -dict {LOC BC19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[31]}] ;# J9.G33 LA31_P +#set_property -dict {LOC BD19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[31]}] ;# J9.G34 LA31_N +#set_property -dict {LOC BF19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[32]}] ;# J9.H37 LA32_P +#set_property -dict {LOC BF18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[32]}] ;# J9.H38 LA32_N +#set_property -dict {LOC BE17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[33]}] ;# J9.G36 LA33_P +#set_property -dict {LOC BF17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[33]}] ;# J9.G37 LA33_N + +#set_property -dict {LOC G14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[0]}] ;# J9.F4 HA00_P_CC +#set_property -dict {LOC F14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[0]}] ;# J9.F5 HA00_N_CC +#set_property -dict {LOC G15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[1]}] ;# J9.E2 HA01_P_CC +#set_property -dict {LOC F15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[1]}] ;# J9.E3 HA01_N_CC +#set_property -dict {LOC A14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[2]}] ;# J9.K7 HA02_P +#set_property -dict {LOC A13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[2]}] ;# J9.K8 HA02_N +#set_property -dict {LOC B17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[3]}] ;# J9.J6 HA03_P +#set_property -dict {LOC A17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[3]}] ;# J9.J7 HA03_N +#set_property -dict {LOC C16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[4]}] ;# J9.F7 HA04_P +#set_property -dict {LOC B16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[4]}] ;# J9.F8 HA04_N +#set_property -dict {LOC B15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[5]}] ;# J9.E6 HA05_P +#set_property -dict {LOC A15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[5]}] ;# J9.E7 HA05_N +#set_property -dict {LOC G17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[6]}] ;# J9.K10 HA06_P +#set_property -dict {LOC G16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[6]}] ;# J9.K11 HA06_N +#set_property -dict {LOC D13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[7]}] ;# J9.J9 HA07_P +#set_property -dict {LOC C13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[7]}] ;# J9.J10 HA07_N +#set_property -dict {LOC E15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[8]}] ;# J9.F10 HA08_P +#set_property -dict {LOC D15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[8]}] ;# J9.F11 HA08_N +#set_property -dict {LOC E16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[9]}] ;# J9.E9 HA09_P +#set_property -dict {LOC D16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[9]}] ;# J9.E10 HA09_N +#set_property -dict {LOC R16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[10]}] ;# J9.K13 HA10_P +#set_property -dict {LOC P16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[10]}] ;# J9.K14 HA10_N +#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[11]}] ;# J9.J12 HA11_P +#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[11]}] ;# J9.J13 HA11_N +#set_property -dict {LOC H17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[12]}] ;# J9.F13 HA12_P +#set_property -dict {LOC H16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[12]}] ;# J9.F14 HA12_N +#set_property -dict {LOC J13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[13]}] ;# J9.E12 HA13_P +#set_property -dict {LOC H13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[13]}] ;# J9.E13 HA13_N +#set_property -dict {LOC P14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[14]}] ;# J9.J15 HA14_P +#set_property -dict {LOC N14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[14]}] ;# J9.J16 HA14_N +#set_property -dict {LOC N16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[15]}] ;# J9.F14 HA15_P +#set_property -dict {LOC M16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[15]}] ;# J9.F16 HA15_N +#set_property -dict {LOC M14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[16]}] ;# J9.E15 HA16_P +#set_property -dict {LOC L14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[16]}] ;# J9.E16 HA16_N +#set_property -dict {LOC J14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[17]}] ;# J9.K16 HA17_P_CC +#set_property -dict {LOC H14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[17]}] ;# J9.K17 HA17_N_CC +#set_property -dict {LOC J16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[18]}] ;# J9.J18 HA18_P_CC +#set_property -dict {LOC J15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[18]}] ;# J9.J19 HA18_N_CC +#set_property -dict {LOC F13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[19]}] ;# J9.F19 HA19_P +#set_property -dict {LOC E13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[19]}] ;# J9.F20 HA19_N +#set_property -dict {LOC K16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[20]}] ;# J9.E18 HA20_P +#set_property -dict {LOC K15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[20]}] ;# J9.E19 HA20_N +#set_property -dict {LOC C14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[21]}] ;# J9.K19 HA21_P +#set_property -dict {LOC B14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[21]}] ;# J9.K20 HA21_N +#set_property -dict {LOC R15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[22]}] ;# J9.J21 HA22_P +#set_property -dict {LOC P15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[22]}] ;# J9.J22 HA22_N +#set_property -dict {LOC P13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[23]}] ;# J9.K22 HA23_P +#set_property -dict {LOC N13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[23]}] ;# J9.K23 HA23_N + +#set_property -dict {LOC H19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[0]}] ;# J9.K25 HB00_P_CC +#set_property -dict {LOC H18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[0]}] ;# J9.K26 HB00_N_CC +#set_property -dict {LOC D18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[1]}] ;# J9.J24 HB01_P +#set_property -dict {LOC C18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[1]}] ;# J9.J25 HB01_N +#set_property -dict {LOC D19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[2]}] ;# J9.F22 HB02_P +#set_property -dict {LOC C19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[2]}] ;# J9.F23 HB02_N +#set_property -dict {LOC B20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[3]}] ;# J9.E21 HB03_P +#set_property -dict {LOC A20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[3]}] ;# J9.E22 HB03_N +#set_property -dict {LOC F18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[4]}] ;# J9.F25 HB04_P +#set_property -dict {LOC F17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[4]}] ;# J9.F26 HB04_N +#set_property -dict {LOC E18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[5]}] ;# J9.E24 HB05_P +#set_property -dict {LOC E17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[5]}] ;# J9.E25 HB05_N +#set_property -dict {LOC J20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[6]}] ;# J9.K28 HB06_P_CC +#set_property -dict {LOC J19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[6]}] ;# J9.K29 HB06_N_CC +#set_property -dict {LOC F20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[7]}] ;# J9.J27 HB07_P +#set_property -dict {LOC F19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[7]}] ;# J9.J28 HB07_N +#set_property -dict {LOC J21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[8]}] ;# J9.F28 HB08_P +#set_property -dict {LOC H21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[8]}] ;# J9.F29 HB08_N +#set_property -dict {LOC G20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[9]}] ;# J9.E27 HB09_P +#set_property -dict {LOC G19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[9]}] ;# J9.E28 HB09_N +#set_property -dict {LOC P19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[10]}] ;# J9.K31 HB10_P +#set_property -dict {LOC N19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[10]}] ;# J9.K32 HB10_N +#set_property -dict {LOC L17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[11]}] ;# J9.J30 HB11_P +#set_property -dict {LOC K17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[11]}] ;# J9.J31 HB11_N +#set_property -dict {LOC L19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[12]}] ;# J9.F31 HB12_P +#set_property -dict {LOC L18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[12]}] ;# J9.F32 HB12_N +#set_property -dict {LOC N17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[13]}] ;# J9.E30 HB13_P +#set_property -dict {LOC M17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[13]}] ;# J9.E31 HB13_N +#set_property -dict {LOC N21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[14]}] ;# J9.K34 HB14_P +#set_property -dict {LOC M21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[14]}] ;# J9.K35 HB14_N +#set_property -dict {LOC R20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[15]}] ;# J9.J33 HB15_P +#set_property -dict {LOC P20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[15]}] ;# J9.J34 HB15_N +#set_property -dict {LOC L20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[16]}] ;# J9.F34 HB16_P +#set_property -dict {LOC K20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[16]}] ;# J9.F35 HB16_N +#set_property -dict {LOC K18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[17]}] ;# J9.K37 HB17_P_CC +#set_property -dict {LOC J18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[17]}] ;# J9.K38 HB17_N_CC +#set_property -dict {LOC C21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[18]}] ;# J9.J36 HB18_P +#set_property -dict {LOC B21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[18]}] ;# J9.J37 HB18_N +#set_property -dict {LOC E21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[19]}] ;# J9.E33 HB19_P +#set_property -dict {LOC E20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[19]}] ;# J9.E34 HB19_N +#set_property -dict {LOC B19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[20]}] ;# J9.F37 HB20_P +#set_property -dict {LOC A19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[20]}] ;# J9.F38 HB20_N +#set_property -dict {LOC D21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[21]}] ;# J9.E36 HB21_P +#set_property -dict {LOC D20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[21]}] ;# J9.E37 HB21_N + +#set_property -dict {LOC AW14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk0_m2c_p}] ;# J9.H4 CLK0_M2C_P +#set_property -dict {LOC AW13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk0_m2c_n}] ;# J9.H5 CLK0_M2C_N +#set_property -dict {LOC AV18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk1_m2c_p}] ;# J9.G2 CLK1_M2C_P +#set_property -dict {LOC AW18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk1_m2c_n}] ;# J9.G3 CLK1_M2C_N + +#set_property -dict {LOC G25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_user_def0_p}] ;# J9.L32 USER_DEF0_P +#set_property -dict {LOC G24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_user_def0_n}] ;# J9.L33 USER_DEF0_N +#set_property -dict {LOC F24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_refclk_m2c_p}] ;# J9.L24 REFCLK_M2C_P +#set_property -dict {LOC F23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_refclk_m2c_n}] ;# J9.L25 REFCLK_M2C_N +set_property -dict {LOC E23 IOSTANDARD LVDS } [get_ports {fmc_sync_c2m_p}] ;# J9.L16 SYNC_C2M_P +set_property -dict {LOC E22 IOSTANDARD LVDS } [get_ports {fmc_sync_c2m_n}] ;# J9.L17 SYNC_C2M_N +#set_property -dict {LOC J24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_sync_m2c_p}] ;# J9.L28 SYNC_M2C_P +#set_property -dict {LOC H24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_sync_m2c_n}] ;# J9.L29 SYNC_M2C_N + +#set_property -dict {LOC AV23 IOSTANDARD LVCMOS18} [get_ports {fmc_pg_m2c}] ;# J9.F1 PG_M2C +#set_property -dict {LOC AW23 IOSTANDARD LVCMOS18} [get_ports {fmc_prsnt_m2c_l}] ;# J9.H2 PRSNT_M2C_L +#set_property -dict {LOC BC23 IOSTANDARD LVCMOS18} [get_ports {fmc_hspc_prsnt_m2c_l}] ;# J9.Z1 HSPC_PRSNT_M2C_L + +set_property -dict {LOC Y7 } [get_ports {fmc_qsfp_1_tx_p[0]}] ;# MGTYTXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C2 DP0_C2M_P +set_property -dict {LOC Y6 } [get_ports {fmc_qsfp_1_tx_n[0]}] ;# MGTYTXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C3 DP0_C2M_N +set_property -dict {LOC Y2 } [get_ports {fmc_qsfp_1_rx_p[0]}] ;# MGTYRXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C6 DP0_M2C_P +set_property -dict {LOC Y1 } [get_ports {fmc_qsfp_1_rx_n[0]}] ;# MGTYRXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C7 DP0_M2C_N +set_property -dict {LOC V7 } [get_ports {fmc_qsfp_1_tx_p[2]}] ;# MGTYTXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A22 DP1_C2M_P +set_property -dict {LOC V6 } [get_ports {fmc_qsfp_1_tx_n[2]}] ;# MGTYTXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A23 DP1_C2M_N +set_property -dict {LOC V2 } [get_ports {fmc_qsfp_1_rx_p[2]}] ;# MGTYRXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A2 DP1_M2C_P +set_property -dict {LOC V1 } [get_ports {fmc_qsfp_1_rx_n[2]}] ;# MGTYRXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A3 DP1_M2C_N +set_property -dict {LOC W9 } [get_ports {fmc_qsfp_1_tx_p[1]}] ;# MGTYTXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A26 DP2_C2M_P +set_property -dict {LOC W8 } [get_ports {fmc_qsfp_1_tx_n[1]}] ;# MGTYTXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A27 DP2_C2M_N +set_property -dict {LOC W4 } [get_ports {fmc_qsfp_1_rx_p[1]}] ;# MGTYRXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A6 DP2_M2C_P +set_property -dict {LOC W3 } [get_ports {fmc_qsfp_1_rx_n[1]}] ;# MGTYRXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A7 DP2_M2C_N +set_property -dict {LOC AA9 } [get_ports {fmc_qsfp_1_tx_p[3]}] ;# MGTYTXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A30 DP3_C2M_P +set_property -dict {LOC AA8 } [get_ports {fmc_qsfp_1_tx_n[3]}] ;# MGTYTXN0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A31 DP3_C2M_N +set_property -dict {LOC AA4 } [get_ports {fmc_qsfp_1_rx_p[3]}] ;# MGTYRXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A10 DP3_M2C_P +set_property -dict {LOC AA3 } [get_ports {fmc_qsfp_1_rx_n[3]}] ;# MGTYRXN0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A11 DP3_M2C_N +set_property -dict {LOC Y11 } [get_ports fmc_qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_229 from J9.D4 GBTCLK0_M2C_P +set_property -dict {LOC Y10 } [get_ports fmc_qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_229 from J9.D5 GBTCLK0_M2C_N +#set_property -dict {LOC V11 } [get_ports fmc_mgt_refclk_0_1_p] ;# MGTREFCLK1P_229 from U27.14 OUT3 +#set_property -dict {LOC V10 } [get_ports fmc_mgt_refclk_0_1_n] ;# MGTREFCLK1N_229 from U27.13 OUT3B + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_1_mgt_refclk [get_ports fmc_qsfp_1_mgt_refclk_p] +#create_clock -period 6.206 -name fmc_mgt_refclk_0_1 [get_ports fmc_mgt_refclk_0_1_p] + +set_property -dict {LOC AC9 } [get_ports {fmc_qsfp_6_tx_p[1]}] ;# MGTYTXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A34 DP4_C2M_P +set_property -dict {LOC AC8 } [get_ports {fmc_qsfp_6_tx_n[1]}] ;# MGTYTXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A35 DP4_C2M_N +set_property -dict {LOC AC4 } [get_ports {fmc_qsfp_6_rx_p[1]}] ;# MGTYRXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A14 DP4_M2C_P +set_property -dict {LOC AC3 } [get_ports {fmc_qsfp_6_rx_n[1]}] ;# MGTYRXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A15 DP4_M2C_N +set_property -dict {LOC AE9 } [get_ports {fmc_qsfp_6_tx_p[0]}] ;# MGTYTXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A38 DP5_C2M_P +set_property -dict {LOC AE8 } [get_ports {fmc_qsfp_6_tx_n[0]}] ;# MGTYTXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A39 DP5_C2M_N +set_property -dict {LOC AE4 } [get_ports {fmc_qsfp_6_rx_p[0]}] ;# MGTYRXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A18 DP5_M2C_P +set_property -dict {LOC AE3 } [get_ports {fmc_qsfp_6_rx_n[0]}] ;# MGTYRXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A19 DP5_M2C_N +set_property -dict {LOC AD7 } [get_ports {fmc_qsfp_6_tx_p[2]}] ;# MGTYTXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B36 DP6_C2M_P +set_property -dict {LOC AD6 } [get_ports {fmc_qsfp_6_tx_n[2]}] ;# MGTYTXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B37 DP6_C2M_N +set_property -dict {LOC AD2 } [get_ports {fmc_qsfp_6_rx_p[2]}] ;# MGTYRXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B16 DP6_M2C_P +set_property -dict {LOC AD1 } [get_ports {fmc_qsfp_6_rx_n[2]}] ;# MGTYRXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B17 DP6_M2C_N +set_property -dict {LOC AB7 } [get_ports {fmc_qsfp_6_tx_p[3]}] ;# MGTYTXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B32 DP7_C2M_P +set_property -dict {LOC AB6 } [get_ports {fmc_qsfp_6_tx_n[3]}] ;# MGTYTXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B33 DP7_C2M_N +set_property -dict {LOC AB2 } [get_ports {fmc_qsfp_6_rx_p[3]}] ;# MGTYRXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B12 DP7_M2C_P +set_property -dict {LOC AB1 } [get_ports {fmc_qsfp_6_rx_n[3]}] ;# MGTYRXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B13 DP7_M2C_N +set_property -dict {LOC AD11} [get_ports fmc_qsfp_6_mgt_refclk_p] ;# MGTREFCLK0P_228 from J9.B20 GBTCLK1_M2C_P +set_property -dict {LOC AD10} [get_ports fmc_qsfp_6_mgt_refclk_n] ;# MGTREFCLK0N_228 from J9.B21 GBTCLK1_M2C_N + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_6_mgt_refclk [get_ports fmc_qsfp_6_mgt_refclk_p] + +set_property -dict {LOC L9 } [get_ports {fmc_qsfp_4_tx_p[3]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B28 DP8_C2M_P +set_property -dict {LOC L8 } [get_ports {fmc_qsfp_4_tx_n[3]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B29 DP8_C2M_N +set_property -dict {LOC L4 } [get_ports {fmc_qsfp_4_rx_p[3]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B8 DP8_M2C_P +set_property -dict {LOC L3 } [get_ports {fmc_qsfp_4_rx_n[3]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B9 DP8_M2C_N +set_property -dict {LOC K7 } [get_ports {fmc_qsfp_4_tx_p[2]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B24 DP9_C2M_P +set_property -dict {LOC K6 } [get_ports {fmc_qsfp_4_tx_n[2]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B25 DP9_C2M_N +set_property -dict {LOC K2 } [get_ports {fmc_qsfp_4_rx_p[2]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B4 DP9_M2C_P +set_property -dict {LOC K1 } [get_ports {fmc_qsfp_4_rx_n[2]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B5 DP9_M2C_N +set_property -dict {LOC M7 } [get_ports {fmc_qsfp_4_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Z24 DP10_C2M_P +set_property -dict {LOC M6 } [get_ports {fmc_qsfp_4_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Z25 DP10_C2M_N +set_property -dict {LOC M2 } [get_ports {fmc_qsfp_4_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Y10 DP10_M2C_P +set_property -dict {LOC M1 } [get_ports {fmc_qsfp_4_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Y11 DP10_M2C_N +set_property -dict {LOC N9 } [get_ports {fmc_qsfp_4_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Y26 DP11_C2M_P +set_property -dict {LOC N8 } [get_ports {fmc_qsfp_4_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Y27 DP11_C2M_N +set_property -dict {LOC N4 } [get_ports {fmc_qsfp_4_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Z12 DP11_M2C_P +set_property -dict {LOC N3 } [get_ports {fmc_qsfp_4_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Z13 DP11_M2C_N +set_property -dict {LOC M11 } [get_ports fmc_qsfp_4_mgt_refclk_p] ;# MGTREFCLK0P_231 from J9.L12 GBTCLK2_M2C_P +set_property -dict {LOC M10 } [get_ports fmc_qsfp_4_mgt_refclk_n] ;# MGTREFCLK0N_231 from J9.L13 GBTCLK2_M2C_N +#set_property -dict {LOC K11 } [get_ports fmc_mgt_refclk_2_1_p] ;# MGTREFCLK1P_231 from U27.17 OUT2 +#set_property -dict {LOC K10 } [get_ports fmc_mgt_refclk_2_1_n] ;# MGTREFCLK1N_231 from U27.16 OUT2B + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_4_mgt_refclk [get_ports fmc_qsfp_4_mgt_refclk_p] +#create_clock -period 6.206 -name fmc_mgt_refclk_2_1 [get_ports fmc_mgt_refclk_2_1_p] + +set_property -dict {LOC P7 } [get_ports {fmc_qsfp_3_tx_p[2]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Z28 DP12_C2M_P +set_property -dict {LOC P6 } [get_ports {fmc_qsfp_3_tx_n[2]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Z29 DP12_C2M_N +set_property -dict {LOC P2 } [get_ports {fmc_qsfp_3_rx_p[2]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Y14 DP12_M2C_P +set_property -dict {LOC P1 } [get_ports {fmc_qsfp_3_rx_n[2]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Y15 DP12_M2C_N +set_property -dict {LOC R9 } [get_ports {fmc_qsfp_3_tx_p[3]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Y30 DP13_C2M_P +set_property -dict {LOC R8 } [get_ports {fmc_qsfp_3_tx_n[3]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Y31 DP13_C2M_N +set_property -dict {LOC R4 } [get_ports {fmc_qsfp_3_rx_p[3]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Z16 DP13_M2C_P +set_property -dict {LOC R3 } [get_ports {fmc_qsfp_3_rx_n[3]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Z17 DP13_M2C_N +set_property -dict {LOC T7 } [get_ports {fmc_qsfp_3_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.M18 DP14_C2M_P +set_property -dict {LOC T6 } [get_ports {fmc_qsfp_3_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.M19 DP14_C2M_N +set_property -dict {LOC T2 } [get_ports {fmc_qsfp_3_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.Y18 DP14_M2C_P +set_property -dict {LOC T1 } [get_ports {fmc_qsfp_3_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.Y19 DP14_M2C_N +set_property -dict {LOC U9 } [get_ports {fmc_qsfp_3_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.M22 DP15_C2M_P +set_property -dict {LOC U8 } [get_ports {fmc_qsfp_3_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.M23 DP15_C2M_N +set_property -dict {LOC U4 } [get_ports {fmc_qsfp_3_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.Y22 DP15_M2C_P +set_property -dict {LOC U3 } [get_ports {fmc_qsfp_3_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.Y23 DP15_M2C_N +set_property -dict {LOC T11 } [get_ports fmc_qsfp_3_mgt_refclk_p] ;# MGTREFCLK0P_230 from J9.L8 GBTCLK3_M2C_P +set_property -dict {LOC T10 } [get_ports fmc_qsfp_3_mgt_refclk_n] ;# MGTREFCLK0N_230 from J9.L9 GBTCLK3_M2C_N + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_3_mgt_refclk [get_ports fmc_qsfp_3_mgt_refclk_p] + +set_property -dict {LOC AF7 } [get_ports {fmc_qsfp_5_tx_p[3]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.M26 DP16_C2M_P +set_property -dict {LOC AF6 } [get_ports {fmc_qsfp_5_tx_n[3]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.M27 DP16_C2M_N +set_property -dict {LOC AF2 } [get_ports {fmc_qsfp_5_rx_p[3]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.Z32 DP16_M2C_P +set_property -dict {LOC AF1 } [get_ports {fmc_qsfp_5_rx_n[3]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.Z33 DP16_M2C_N +set_property -dict {LOC AG9 } [get_ports {fmc_qsfp_5_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.M30 DP17_C2M_P +set_property -dict {LOC AG8 } [get_ports {fmc_qsfp_5_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.M31 DP17_C2M_N +set_property -dict {LOC AG4 } [get_ports {fmc_qsfp_5_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.Y34 DP17_M2C_P +set_property -dict {LOC AG3 } [get_ports {fmc_qsfp_5_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.Y35 DP17_M2C_N +set_property -dict {LOC AH7 } [get_ports {fmc_qsfp_5_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.M34 DP18_C2M_P +set_property -dict {LOC AH6 } [get_ports {fmc_qsfp_5_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.M35 DP18_C2M_N +set_property -dict {LOC AH2 } [get_ports {fmc_qsfp_5_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.Z36 DP18_M2C_P +set_property -dict {LOC AH1 } [get_ports {fmc_qsfp_5_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.Z37 DP18_M2C_N +set_property -dict {LOC AJ9 } [get_ports {fmc_qsfp_5_tx_p[0]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.M38 DP19_C2M_P +set_property -dict {LOC AJ8 } [get_ports {fmc_qsfp_5_tx_n[0]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.M39 DP19_C2M_N +set_property -dict {LOC AJ4 } [get_ports {fmc_qsfp_5_rx_p[0]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.Y38 DP19_M2C_P +set_property -dict {LOC AJ3 } [get_ports {fmc_qsfp_5_rx_n[0]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.Y39 DP19_M2C_N +set_property -dict {LOC AH11} [get_ports fmc_qsfp_5_mgt_refclk_p] ;# MGTREFCLK0P_227 from J9.L4 GBTCLK4_M2C_P +set_property -dict {LOC AH10} [get_ports fmc_qsfp_5_mgt_refclk_n] ;# MGTREFCLK0N_227 from J9.L5 GBTCLK4_M2C_N +#set_property -dict {LOC AF11} [get_ports fmc_mgt_refclk_4_1_p] ;# MGTREFCLK1P_227 from U27.11 OUT4 +#set_property -dict {LOC AF10} [get_ports fmc_mgt_refclk_4_1_n] ;# MGTREFCLK1N_227 from U27.12 OUT4B + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_5_mgt_refclk [get_ports fmc_qsfp_5_mgt_refclk_p] +#create_clock -period 6.206 -name fmc_mgt_refclk_4_1 [get_ports fmc_mgt_refclk_4_1_p] + +set_property -dict {LOC J9 } [get_ports {fmc_qsfp_2_tx_p[3]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.Z8 DP20_C2M_P +set_property -dict {LOC J8 } [get_ports {fmc_qsfp_2_tx_n[3]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.Z9 DP20_C2M_N +set_property -dict {LOC J4 } [get_ports {fmc_qsfp_2_rx_p[3]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.M14 DP20_M2C_P +set_property -dict {LOC J3 } [get_ports {fmc_qsfp_2_rx_n[3]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.M15 DP20_M2C_N +set_property -dict {LOC H7 } [get_ports {fmc_qsfp_2_tx_p[2]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.Y6 DP21_C2M_P +set_property -dict {LOC H6 } [get_ports {fmc_qsfp_2_tx_n[2]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.Y7 DP21_C2M_N +set_property -dict {LOC H2 } [get_ports {fmc_qsfp_2_rx_p[2]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.M10 DP21_M2C_P +set_property -dict {LOC H1 } [get_ports {fmc_qsfp_2_rx_n[2]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.M11 DP21_M2C_N +set_property -dict {LOC G9 } [get_ports {fmc_qsfp_2_tx_p[0]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.Z4 DP22_C2M_P +set_property -dict {LOC G8 } [get_ports {fmc_qsfp_2_tx_n[0]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.Z5 DP22_C2M_N +set_property -dict {LOC G4 } [get_ports {fmc_qsfp_2_rx_p[0]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.M6 DP22_M2C_P +set_property -dict {LOC G3 } [get_ports {fmc_qsfp_2_rx_n[0]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.M7 DP22_M2C_N +set_property -dict {LOC F7 } [get_ports {fmc_qsfp_2_tx_p[1]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.Y2 DP23_C2M_P +set_property -dict {LOC F6 } [get_ports {fmc_qsfp_2_tx_n[1]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.Y3 DP23_C2M_N +set_property -dict {LOC F2 } [get_ports {fmc_qsfp_2_rx_p[1]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.M2 DP23_M2C_P +set_property -dict {LOC F1 } [get_ports {fmc_qsfp_2_rx_n[1]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.M3 DP23_M2C_N +set_property -dict {LOC H11 } [get_ports fmc_qsfp_2_mgt_refclk_p] ;# MGTREFCLK0P_232 from J9.Z20 GBTCLK5_M2C_P +set_property -dict {LOC H10 } [get_ports fmc_qsfp_2_mgt_refclk_n] ;# MGTREFCLK0N_232 from J9.Z21 GBTCLK5_M2C_N + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_2_mgt_refclk [get_ports fmc_qsfp_2_mgt_refclk_p] diff --git a/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu13p/Makefile b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu13p/Makefile new file mode 100644 index 0000000..7a92539 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu13p/Makefile @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcvu13p-fhgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga_6qsfp.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init_6qsfp.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += ../fmc_6qsfp.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl + +# Configuration +# CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu9p/Makefile b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu9p/Makefile new file mode 100644 index 0000000..dfd2e8e --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_10g_6q_vu9p/Makefile @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga_6qsfp.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init_6qsfp.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += ../fmc_6qsfp.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl + +# Configuration +# CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/eth/example/HTG9200/fpga/fpga_6q_vu13p/Makefile b/src/eth/example/HTG9200/fpga/fpga_6q_vu13p/Makefile new file mode 100644 index 0000000..5e6e5d8 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_6q_vu13p/Makefile @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcvu13p-fhgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga_6qsfp.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init_6qsfp.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += ../fmc_6qsfp.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl + +# Configuration +# CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/eth/example/HTG9200/fpga/fpga_6q_vu9p/Makefile b/src/eth/example/HTG9200/fpga/fpga_6q_vu9p/Makefile new file mode 100644 index 0000000..85bd9b7 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_6q_vu9p/Makefile @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga_6qsfp.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init_6qsfp.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += ../fmc_6qsfp.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl + +# Configuration +# CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/eth/example/HTG9200/fpga/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt b/src/eth/example/HTG9200/fpga/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt new file mode 100644 index 0000000..ac46ab6 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt @@ -0,0 +1,412 @@ +# Si534x/7x/8x/9x Registers Script +# +# Part: Si5341 +# Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_fmc_htg_6qsfp_25g\pll\HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj +# Design ID: HTG6Q161 +# Includes Pre/Post Download Control Register Writes: Yes +# Die Revision: B1 +# Creator: ClockBuilder Pro v4.1 [2021-09-22] +# Created On: 2023-07-19 01:56:52 GMT-07:00 +Address,Data +# +# Start configuration preamble +0x0B24,0xC0 +0x0B25,0x00 +# Rev D stuck divider fix +0x0502,0x01 +0x0505,0x03 +0x0957,0x17 +0x0B4E,0x1A +# End configuration preamble +# +# Delay 300 msec +# Delay is worst case time for device to complete any calibration +# that is running due to device state change previous to this script +# being processed. +# +# Start configuration registers +0x0006,0x00 +0x0007,0x00 +0x0008,0x00 +0x000B,0x74 +0x0017,0xD0 +0x0018,0xFF +0x0021,0x0D +0x0022,0x00 +0x002B,0x02 +0x002C,0x34 +0x002D,0x10 +0x002E,0x00 +0x002F,0x00 +0x0030,0x00 +0x0031,0x00 +0x0032,0xA8 +0x0033,0x00 +0x0034,0x00 +0x0035,0x00 +0x0036,0x00 +0x0037,0x00 +0x0038,0x00 +0x0039,0x00 +0x003A,0xA8 +0x003B,0x00 +0x003C,0x00 +0x003D,0x00 +0x0041,0x00 +0x0042,0x00 +0x0043,0x07 +0x0044,0x00 +0x009E,0x00 +0x0102,0x01 +0x0108,0x06 +0x0109,0x09 +0x010A,0x33 +0x010B,0x08 +0x010D,0x06 +0x010E,0x09 +0x010F,0x33 +0x0110,0x08 +0x0112,0x06 +0x0113,0x09 +0x0114,0x33 +0x0115,0x08 +0x0117,0x06 +0x0118,0x09 +0x0119,0x33 +0x011A,0x08 +0x011C,0x06 +0x011D,0x09 +0x011E,0x33 +0x011F,0x08 +0x0121,0x06 +0x0122,0x09 +0x0123,0x33 +0x0124,0x08 +0x0126,0x06 +0x0127,0x09 +0x0128,0x33 +0x0129,0x08 +0x012B,0x06 +0x012C,0x09 +0x012D,0x33 +0x012E,0x08 +0x0130,0x06 +0x0131,0x09 +0x0132,0x33 +0x0133,0x08 +0x013A,0x01 +0x013B,0x09 +0x013C,0x3B +0x013D,0x28 +0x013F,0x00 +0x0140,0x00 +0x0141,0x40 +0x0206,0x00 +0x0208,0x00 +0x0209,0x00 +0x020A,0x00 +0x020B,0x00 +0x020C,0x00 +0x020D,0x00 +0x020E,0x00 +0x020F,0x00 +0x0210,0x00 +0x0211,0x00 +0x0212,0x00 +0x0213,0x00 +0x0214,0x00 +0x0215,0x00 +0x0216,0x00 +0x0217,0x00 +0x0218,0x00 +0x0219,0x00 +0x021A,0x00 +0x021B,0x00 +0x021C,0x02 +0x021D,0x00 +0x021E,0x00 +0x021F,0x00 +0x0220,0x00 +0x0221,0x00 +0x0222,0x01 +0x0223,0x00 +0x0224,0x00 +0x0225,0x00 +0x0226,0x00 +0x0227,0x00 +0x0228,0x00 +0x0229,0x00 +0x022A,0x00 +0x022B,0x00 +0x022C,0x00 +0x022D,0x00 +0x022E,0x00 +0x022F,0x00 +0x0235,0x00 +0x0236,0x00 +0x0237,0x00 +0x0238,0x00 +0x0239,0x52 +0x023A,0x00 +0x023B,0x00 +0x023C,0x00 +0x023D,0x00 +0x023E,0x80 +0x024A,0x00 +0x024B,0x00 +0x024C,0x00 +0x024D,0x00 +0x024E,0x00 +0x024F,0x00 +0x0250,0x00 +0x0251,0x00 +0x0252,0x00 +0x0253,0x00 +0x0254,0x00 +0x0255,0x00 +0x0256,0x00 +0x0257,0x00 +0x0258,0x00 +0x0259,0x00 +0x025A,0x00 +0x025B,0x00 +0x025C,0x00 +0x025D,0x00 +0x025E,0x00 +0x025F,0x00 +0x0260,0x00 +0x0261,0x00 +0x0262,0x00 +0x0263,0x00 +0x0264,0x00 +0x0268,0x00 +0x0269,0x00 +0x026A,0x00 +0x026B,0x48 +0x026C,0x54 +0x026D,0x47 +0x026E,0x36 +0x026F,0x51 +0x0270,0x31 +0x0271,0x36 +0x0272,0x31 +0x0302,0x00 +0x0303,0x00 +0x0304,0x00 +0x0305,0x80 +0x0306,0x14 +0x0307,0x00 +0x0308,0x00 +0x0309,0x00 +0x030A,0x00 +0x030B,0x80 +0x030C,0x00 +0x030D,0x00 +0x030E,0x00 +0x030F,0x00 +0x0310,0x00 +0x0311,0x00 +0x0312,0x00 +0x0313,0x00 +0x0314,0x00 +0x0315,0x00 +0x0316,0x00 +0x0317,0x00 +0x0318,0x00 +0x0319,0x00 +0x031A,0x00 +0x031B,0x00 +0x031C,0x00 +0x031D,0x00 +0x031E,0x00 +0x031F,0x00 +0x0320,0x00 +0x0321,0x00 +0x0322,0x00 +0x0323,0x00 +0x0324,0x00 +0x0325,0x00 +0x0326,0x00 +0x0327,0x00 +0x0328,0x00 +0x0329,0x00 +0x032A,0x00 +0x032B,0x00 +0x032C,0x00 +0x032D,0x00 +0x032E,0x00 +0x032F,0x00 +0x0330,0x00 +0x0331,0x00 +0x0332,0x00 +0x0333,0x00 +0x0334,0x00 +0x0335,0x00 +0x0336,0x00 +0x0337,0x00 +0x0338,0x00 +0x0339,0x1F +0x033B,0x00 +0x033C,0x00 +0x033D,0x00 +0x033E,0x00 +0x033F,0x00 +0x0340,0x00 +0x0341,0x00 +0x0342,0x00 +0x0343,0x00 +0x0344,0x00 +0x0345,0x00 +0x0346,0x00 +0x0347,0x00 +0x0348,0x00 +0x0349,0x00 +0x034A,0x00 +0x034B,0x00 +0x034C,0x00 +0x034D,0x00 +0x034E,0x00 +0x034F,0x00 +0x0350,0x00 +0x0351,0x00 +0x0352,0x00 +0x0353,0x00 +0x0354,0x00 +0x0355,0x00 +0x0356,0x00 +0x0357,0x00 +0x0358,0x00 +0x0359,0x00 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+0x0846,0x00 +0x0847,0x00 +0x0848,0x00 +0x0849,0x00 +0x084A,0x00 +0x084B,0x00 +0x084C,0x00 +0x084D,0x00 +0x084E,0x00 +0x084F,0x00 +0x0850,0x00 +0x0851,0x00 +0x0852,0x00 +0x0853,0x00 +0x0854,0x00 +0x0855,0x00 +0x0856,0x00 +0x0857,0x00 +0x0858,0x00 +0x0859,0x00 +0x085A,0x00 +0x085B,0x00 +0x085C,0x00 +0x085D,0x00 +0x085E,0x00 +0x085F,0x00 +0x0860,0x00 +0x0861,0x00 +0x090E,0x00 +0x091C,0x04 +0x0943,0x00 +0x0949,0x04 +0x094A,0x40 +0x094E,0x49 +0x094F,0x02 +0x095E,0x00 +0x0A02,0x00 +0x0A03,0x01 +0x0A04,0x01 +0x0A05,0x01 +0x0A14,0x00 +0x0A1A,0x00 +0x0A20,0x00 +0x0A26,0x00 +0x0A2C,0x00 +0x0B44,0x0F +0x0B4A,0x1E +0x0B57,0xA0 +0x0B58,0x00 +# End configuration registers +# +# Start configuration postamble +0x001C,0x01 +0x0B24,0xC3 +0x0B25,0x02 +# End configuration postamble diff --git a/src/eth/example/HTG9200/fpga/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj b/src/eth/example/HTG9200/fpga/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj new file mode 100644 index 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