From 4d8f0cfece788c33bb5992e27ed16a6359598bfd Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 3 Mar 2026 13:31:16 -0800 Subject: [PATCH] cndm: Move control registers out of port module Signed-off-by: Alex Forencich --- src/cndm/rtl/cndm_micro_cpl_wr.sv | 201 +++++++++++++++-- src/cndm/rtl/cndm_micro_desc_rd.sv | 217 +++++++++++++++++-- src/cndm/rtl/cndm_micro_dp_mgr.sv | 20 +- src/cndm/rtl/cndm_micro_port.sv | 336 ++++++++--------------------- 4 files changed, 467 insertions(+), 307 deletions(-) diff --git a/src/cndm/rtl/cndm_micro_cpl_wr.sv b/src/cndm/rtl/cndm_micro_cpl_wr.sv index ba73edf..0b7589e 100644 --- a/src/cndm/rtl/cndm_micro_cpl_wr.sv +++ b/src/cndm/rtl/cndm_micro_cpl_wr.sv @@ -20,6 +20,17 @@ module cndm_micro_cpl_wr input wire logic clk, input wire logic rst, + /* + * Control register interface + */ + taxi_axil_if.wr_slv s_axil_ctrl_wr, + taxi_axil_if.rd_slv s_axil_ctrl_rd, + + /* + * Datapath control register interface + */ + taxi_apb_if.slv s_apb_dp_ctrl, + /* * DMA */ @@ -27,19 +38,169 @@ module cndm_micro_cpl_wr taxi_dma_desc_if.sts_snk dma_wr_desc_sts, taxi_dma_ram_if.rd_slv dma_ram_rd, - input wire logic txcq_en, - input wire logic [3:0] txcq_size, - input wire logic [63:0] txcq_base_addr, - output wire logic [15:0] txcq_prod, - input wire logic rxcq_en, - input wire logic [3:0] rxcq_size, - input wire logic [63:0] rxcq_base_addr, - output wire logic [15:0] rxcq_prod, - taxi_axis_if.snk axis_cpl[2], output wire logic irq ); +localparam AXIL_ADDR_W = s_axil_ctrl_wr.ADDR_W; +localparam AXIL_DATA_W = s_axil_ctrl_wr.DATA_W; + +localparam APB_ADDR_W = s_apb_dp_ctrl.ADDR_W; +localparam APB_DATA_W = s_apb_dp_ctrl.DATA_W; + +logic txcq_en_reg = '0; +logic [3:0] txcq_size_reg = '0; +logic [63:0] txcq_base_addr_reg = '0; +logic rxcq_en_reg = '0; +logic [3:0] rxcq_size_reg = '0; +logic [63:0] rxcq_base_addr_reg = '0; + +logic [15:0] txcq_prod_ptr_reg = '0; +logic [15:0] rxcq_prod_ptr_reg = '0; + +logic s_axil_ctrl_awready_reg = 1'b0; +logic s_axil_ctrl_wready_reg = 1'b0; +logic s_axil_ctrl_bvalid_reg = 1'b0; + +logic s_axil_ctrl_arready_reg = 1'b0; +logic [AXIL_DATA_W-1:0] s_axil_ctrl_rdata_reg = '0; +logic s_axil_ctrl_rvalid_reg = 1'b0; + +assign s_axil_ctrl_wr.awready = s_axil_ctrl_awready_reg; +assign s_axil_ctrl_wr.wready = s_axil_ctrl_wready_reg; +assign s_axil_ctrl_wr.bresp = '0; +assign s_axil_ctrl_wr.buser = '0; +assign s_axil_ctrl_wr.bvalid = s_axil_ctrl_bvalid_reg; + +assign s_axil_ctrl_rd.arready = s_axil_ctrl_arready_reg; +assign s_axil_ctrl_rd.rdata = s_axil_ctrl_rdata_reg; +assign s_axil_ctrl_rd.rresp = '0; +assign s_axil_ctrl_rd.ruser = '0; +assign s_axil_ctrl_rd.rvalid = s_axil_ctrl_rvalid_reg; + +logic s_apb_dp_ctrl_pready_reg = 1'b0; +logic [AXIL_DATA_W-1:0] s_apb_dp_ctrl_prdata_reg = '0; + +assign s_apb_dp_ctrl.pready = s_apb_dp_ctrl_pready_reg; +assign s_apb_dp_ctrl.prdata = s_apb_dp_ctrl_prdata_reg; +assign s_apb_dp_ctrl.pslverr = 1'b0; +assign s_apb_dp_ctrl.pruser = '0; +assign s_apb_dp_ctrl.pbuser = '0; + +always_ff @(posedge clk) begin + s_axil_ctrl_awready_reg <= 1'b0; + s_axil_ctrl_wready_reg <= 1'b0; + s_axil_ctrl_bvalid_reg <= s_axil_ctrl_bvalid_reg && !s_axil_ctrl_wr.bready; + + s_axil_ctrl_arready_reg <= 1'b0; + s_axil_ctrl_rvalid_reg <= s_axil_ctrl_rvalid_reg && !s_axil_ctrl_rd.rready; + + s_apb_dp_ctrl_pready_reg <= 1'b0; + + if (s_axil_ctrl_wr.awvalid && s_axil_ctrl_wr.wvalid && !s_axil_ctrl_bvalid_reg) begin + s_axil_ctrl_awready_reg <= 1'b1; + s_axil_ctrl_wready_reg <= 1'b1; + s_axil_ctrl_bvalid_reg <= 1'b1; + + // case ({s_axil_ctrl_wr.awaddr[9:2], 2'b00}) + // 10'h000: begin + // txcq_en_reg <= s_axil_ctrl_wr.wdata[0]; + // txcq_size_reg <= s_axil_ctrl_wr.wdata[19:16]; + // end + // 10'h008: txcq_base_addr_reg[31:0] <= s_axil_ctrl_wr.wdata; + // 10'h00c: txcq_base_addr_reg[63:32] <= s_axil_ctrl_wr.wdata; + + // 10'h100: begin + // rxcq_en_reg <= s_axil_ctrl_wr.wdata[0]; + // rxcq_size_reg <= s_axil_ctrl_wr.wdata[19:16]; + // end + // 10'h108: rxcq_base_addr_reg[31:0] <= s_axil_ctrl_wr.wdata; + // 10'h10c: rxcq_base_addr_reg[63:32] <= s_axil_ctrl_wr.wdata; + // default: begin end + // endcase + end + + if (s_axil_ctrl_rd.arvalid && !s_axil_ctrl_rvalid_reg) begin + s_axil_ctrl_rdata_reg <= '0; + + s_axil_ctrl_arready_reg <= 1'b1; + s_axil_ctrl_rvalid_reg <= 1'b1; + + // case ({s_axil_ctrl_rd.araddr[9:2], 2'b00}) + // 10'h000: begin + // s_axil_ctrl_rdata_reg[0] <= txcq_en_reg; + // s_axil_ctrl_rdata_reg[19:16] <= txcq_size_reg; + // end + // 10'h004: s_axil_ctrl_rdata_reg[15:0] <= txcq_prod_ptr_reg; + // 10'h008: s_axil_ctrl_rdata_reg <= txcq_base_addr_reg[31:0]; + // 10'h00c: s_axil_ctrl_rdata_reg <= txcq_base_addr_reg[63:32]; + + // 10'h100: begin + // s_axil_ctrl_rdata_reg[0] <= rxcq_en_reg; + // s_axil_ctrl_rdata_reg[19:16] <= rxcq_size_reg; + // end + // 10'h104: s_axil_ctrl_rdata_reg[15:0] <= rxcq_prod_ptr_reg; + // 10'h108: s_axil_ctrl_rdata_reg <= rxcq_base_addr_reg[31:0]; + // 10'h10c: s_axil_ctrl_rdata_reg <= rxcq_base_addr_reg[63:32]; + // default: begin end + // endcase + end + + if (s_apb_dp_ctrl.penable && s_apb_dp_ctrl.psel && !s_apb_dp_ctrl_pready_reg) begin + s_apb_dp_ctrl_pready_reg <= 1'b1; + s_apb_dp_ctrl_prdata_reg <= '0; + + if (s_apb_dp_ctrl.pwrite) begin + case ({s_apb_dp_ctrl.paddr[9:2], 2'b00}) + 10'h000: begin + txcq_en_reg <= s_apb_dp_ctrl.pwdata[0]; + txcq_size_reg <= s_apb_dp_ctrl.pwdata[19:16]; + end + 10'h008: txcq_base_addr_reg[31:0] <= s_apb_dp_ctrl.pwdata; + 10'h00c: txcq_base_addr_reg[63:32] <= s_apb_dp_ctrl.pwdata; + + 10'h100: begin + rxcq_en_reg <= s_apb_dp_ctrl.pwdata[0]; + rxcq_size_reg <= s_apb_dp_ctrl.pwdata[19:16]; + end + 10'h108: rxcq_base_addr_reg[31:0] <= s_apb_dp_ctrl.pwdata; + 10'h10c: rxcq_base_addr_reg[63:32] <= s_apb_dp_ctrl.pwdata; + default: begin end + endcase + end + + case ({s_apb_dp_ctrl.paddr[9:2], 2'b00}) + 10'h000: begin + s_apb_dp_ctrl_prdata_reg[0] <= txcq_en_reg; + s_apb_dp_ctrl_prdata_reg[19:16] <= txcq_size_reg; + end + 10'h004: s_apb_dp_ctrl_prdata_reg[15:0] <= txcq_prod_ptr_reg; + 10'h008: s_apb_dp_ctrl_prdata_reg <= txcq_base_addr_reg[31:0]; + 10'h00c: s_apb_dp_ctrl_prdata_reg <= txcq_base_addr_reg[63:32]; + + 10'h100: begin + s_apb_dp_ctrl_prdata_reg[0] <= rxcq_en_reg; + s_apb_dp_ctrl_prdata_reg[19:16] <= rxcq_size_reg; + end + 10'h104: s_apb_dp_ctrl_prdata_reg[15:0] <= rxcq_prod_ptr_reg; + 10'h108: s_apb_dp_ctrl_prdata_reg <= rxcq_base_addr_reg[31:0]; + 10'h10c: s_apb_dp_ctrl_prdata_reg <= rxcq_base_addr_reg[63:32]; + default: begin end + endcase + end + + if (rst) begin + s_axil_ctrl_awready_reg <= 1'b0; + s_axil_ctrl_wready_reg <= 1'b0; + s_axil_ctrl_bvalid_reg <= 1'b0; + + s_axil_ctrl_arready_reg <= 1'b0; + s_axil_ctrl_rvalid_reg <= 1'b0; + + s_apb_dp_ctrl_pready_reg <= 1'b0; + end +end + taxi_axis_if #( .DATA_W(axis_cpl[0].DATA_W), .KEEP_EN(axis_cpl[0].KEEP_EN), @@ -62,16 +223,10 @@ typedef enum logic [1:0] { state_t state_reg = STATE_IDLE; -logic [15:0] txcq_prod_ptr_reg = '0; -logic [15:0] rxcq_prod_ptr_reg = '0; - logic phase_tag_reg = 1'b0; logic irq_reg = 1'b0; -assign txcq_prod = txcq_prod_ptr_reg; -assign rxcq_prod = rxcq_prod_ptr_reg; - assign irq = irq_reg; always_ff @(posedge clk) begin @@ -90,11 +245,11 @@ always_ff @(posedge clk) begin dma_wr_desc_req.req_user <= '0; dma_wr_desc_req.req_valid <= dma_wr_desc_req.req_valid && !dma_wr_desc_req.req_ready; - if (!txcq_en) begin + if (!txcq_en_reg) begin txcq_prod_ptr_reg <= '0; end - if (!rxcq_en) begin + if (!rxcq_en_reg) begin rxcq_prod_ptr_reg <= '0; end @@ -105,11 +260,11 @@ always_ff @(posedge clk) begin dma_wr_desc_req.req_src_addr <= '0; if (cpl_comb.tid == 0) begin - dma_wr_desc_req.req_dst_addr <= txcq_base_addr + 64'(16'(txcq_prod_ptr_reg & ({16{1'b1}} >> (16 - txcq_size))) * 16); - phase_tag_reg <= !txcq_prod_ptr_reg[txcq_size]; + dma_wr_desc_req.req_dst_addr <= txcq_base_addr_reg + 64'(16'(txcq_prod_ptr_reg & ({16{1'b1}} >> (16 - txcq_size_reg))) * 16); + phase_tag_reg <= !txcq_prod_ptr_reg[txcq_size_reg]; if (cpl_comb.tvalid && !cpl_comb.tready) begin txcq_prod_ptr_reg <= txcq_prod_ptr_reg + 1; - if (txcq_en) begin + if (txcq_en_reg) begin dma_wr_desc_req.req_valid <= 1'b1; state_reg <= STATE_WRITE_DATA; end else begin @@ -117,11 +272,11 @@ always_ff @(posedge clk) begin end end end else begin - dma_wr_desc_req.req_dst_addr <= rxcq_base_addr + 64'(16'(rxcq_prod_ptr_reg & ({16{1'b1}} >> (16 - rxcq_size))) * 16); - phase_tag_reg <= !rxcq_prod_ptr_reg[rxcq_size]; + dma_wr_desc_req.req_dst_addr <= rxcq_base_addr_reg + 64'(16'(rxcq_prod_ptr_reg & ({16{1'b1}} >> (16 - rxcq_size_reg))) * 16); + phase_tag_reg <= !rxcq_prod_ptr_reg[rxcq_size_reg]; if (cpl_comb.tvalid && !cpl_comb.tready) begin rxcq_prod_ptr_reg <= rxcq_prod_ptr_reg + 1; - if (rxcq_en) begin + if (rxcq_en_reg) begin dma_wr_desc_req.req_valid <= 1'b1; state_reg <= STATE_WRITE_DATA; end else begin diff --git a/src/cndm/rtl/cndm_micro_desc_rd.sv b/src/cndm/rtl/cndm_micro_desc_rd.sv index 1b2f0d9..3b84fee 100644 --- a/src/cndm/rtl/cndm_micro_desc_rd.sv +++ b/src/cndm/rtl/cndm_micro_desc_rd.sv @@ -20,6 +20,17 @@ module cndm_micro_desc_rd input wire logic clk, input wire logic rst, + /* + * Control register interface + */ + taxi_axil_if.wr_slv s_axil_ctrl_wr, + taxi_axil_if.rd_slv s_axil_ctrl_rd, + + /* + * Datapath control register interface + */ + taxi_apb_if.slv s_apb_dp_ctrl, + /* * DMA */ @@ -27,23 +38,189 @@ module cndm_micro_desc_rd taxi_dma_desc_if.sts_snk dma_rd_desc_sts, taxi_dma_ram_if.wr_slv dma_ram_wr, - input wire logic txq_en, - input wire logic [3:0] txq_size, - input wire logic [63:0] txq_base_addr, - input wire logic [15:0] txq_prod, - output wire logic [15:0] txq_cons, - input wire logic rxq_en, - input wire logic [3:0] rxq_size, - input wire logic [63:0] rxq_base_addr, - input wire logic [15:0] rxq_prod, - output wire logic [15:0] rxq_cons, - input wire logic [1:0] desc_req, taxi_axis_if.src axis_desc[2] ); +localparam AXIL_ADDR_W = s_axil_ctrl_wr.ADDR_W; +localparam AXIL_DATA_W = s_axil_ctrl_wr.DATA_W; + +localparam APB_ADDR_W = s_apb_dp_ctrl.ADDR_W; +localparam APB_DATA_W = s_apb_dp_ctrl.DATA_W; + localparam RAM_ADDR_W = 16; +logic txq_en_reg = '0; +logic [3:0] txq_size_reg = '0; +logic [63:0] txq_base_addr_reg = '0; +logic [15:0] txq_prod_reg = '0; +logic rxq_en_reg = '0; +logic [3:0] rxq_size_reg = '0; +logic [63:0] rxq_base_addr_reg = '0; +logic [15:0] rxq_prod_reg = '0; + +logic [15:0] txq_cons_ptr_reg = '0; +logic [15:0] rxq_cons_ptr_reg = '0; + +logic s_axil_ctrl_awready_reg = 1'b0; +logic s_axil_ctrl_wready_reg = 1'b0; +logic s_axil_ctrl_bvalid_reg = 1'b0; + +logic s_axil_ctrl_arready_reg = 1'b0; +logic [AXIL_DATA_W-1:0] s_axil_ctrl_rdata_reg = '0; +logic s_axil_ctrl_rvalid_reg = 1'b0; + +assign s_axil_ctrl_wr.awready = s_axil_ctrl_awready_reg; +assign s_axil_ctrl_wr.wready = s_axil_ctrl_wready_reg; +assign s_axil_ctrl_wr.bresp = '0; +assign s_axil_ctrl_wr.buser = '0; +assign s_axil_ctrl_wr.bvalid = s_axil_ctrl_bvalid_reg; + +assign s_axil_ctrl_rd.arready = s_axil_ctrl_arready_reg; +assign s_axil_ctrl_rd.rdata = s_axil_ctrl_rdata_reg; +assign s_axil_ctrl_rd.rresp = '0; +assign s_axil_ctrl_rd.ruser = '0; +assign s_axil_ctrl_rd.rvalid = s_axil_ctrl_rvalid_reg; + +logic s_apb_dp_ctrl_pready_reg = 1'b0; +logic [AXIL_DATA_W-1:0] s_apb_dp_ctrl_prdata_reg = '0; + +assign s_apb_dp_ctrl.pready = s_apb_dp_ctrl_pready_reg; +assign s_apb_dp_ctrl.prdata = s_apb_dp_ctrl_prdata_reg; +assign s_apb_dp_ctrl.pslverr = 1'b0; +assign s_apb_dp_ctrl.pruser = '0; +assign s_apb_dp_ctrl.pbuser = '0; + +always_ff @(posedge clk) begin + s_axil_ctrl_awready_reg <= 1'b0; + s_axil_ctrl_wready_reg <= 1'b0; + s_axil_ctrl_bvalid_reg <= s_axil_ctrl_bvalid_reg && !s_axil_ctrl_wr.bready; + + s_axil_ctrl_arready_reg <= 1'b0; + s_axil_ctrl_rvalid_reg <= s_axil_ctrl_rvalid_reg && !s_axil_ctrl_rd.rready; + + s_apb_dp_ctrl_pready_reg <= 1'b0; + + if (s_axil_ctrl_wr.awvalid && s_axil_ctrl_wr.wvalid && !s_axil_ctrl_bvalid_reg) begin + s_axil_ctrl_awready_reg <= 1'b1; + s_axil_ctrl_wready_reg <= 1'b1; + s_axil_ctrl_bvalid_reg <= 1'b1; + + case ({s_axil_ctrl_wr.awaddr[9:2], 2'b00}) + // 10'h000: begin + // txq_en_reg <= s_axil_ctrl_wr.wdata[0]; + // txq_size_reg <= s_axil_ctrl_wr.wdata[19:16]; + // end + 10'h004: txq_prod_reg <= s_axil_ctrl_wr.wdata[15:0]; + // 10'h008: txq_base_addr_reg[31:0] <= s_axil_ctrl_wr.wdata; + // 10'h00c: txq_base_addr_reg[63:32] <= s_axil_ctrl_wr.wdata; + + // 10'h100: begin + // rxq_en_reg <= s_axil_ctrl_wr.wdata[0]; + // rxq_size_reg <= s_axil_ctrl_wr.wdata[19:16]; + // end + 10'h104: rxq_prod_reg <= s_axil_ctrl_wr.wdata[15:0]; + // 10'h108: rxq_base_addr_reg[31:0] <= s_axil_ctrl_wr.wdata; + // 10'h10c: rxq_base_addr_reg[63:32] <= s_axil_ctrl_wr.wdata; + default: begin end + endcase + end + + if (s_axil_ctrl_rd.arvalid && !s_axil_ctrl_rvalid_reg) begin + s_axil_ctrl_rdata_reg <= '0; + + s_axil_ctrl_arready_reg <= 1'b1; + s_axil_ctrl_rvalid_reg <= 1'b1; + + // case ({s_axil_ctrl_rd.araddr[9:2], 2'b00}) + // 10'h000: begin + // s_axil_ctrl_rdata_reg[0] <= txq_en_reg; + // s_axil_ctrl_rdata_reg[19:16] <= txq_size_reg; + // end + // 10'h004: begin + // s_axil_ctrl_rdata_reg[15:0] <= txq_prod_reg; + // s_axil_ctrl_rdata_reg[31:16] <= txq_cons_ptr_reg; + // end + // 10'h008: s_axil_ctrl_rdata_reg <= txq_base_addr_reg[31:0]; + // 10'h00c: s_axil_ctrl_rdata_reg <= txq_base_addr_reg[63:32]; + + // 10'h100: begin + // s_axil_ctrl_rdata_reg[0] <= rxq_en_reg; + // s_axil_ctrl_rdata_reg[19:16] <= rxq_size_reg; + // end + // 10'h104: begin + // s_axil_ctrl_rdata_reg[15:0] <= rxq_prod_reg; + // s_axil_ctrl_rdata_reg[31:16] <= rxq_cons_ptr_reg; + // end + // 10'h108: s_axil_ctrl_rdata_reg <= rxq_base_addr_reg[31:0]; + // 10'h10c: s_axil_ctrl_rdata_reg <= rxq_base_addr_reg[63:32]; + // default: begin end + // endcase + end + + if (s_apb_dp_ctrl.penable && s_apb_dp_ctrl.psel && !s_apb_dp_ctrl_pready_reg) begin + s_apb_dp_ctrl_pready_reg <= 1'b1; + s_apb_dp_ctrl_prdata_reg <= '0; + + if (s_apb_dp_ctrl.pwrite) begin + case ({s_apb_dp_ctrl.paddr[9:2], 2'b00}) + 10'h000: begin + txq_en_reg <= s_apb_dp_ctrl.pwdata[0]; + txq_size_reg <= s_apb_dp_ctrl.pwdata[19:16]; + end + 10'h004: txq_prod_reg <= s_apb_dp_ctrl.pwdata[15:0]; + 10'h008: txq_base_addr_reg[31:0] <= s_apb_dp_ctrl.pwdata; + 10'h00c: txq_base_addr_reg[63:32] <= s_apb_dp_ctrl.pwdata; + + 10'h100: begin + rxq_en_reg <= s_apb_dp_ctrl.pwdata[0]; + rxq_size_reg <= s_apb_dp_ctrl.pwdata[19:16]; + end + 10'h104: rxq_prod_reg <= s_apb_dp_ctrl.pwdata[15:0]; + 10'h108: rxq_base_addr_reg[31:0] <= s_apb_dp_ctrl.pwdata; + 10'h10c: rxq_base_addr_reg[63:32] <= s_apb_dp_ctrl.pwdata; + default: begin end + endcase + end + + case ({s_apb_dp_ctrl.paddr[9:2], 2'b00}) + 10'h000: begin + s_apb_dp_ctrl_prdata_reg[0] <= txq_en_reg; + s_apb_dp_ctrl_prdata_reg[19:16] <= txq_size_reg; + end + 10'h004: begin + s_apb_dp_ctrl_prdata_reg[15:0] <= txq_prod_reg; + s_apb_dp_ctrl_prdata_reg[31:16] <= txq_cons_ptr_reg; + end + 10'h008: s_apb_dp_ctrl_prdata_reg <= txq_base_addr_reg[31:0]; + 10'h00c: s_apb_dp_ctrl_prdata_reg <= txq_base_addr_reg[63:32]; + + 10'h100: begin + s_apb_dp_ctrl_prdata_reg[0] <= rxq_en_reg; + s_apb_dp_ctrl_prdata_reg[19:16] <= rxq_size_reg; + end + 10'h104: begin + s_apb_dp_ctrl_prdata_reg[15:0] <= rxq_prod_reg; + s_apb_dp_ctrl_prdata_reg[31:16] <= rxq_cons_ptr_reg; + end + 10'h108: s_apb_dp_ctrl_prdata_reg <= rxq_base_addr_reg[31:0]; + 10'h10c: s_apb_dp_ctrl_prdata_reg <= rxq_base_addr_reg[63:32]; + default: begin end + endcase + end + + if (rst) begin + s_axil_ctrl_awready_reg <= 1'b0; + s_axil_ctrl_wready_reg <= 1'b0; + s_axil_ctrl_bvalid_reg <= 1'b0; + + s_axil_ctrl_arready_reg <= 1'b0; + s_axil_ctrl_rvalid_reg <= 1'b0; + + s_apb_dp_ctrl_pready_reg <= 1'b0; + end +end + taxi_dma_desc_if #( .SRC_ADDR_W(RAM_ADDR_W), .SRC_SEL_EN(1'b0), @@ -72,12 +249,6 @@ state_t state_reg = STATE_IDLE; logic [1:0] desc_req_reg = '0; -logic [15:0] txq_cons_ptr_reg = '0; -logic [15:0] rxq_cons_ptr_reg = '0; - -assign txq_cons = txq_cons_ptr_reg; -assign rxq_cons = rxq_cons_ptr_reg; - always_ff @(posedge clk) begin // axis_desc.tready <= 1'b0; @@ -109,21 +280,21 @@ always_ff @(posedge clk) begin desc_req_reg <= desc_req_reg | desc_req; - if (!txq_en) begin + if (!txq_en_reg) begin txq_cons_ptr_reg <= '0; end - if (!rxq_en) begin + if (!rxq_en_reg) begin rxq_cons_ptr_reg <= '0; end case (state_reg) STATE_IDLE: begin if (desc_req_reg[1]) begin - dma_rd_desc_req.req_src_addr <= rxq_base_addr + 64'(16'(rxq_cons_ptr_reg & ({16{1'b1}} >> (16 - rxq_size))) * 16); + dma_rd_desc_req.req_src_addr <= rxq_base_addr_reg + 64'(16'(rxq_cons_ptr_reg & ({16{1'b1}} >> (16 - rxq_size_reg))) * 16); dma_desc.req_dest <= 1'b1; desc_req_reg[1] <= 1'b0; - if (rxq_cons_ptr_reg == rxq_prod || !rxq_en) begin + if (rxq_cons_ptr_reg == rxq_prod_reg || !rxq_en_reg) begin dma_desc.req_user <= 1'b1; dma_desc.req_valid <= 1'b1; state_reg <= STATE_TX_DESC; @@ -134,10 +305,10 @@ always_ff @(posedge clk) begin state_reg <= STATE_READ_DESC; end end else if (desc_req_reg[0]) begin - dma_rd_desc_req.req_src_addr <= txq_base_addr + 64'(16'(txq_cons_ptr_reg & ({16{1'b1}} >> (16 - txq_size))) * 16); + dma_rd_desc_req.req_src_addr <= txq_base_addr_reg + 64'(16'(txq_cons_ptr_reg & ({16{1'b1}} >> (16 - txq_size_reg))) * 16); dma_desc.req_dest <= 1'b0; desc_req_reg[0] <= 1'b0; - if (txq_cons_ptr_reg == txq_prod || !txq_en) begin + if (txq_cons_ptr_reg == txq_prod_reg || !txq_en_reg) begin dma_desc.req_user <= 1'b1; dma_desc.req_valid <= 1'b1; state_reg <= STATE_TX_DESC; diff --git a/src/cndm/rtl/cndm_micro_dp_mgr.sv b/src/cndm/rtl/cndm_micro_dp_mgr.sv index 6b3de1e..6c0a920 100644 --- a/src/cndm/rtl/cndm_micro_dp_mgr.sv +++ b/src/cndm/rtl/cndm_micro_dp_mgr.sv @@ -248,8 +248,8 @@ always_comb begin CMD_OP_DESTROY_EQ: begin // EQ - dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0000) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); - host_ptr_next = 32'({port_reg, 16'd0} | 'h0000) + PORT_BASE_ADDR_HOST; + dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h8000) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); + host_ptr_next = 32'({port_reg, 16'd0} | 'h8000) + PORT_BASE_ADDR_HOST; end CMD_OP_CREATE_CQ, CMD_OP_MODIFY_CQ, @@ -258,11 +258,11 @@ always_comb begin begin // CQ if (qn_reg[0]) begin - dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0300) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); - host_ptr_next = 32'({port_reg, 16'd0} | 'h0300) + PORT_BASE_ADDR_HOST; + dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h8000) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); + host_ptr_next = 32'({port_reg, 16'd0} | 'h8000) + PORT_BASE_ADDR_HOST; end else begin - dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0400) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); - host_ptr_next = 32'({port_reg, 16'd0} | 'h0400) + PORT_BASE_ADDR_HOST; + dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h8100) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); + host_ptr_next = 32'({port_reg, 16'd0} | 'h8100) + PORT_BASE_ADDR_HOST; end end CMD_OP_CREATE_SQ, @@ -271,8 +271,8 @@ always_comb begin CMD_OP_DESTROY_SQ: begin // SQ - dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0100) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); - host_ptr_next = 32'({port_reg, 16'd0} | 'h0100) + PORT_BASE_ADDR_HOST; + dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0000) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); + host_ptr_next = 32'({port_reg, 16'd0} | 'h0000) + PORT_BASE_ADDR_HOST; end CMD_OP_CREATE_RQ, CMD_OP_MODIFY_RQ, @@ -280,8 +280,8 @@ always_comb begin CMD_OP_DESTROY_RQ: begin // RQ - dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0200) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); - host_ptr_next = 32'({port_reg, 16'd0} | 'h0200) + PORT_BASE_ADDR_HOST; + dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0100) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); + host_ptr_next = 32'({port_reg, 16'd0} | 'h0100) + PORT_BASE_ADDR_HOST; end default: begin end endcase diff --git a/src/cndm/rtl/cndm_micro_port.sv b/src/cndm/rtl/cndm_micro_port.sv index 2aa1785..97f5d87 100644 --- a/src/cndm/rtl/cndm_micro_port.sv +++ b/src/cndm/rtl/cndm_micro_port.sv @@ -75,244 +75,76 @@ localparam RAM_SEG_DATA_W = dma_ram_wr.SEG_DATA_W; localparam RAM_SEG_BE_W = dma_ram_wr.SEG_BE_W; localparam RAM_SEL_W = dma_ram_wr.SEL_W; -logic txq_en_reg = '0; -logic [3:0] txq_size_reg = '0; -logic [63:0] txq_base_addr_reg = '0; -logic [15:0] txq_prod_reg = '0; -wire [15:0] txq_cons; -logic rxq_en_reg = '0; -logic [3:0] rxq_size_reg = '0; -logic [63:0] rxq_base_addr_reg = '0; -logic [15:0] rxq_prod_reg = '0; -wire [15:0] rxq_cons; +taxi_axil_if #( + .DATA_W(s_axil_ctrl_wr.DATA_W), + .ADDR_W(15), + .STRB_W(s_axil_ctrl_wr.STRB_W), + .AWUSER_EN(s_axil_ctrl_wr.AWUSER_EN), + .AWUSER_W(s_axil_ctrl_wr.AWUSER_W), + .WUSER_EN(s_axil_ctrl_wr.WUSER_EN), + .WUSER_W(s_axil_ctrl_wr.WUSER_W), + .BUSER_EN(s_axil_ctrl_wr.BUSER_EN), + .BUSER_W(s_axil_ctrl_wr.BUSER_W), + .ARUSER_EN(s_axil_ctrl_wr.ARUSER_EN), + .ARUSER_W(s_axil_ctrl_wr.ARUSER_W), + .RUSER_EN(s_axil_ctrl_wr.RUSER_EN), + .RUSER_W(s_axil_ctrl_wr.RUSER_W) +) +axil_ctrl[2](); -logic txcq_en_reg = '0; -logic [3:0] txcq_size_reg = '0; -logic [63:0] txcq_base_addr_reg = '0; -wire [15:0] txcq_prod; -logic rxcq_en_reg = '0; -logic [3:0] rxcq_size_reg = '0; -logic [63:0] rxcq_base_addr_reg = '0; -wire [15:0] rxcq_prod; +taxi_axil_interconnect_1s #( + .M_COUNT($size(axil_ctrl)), + .ADDR_W(s_axil_ctrl_wr.ADDR_W), + .M_REGIONS(1), + .M_BASE_ADDR('0), + .M_ADDR_W({$size(axil_ctrl){{1{32'd15}}}}), + .M_SECURE({$size(axil_ctrl){1'b0}}) +) +port_intercon_inst ( + .clk(clk), + .rst(rst), -logic s_axil_ctrl_awready_reg = 1'b0; -logic s_axil_ctrl_wready_reg = 1'b0; -logic s_axil_ctrl_bvalid_reg = 1'b0; + /* + * AXI4-lite slave interface + */ + .s_axil_wr(s_axil_ctrl_wr), + .s_axil_rd(s_axil_ctrl_rd), -logic s_axil_ctrl_arready_reg = 1'b0; -logic [AXIL_DATA_W-1:0] s_axil_ctrl_rdata_reg = '0; -logic s_axil_ctrl_rvalid_reg = 1'b0; + /* + * AXI4-lite master interfaces + */ + .m_axil_wr(axil_ctrl), + .m_axil_rd(axil_ctrl) +); -assign s_axil_ctrl_wr.awready = s_axil_ctrl_awready_reg; -assign s_axil_ctrl_wr.wready = s_axil_ctrl_wready_reg; -assign s_axil_ctrl_wr.bresp = '0; -assign s_axil_ctrl_wr.buser = '0; -assign s_axil_ctrl_wr.bvalid = s_axil_ctrl_bvalid_reg; +taxi_apb_if #( + .DATA_W(32), + .ADDR_W(15) +) +apb_dp_ctrl[2](); -assign s_axil_ctrl_rd.arready = s_axil_ctrl_arready_reg; -assign s_axil_ctrl_rd.rdata = s_axil_ctrl_rdata_reg; -assign s_axil_ctrl_rd.rresp = '0; -assign s_axil_ctrl_rd.ruser = '0; -assign s_axil_ctrl_rd.rvalid = s_axil_ctrl_rvalid_reg; +taxi_apb_interconnect #( + .M_CNT($size(apb_dp_ctrl)), + .ADDR_W(s_apb_dp_ctrl.ADDR_W), + .M_REGIONS(1), + .M_BASE_ADDR('0), + .M_ADDR_W({$size(apb_dp_ctrl){{1{32'd15}}}}), + .M_SECURE({$size(apb_dp_ctrl){1'b0}}) +) +port_dp_intercon_inst ( + .clk(clk), + .rst(rst), -logic s_apb_dp_ctrl_pready_reg = 1'b0; -logic [AXIL_DATA_W-1:0] s_apb_dp_ctrl_prdata_reg = '0; + /* + * APB slave interface + */ + .s_apb(s_apb_dp_ctrl), -assign s_apb_dp_ctrl.pready = s_apb_dp_ctrl_pready_reg; -assign s_apb_dp_ctrl.prdata = s_apb_dp_ctrl_prdata_reg; -assign s_apb_dp_ctrl.pslverr = 1'b0; -assign s_apb_dp_ctrl.pruser = '0; -assign s_apb_dp_ctrl.pbuser = '0; - -always_ff @(posedge clk) begin - s_axil_ctrl_awready_reg <= 1'b0; - s_axil_ctrl_wready_reg <= 1'b0; - s_axil_ctrl_bvalid_reg <= s_axil_ctrl_bvalid_reg && !s_axil_ctrl_wr.bready; - - s_axil_ctrl_arready_reg <= 1'b0; - s_axil_ctrl_rvalid_reg <= s_axil_ctrl_rvalid_reg && !s_axil_ctrl_rd.rready; - - s_apb_dp_ctrl_pready_reg <= 1'b0; - - if (s_axil_ctrl_wr.awvalid && s_axil_ctrl_wr.wvalid && !s_axil_ctrl_bvalid_reg) begin - s_axil_ctrl_awready_reg <= 1'b1; - s_axil_ctrl_wready_reg <= 1'b1; - s_axil_ctrl_bvalid_reg <= 1'b1; - - case ({s_axil_ctrl_wr.awaddr[15:2], 2'b00}) - 16'h0100: begin - txq_en_reg <= s_axil_ctrl_wr.wdata[0]; - txq_size_reg <= s_axil_ctrl_wr.wdata[19:16]; - end - 16'h0104: txq_prod_reg <= s_axil_ctrl_wr.wdata[15:0]; - 16'h0108: txq_base_addr_reg[31:0] <= s_axil_ctrl_wr.wdata; - 16'h010c: txq_base_addr_reg[63:32] <= s_axil_ctrl_wr.wdata; - - 16'h0200: begin - rxq_en_reg <= s_axil_ctrl_wr.wdata[0]; - rxq_size_reg <= s_axil_ctrl_wr.wdata[19:16]; - end - 16'h0204: rxq_prod_reg <= s_axil_ctrl_wr.wdata[15:0]; - 16'h0208: rxq_base_addr_reg[31:0] <= s_axil_ctrl_wr.wdata; - 16'h020c: rxq_base_addr_reg[63:32] <= s_axil_ctrl_wr.wdata; - - 16'h0300: begin - txcq_en_reg <= s_axil_ctrl_wr.wdata[0]; - txcq_size_reg <= s_axil_ctrl_wr.wdata[19:16]; - end - 16'h0308: txcq_base_addr_reg[31:0] <= s_axil_ctrl_wr.wdata; - 16'h030c: txcq_base_addr_reg[63:32] <= s_axil_ctrl_wr.wdata; - - 16'h0400: begin - rxcq_en_reg <= s_axil_ctrl_wr.wdata[0]; - rxcq_size_reg <= s_axil_ctrl_wr.wdata[19:16]; - end - 16'h0408: rxcq_base_addr_reg[31:0] <= s_axil_ctrl_wr.wdata; - 16'h040c: rxcq_base_addr_reg[63:32] <= s_axil_ctrl_wr.wdata; - default: begin end - endcase - end - - if (s_axil_ctrl_rd.arvalid && !s_axil_ctrl_rvalid_reg) begin - s_axil_ctrl_rdata_reg <= '0; - - s_axil_ctrl_arready_reg <= 1'b1; - s_axil_ctrl_rvalid_reg <= 1'b1; - - case ({s_axil_ctrl_rd.araddr[15:2], 2'b00}) - 16'h0100: begin - s_axil_ctrl_rdata_reg[0] <= txq_en_reg; - s_axil_ctrl_rdata_reg[19:16] <= txq_size_reg; - end - 16'h0104: begin - s_axil_ctrl_rdata_reg[15:0] <= txq_prod_reg; - s_axil_ctrl_rdata_reg[31:16] <= txq_cons; - end - 16'h0108: s_axil_ctrl_rdata_reg <= txq_base_addr_reg[31:0]; - 16'h010c: s_axil_ctrl_rdata_reg <= txq_base_addr_reg[63:32]; - - 16'h0200: begin - s_axil_ctrl_rdata_reg[0] <= rxq_en_reg; - s_axil_ctrl_rdata_reg[19:16] <= rxq_size_reg; - end - 16'h0204: begin - s_axil_ctrl_rdata_reg[15:0] <= rxq_prod_reg; - s_axil_ctrl_rdata_reg[31:16] <= rxq_cons; - end - 16'h0208: s_axil_ctrl_rdata_reg <= rxq_base_addr_reg[31:0]; - 16'h020c: s_axil_ctrl_rdata_reg <= rxq_base_addr_reg[63:32]; - - 16'h0300: begin - s_axil_ctrl_rdata_reg[0] <= txcq_en_reg; - s_axil_ctrl_rdata_reg[19:16] <= txcq_size_reg; - end - 16'h0304: s_axil_ctrl_rdata_reg[15:0] <= txcq_prod; - 16'h0308: s_axil_ctrl_rdata_reg <= txcq_base_addr_reg[31:0]; - 16'h030c: s_axil_ctrl_rdata_reg <= txcq_base_addr_reg[63:32]; - - 16'h0400: begin - s_axil_ctrl_rdata_reg[0] <= rxcq_en_reg; - s_axil_ctrl_rdata_reg[19:16] <= rxcq_size_reg; - end - 16'h0404: s_axil_ctrl_rdata_reg[15:0] <= rxcq_prod; - 16'h0408: s_axil_ctrl_rdata_reg <= rxcq_base_addr_reg[31:0]; - 16'h040c: s_axil_ctrl_rdata_reg <= rxcq_base_addr_reg[63:32]; - default: begin end - endcase - end - - if (s_apb_dp_ctrl.penable && s_apb_dp_ctrl.psel && !s_apb_dp_ctrl_pready_reg) begin - s_apb_dp_ctrl_pready_reg <= 1'b1; - s_apb_dp_ctrl_prdata_reg <= '0; - - if (s_apb_dp_ctrl.pwrite) begin - case ({s_apb_dp_ctrl.paddr[15:2], 2'b00}) - 16'h0100: begin - txq_en_reg <= s_apb_dp_ctrl.pwdata[0]; - txq_size_reg <= s_apb_dp_ctrl.pwdata[19:16]; - end - 16'h0104: txq_prod_reg <= s_apb_dp_ctrl.pwdata[15:0]; - 16'h0108: txq_base_addr_reg[31:0] <= s_apb_dp_ctrl.pwdata; - 16'h010c: txq_base_addr_reg[63:32] <= s_apb_dp_ctrl.pwdata; - - 16'h0200: begin - rxq_en_reg <= s_apb_dp_ctrl.pwdata[0]; - rxq_size_reg <= s_apb_dp_ctrl.pwdata[19:16]; - end - 16'h0204: rxq_prod_reg <= s_apb_dp_ctrl.pwdata[15:0]; - 16'h0208: rxq_base_addr_reg[31:0] <= s_apb_dp_ctrl.pwdata; - 16'h020c: rxq_base_addr_reg[63:32] <= s_apb_dp_ctrl.pwdata; - - 16'h0300: begin - txcq_en_reg <= s_apb_dp_ctrl.pwdata[0]; - txcq_size_reg <= s_apb_dp_ctrl.pwdata[19:16]; - end - 16'h0308: txcq_base_addr_reg[31:0] <= s_apb_dp_ctrl.pwdata; - 16'h030c: txcq_base_addr_reg[63:32] <= s_apb_dp_ctrl.pwdata; - - 16'h0400: begin - rxcq_en_reg <= s_apb_dp_ctrl.pwdata[0]; - rxcq_size_reg <= s_apb_dp_ctrl.pwdata[19:16]; - end - 16'h0408: rxcq_base_addr_reg[31:0] <= s_apb_dp_ctrl.pwdata; - 16'h040c: rxcq_base_addr_reg[63:32] <= s_apb_dp_ctrl.pwdata; - default: begin end - endcase - end - - case ({s_apb_dp_ctrl.paddr[15:2], 2'b00}) - 16'h0100: begin - s_apb_dp_ctrl_prdata_reg[0] <= txq_en_reg; - s_apb_dp_ctrl_prdata_reg[19:16] <= txq_size_reg; - end - 16'h0104: begin - s_apb_dp_ctrl_prdata_reg[15:0] <= txq_prod_reg; - s_apb_dp_ctrl_prdata_reg[31:16] <= txq_cons; - end - 16'h0108: s_apb_dp_ctrl_prdata_reg <= txq_base_addr_reg[31:0]; - 16'h010c: s_apb_dp_ctrl_prdata_reg <= txq_base_addr_reg[63:32]; - - 16'h0200: begin - s_apb_dp_ctrl_prdata_reg[0] <= rxq_en_reg; - s_apb_dp_ctrl_prdata_reg[19:16] <= rxq_size_reg; - end - 16'h0204: begin - s_apb_dp_ctrl_prdata_reg[15:0] <= rxq_prod_reg; - s_apb_dp_ctrl_prdata_reg[31:16] <= rxq_cons; - end - 16'h0208: s_apb_dp_ctrl_prdata_reg <= rxq_base_addr_reg[31:0]; - 16'h020c: s_apb_dp_ctrl_prdata_reg <= rxq_base_addr_reg[63:32]; - - 16'h0300: begin - s_apb_dp_ctrl_prdata_reg[0] <= txcq_en_reg; - s_apb_dp_ctrl_prdata_reg[19:16] <= txcq_size_reg; - end - 16'h0304: s_apb_dp_ctrl_prdata_reg[15:0] <= txcq_prod; - 16'h0308: s_apb_dp_ctrl_prdata_reg <= txcq_base_addr_reg[31:0]; - 16'h030c: s_apb_dp_ctrl_prdata_reg <= txcq_base_addr_reg[63:32]; - - 16'h0400: begin - s_apb_dp_ctrl_prdata_reg[0] <= rxcq_en_reg; - s_apb_dp_ctrl_prdata_reg[19:16] <= rxcq_size_reg; - end - 16'h0404: s_apb_dp_ctrl_prdata_reg[15:0] <= rxcq_prod; - 16'h0408: s_apb_dp_ctrl_prdata_reg <= rxcq_base_addr_reg[31:0]; - 16'h040c: s_apb_dp_ctrl_prdata_reg <= rxcq_base_addr_reg[63:32]; - default: begin end - endcase - end - - if (rst) begin - s_axil_ctrl_awready_reg <= 1'b0; - s_axil_ctrl_wready_reg <= 1'b0; - s_axil_ctrl_bvalid_reg <= 1'b0; - - s_axil_ctrl_arready_reg <= 1'b0; - s_axil_ctrl_rvalid_reg <= 1'b0; - - s_apb_dp_ctrl_pready_reg <= 1'b0; - end -end + /* + * APB master interfaces + */ + .m_apb(apb_dp_ctrl) +); taxi_dma_desc_if #( .SRC_ADDR_W(dma_rd_desc_req.SRC_ADDR_W), @@ -455,6 +287,17 @@ desc_rd_inst ( .clk(clk), .rst(rst), + /* + * Control register interface + */ + .s_axil_ctrl_wr(axil_ctrl[0]), + .s_axil_ctrl_rd(axil_ctrl[0]), + + /* + * Datapath control register interface + */ + .s_apb_dp_ctrl(apb_dp_ctrl[0]), + /* * DMA */ @@ -462,17 +305,6 @@ desc_rd_inst ( .dma_rd_desc_sts(dma_rd_desc_int[0]), .dma_ram_wr(dma_ram_wr_int[0]), - .txq_en(txq_en_reg), - .txq_size(txq_size_reg), - .txq_base_addr(txq_base_addr_reg), - .txq_prod(txq_prod_reg), - .txq_cons(txq_cons), - .rxq_en(rxq_en_reg), - .rxq_size(rxq_size_reg), - .rxq_base_addr(rxq_base_addr_reg), - .rxq_prod(rxq_prod_reg), - .rxq_cons(rxq_cons), - .desc_req(desc_req), .axis_desc(axis_desc) ); @@ -482,6 +314,17 @@ cpl_wr_inst ( .clk(clk), .rst(rst), + /* + * Control register interface + */ + .s_axil_ctrl_wr(axil_ctrl[1]), + .s_axil_ctrl_rd(axil_ctrl[1]), + + /* + * Datapath control register interface + */ + .s_apb_dp_ctrl(apb_dp_ctrl[1]), + /* * DMA */ @@ -489,15 +332,6 @@ cpl_wr_inst ( .dma_wr_desc_sts(dma_wr_desc_int[0]), .dma_ram_rd(dma_ram_rd_int[0]), - .txcq_en(txcq_en_reg), - .txcq_size(txcq_size_reg), - .txcq_base_addr(txcq_base_addr_reg), - .txcq_prod(txcq_prod), - .rxcq_en(rxcq_en_reg), - .rxcq_size(rxcq_size_reg), - .rxcq_base_addr(rxcq_base_addr_reg), - .rxcq_prod(rxcq_prod), - .axis_cpl(axis_cpl), .irq(irq) );