mirror of
https://github.com/fpganinja/taxi.git
synced 2025-12-07 16:28:40 -08:00
eth: Add Ethernet example design for VC709
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
@@ -172,6 +172,7 @@ Example designs are provided for several different FPGA boards, showcasing many
|
||||
* Xilinx KC705 (Xilinx Kintex 7 XC7K325T)
|
||||
* Xilinx KCU105 (Xilinx Kintex UltraScale XCKU040)
|
||||
* Xilinx Kria KR260 (Xilinx Kria K26 SoM / Zynq UltraScale+ XCK26)
|
||||
* Xilinx VC709 (Xilinx Virtex 7 XC7V690T)
|
||||
* Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095)
|
||||
* Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P)
|
||||
* Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P)
|
||||
|
||||
Reference in New Issue
Block a user