bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2026-04-08 04:58:43 -07:00
Code Issues Packages Projects Releases Wiki Activity

math: Add MT19937 Mersenne Twister PRNG module and testbench

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-10-15 22:14:21 -07:00
parent 7ec62b6b47
commit 4e099af53a
10 changed files with 794 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

116
src/math/tb/mt19937.py Normal file
View File

@@ -0,0 +1,116 @@
#!/usr/bin/env python3
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2014-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
This is a python implementation of MT19937 from
http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/MT2002/emt19937ar.html
http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/MT2002/CODES/mt19937ar.c
"""
class mt19937(object):
def __init__(self):
self.mt = [0]*624
self.mti = 625
def seed(self, seed):
self.mt[0] = seed & 0xffffffff
for i in range(1,624):
self.mt[i] = (1812433253 * (self.mt[i-1] ^ (self.mt[i-1] >> 30)) + i) & 0xffffffff
self.mti = 624
def init_by_array(self, key):
self.seed(19650218)
i = 1
j = 0
k = max(624, len(key))
for ki in range(k):
self.mt[i] = ((self.mt[i] ^ ((self.mt[i-1] ^ (self.mt[i-1] >> 30)) * 1664525)) + key[j] + j) & 0xffffffff
i += 1
j += 1
if i >= 624:
self.mt[0] = self.mt[623]
i = 1
if j >= len(key):
j = 0
for ki in range(624):
self.mt[i] = ((self.mt[i] ^ ((self.mt[i-1] ^ (self.mt[i-1] >> 30)) * 1566083941)) - i) & 0xffffffff
i += 1
if i >= 624:
self.mt[0] = self.mt[623]
i = 1
self.mt[0] = 0x80000000
def int32(self):
if self.mti >= 624:
if self.mti == 625:
self.seed(5489)
for k in range(623):
y = (self.mt[k] & 0x80000000) | (self.mt[k+1] & 0x7fffffff)
if k < 624 - 397:
self.mt[k] = self.mt[k+397] ^ (y >> 1) ^ (0x9908b0df if y & 1 else 0)
else:
self.mt[k] = self.mt[k+397-624] ^ (y >> 1) ^ (0x9908b0df if y & 1 else 0)
y = (self.mt[623] & 0x80000000) | (self.mt[0] & 0x7fffffff)
self.mt[623] = self.mt[396] ^ (y >> 1) ^ (0x9908b0df if y & 1 else 0)
self.mti = 0
y = self.mt[self.mti]
self.mti += 1
y ^= (y >> 11)
y ^= (y << 7) & 0x9d2c5680
y ^= (y << 15) & 0xefc60000
y ^= (y >> 18)
return y
def int32b(self):
if self.mti == 625:
self.seed(5489)
k = self.mti
if k == 624:
k = 0
self.mti = 0
if k == 623:
y = (self.mt[623] & 0x80000000) | (self.mt[0] & 0x7fffffff)
self.mt[623] = self.mt[396] ^ (y >> 1) ^ (0x9908b0df if y & 1 else 0)
else:
y = (self.mt[k] & 0x80000000) | (self.mt[k+1] & 0x7fffffff)
if k < 624 - 397:
self.mt[k] = self.mt[k+397] ^ (y >> 1) ^ (0x9908b0df if y & 1 else 0)
else:
self.mt[k] = self.mt[k+397-624] ^ (y >> 1) ^ (0x9908b0df if y & 1 else 0)
y = self.mt[self.mti]
self.mti += 1
y ^= (y >> 11)
y ^= (y << 7) & 0x9d2c5680
y ^= (y << 15) & 0xefc60000
y ^= (y >> 18)
return y
if __name__ == '__main__':
mt = mt19937()
mt.init_by_array([0x123, 0x234, 0x345, 0x456])
print("1000 outputs of int32")
s=''
for i in range(1000):
s += "%10lu " % mt.int32()
if i % 5 == 4:
print(s)
s = ''
if len(s) > 0:
print(s)

116
src/math/tb/mt19937_64.py Normal file
View File

@@ -0,0 +1,116 @@
#!/usr/bin/env python3
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2014-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
This is a python implementation of MT19937-64 from
http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/emt64.html
http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/VERSIONS/C-LANG/mt19937-64.c
"""
class mt19937_64(object):
def __init__(self):
self.mt = [0]*312
self.mti = 313
def seed(self, seed):
self.mt[0] = seed & 0xffffffffffffffff
for i in range(1,312):
self.mt[i] = (6364136223846793005 * (self.mt[i-1] ^ (self.mt[i-1] >> 62)) + i) & 0xffffffffffffffff
self.mti = 312
def init_by_array(self, key):
self.seed(19650218)
i = 1
j = 0
k = max(312, len(key))
for ki in range(k):
self.mt[i] = ((self.mt[i] ^ ((self.mt[i-1] ^ (self.mt[i-1] >> 62)) * 3935559000370003845)) + key[j] + j) & 0xffffffffffffffff
i += 1
j += 1
if i >= 312:
self.mt[0] = self.mt[311]
i = 1
if j >= len(key):
j = 0
for ki in range(312):
self.mt[i] = ((self.mt[i] ^ ((self.mt[i-1] ^ (self.mt[i-1] >> 62)) * 2862933555777941757)) - i) & 0xffffffffffffffff
i += 1
if i >= 312:
self.mt[0] = self.mt[311]
i = 1
self.mt[0] = 1 << 63
def int64(self):
if self.mti >= 312:
if self.mti == 313:
self.seed(5489)
for k in range(311):
y = (self.mt[k] & 0xFFFFFFFF80000000) | (self.mt[k+1] & 0x7fffffff)
if k < 312 - 156:
self.mt[k] = self.mt[k+156] ^ (y >> 1) ^ (0xB5026F5AA96619E9 if y & 1 else 0)
else:
self.mt[k] = self.mt[k+156-624] ^ (y >> 1) ^ (0xB5026F5AA96619E9 if y & 1 else 0)
y = (self.mt[311] & 0xFFFFFFFF80000000) | (self.mt[0] & 0x7fffffff)
self.mt[311] = self.mt[155] ^ (y >> 1) ^ (0xB5026F5AA96619E9 if y & 1 else 0)
self.mti = 0
y = self.mt[self.mti]
self.mti += 1
y ^= (y >> 29) & 0x5555555555555555
y ^= (y << 17) & 0x71D67FFFEDA60000
y ^= (y << 37) & 0xFFF7EEE000000000
y ^= (y >> 43)
return y
def int64b(self):
if self.mti == 313:
self.seed(5489)
k = self.mti
if k == 312:
k = 0
self.mti = 0
if k == 311:
y = (self.mt[311] & 0xFFFFFFFF80000000) | (self.mt[0] & 0x7fffffff)
self.mt[311] = self.mt[155] ^ (y >> 1) ^ (0xB5026F5AA96619E9 if y & 1 else 0)
else:
y = (self.mt[k] & 0xFFFFFFFF80000000) | (self.mt[k+1] & 0x7fffffff)
if k < 312 - 156:
self.mt[k] = self.mt[k+156] ^ (y >> 1) ^ (0xB5026F5AA96619E9 if y & 1 else 0)
else:
self.mt[k] = self.mt[k+156-624] ^ (y >> 1) ^ (0xB5026F5AA96619E9 if y & 1 else 0)
y = self.mt[self.mti]
self.mti += 1
y ^= (y >> 29) & 0x5555555555555555
y ^= (y << 17) & 0x71D67FFFEDA60000
y ^= (y << 37) & 0xFFF7EEE000000000
y ^= (y >> 43)
return y
if __name__ == '__main__':
mt = mt19937_64()
mt.init_by_array([0x12345, 0x23456, 0x34567, 0x45678])
print("1000 outputs of int64")
s=''
for i in range(1000):
s += "%10lu " % mt.int64b()
if i % 5 == 4:
print(s)
s = ''
if len(s) > 0:
print(s)

52
src/math/tb/taxi_mt19937/Makefile Normal file
View File

@@ -0,0 +1,52 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2021-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_mt19937
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_MT_W := 32
export PARAM_INIT_SEED := 5489
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

1
src/math/tb/taxi_mt19937/mt19937.py Symbolic link
View File

@@ -0,0 +1 @@
../mt19937.py

1
src/math/tb/taxi_mt19937/mt19937_64.py Symbolic link
View File

@@ -0,0 +1 @@
../mt19937_64.py

168
src/math/tb/taxi_mt19937/test_taxi_mt19937.py Normal file
View File

@@ -0,0 +1,168 @@
#!/usr/bin/env python3
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import sys
import pytest
import cocotb_test.simulator
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamSink
try:
import mt19937, mt19937_64
except ImportError:
# attempt import from current directory
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
try:
import mt19937, mt19937_64
finally:
del sys.path[0]
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
def set_backpressure_generator(self, generator=None):
if generator:
self.sink.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test(dut, seed=None, backpressure_inserter=None):
tb = TB(dut)
await tb.reset()
tb.set_backpressure_generator(backpressure_inserter)
if dut.MT_W.value == 32:
mt = mt19937.mt19937()
else:
mt = mt19937_64.mt19937_64()
if seed is not None:
mt.seed(seed)
await RisingEdge(dut.clk)
dut.seed_val.value = seed
dut.seed_start.value = 1
await RisingEdge(dut.clk)
dut.seed_start.value = 0
await RisingEdge(dut.clk)
tb.sink.clear()
for i in range(1000):
frame = await tb.sink.recv()
if dut.MT_W.value == 32:
ref = mt.int32()
else:
ref = mt.int64()
assert frame.tdata[0] == ref
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
if getattr(cocotb, 'top', None) is not None:
factory = TestFactory(run_test)
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.add_option("seed", [None, 0x12345678])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("mt_w", [32, 64])
def test_taxi_mt19937(request, mt_w):
dut = "taxi_mt19937"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.sv"),
os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['MT_W'] = mt_w
parameters['INIT_SEED'] = 5489
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

68
src/math/tb/taxi_mt19937/test_taxi_mt19937.sv Normal file
View File

@@ -0,0 +1,68 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* MT19937/MT19937-64 Mersenne Twister PRNG testbench
*/
module test_taxi_mt19937 #(
/* verilator lint_off WIDTHTRUNC */
/* verilator lint_off WIDTHEXPAND */
parameter integer MT_W = 32,
parameter logic [MT_W-1:0] INIT_SEED = 5489
/* verilator lint_on WIDTHTRUNC */
/* verilator lint_on WIDTHEXPAND */
)
();
logic clk;
logic rst;
taxi_axis_if #(
.DATA_W(MT_W),
.KEEP_W(1)
) m_axis();
wire busy;
logic [MT_W-1:0] seed_val;
logic seed_start;
taxi_mt19937 #(
.MT_W(MT_W),
.INIT_SEED(INIT_SEED)
)
uut (
.clk(clk),
.rst(rst),
/*
* AXI output (source)
*/
.m_axis(m_axis),
/*
* Status
*/
.busy(busy),
/*
* Configuration
*/
.seed_val(seed_val),
.seed_start(seed_start)
);
endmodule
`resetall