From 4e256cfe377318b220c151eccd90ef56500dbfff Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 9 Nov 2025 13:39:14 -0800 Subject: [PATCH] eth: Add support for 7-series GTX transceiver to 10G/25G MAC Signed-off-by: Alex Forencich --- src/eth/rtl/us/taxi_eth_phy_10g_7_gt.sv | 655 ++++++++++++++++++- src/eth/syn/vivado/taxi_eth_phy_10g_7_gt.tcl | 10 +- 2 files changed, 659 insertions(+), 6 deletions(-) diff --git a/src/eth/rtl/us/taxi_eth_phy_10g_7_gt.sv b/src/eth/rtl/us/taxi_eth_phy_10g_7_gt.sv index f009963..6e05a5c 100644 --- a/src/eth/rtl/us/taxi_eth_phy_10g_7_gt.sv +++ b/src/eth/rtl/us/taxi_eth_phy_10g_7_gt.sv @@ -470,7 +470,7 @@ end else if (GT_TYPE == "GTH") begin : xcvr .QPLL_VTRL_RESET (2'b00), .RCAL_CFG (2'b00) ) - gthe2_common_i + gt_common_inst ( //----------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- .DRPADDR (8'd0), @@ -834,7 +834,7 @@ end else if (GT_TYPE == "GTH") begin : xcvr .TXSYNC_OVRD (1'b0), .TXSYNC_SKIP_DA (1'b0) ) - gthe2_i + gt_ch_inst ( //------------------------------- CPLL Ports ------------------------------- .CPLLFBCLKLOST (), @@ -1187,6 +1187,657 @@ end else if (GT_TYPE == "GTH") begin : xcvr .TXQPISENP () ); +end else if (GT_TYPE == "GTX") begin : xcvr + // 7-series GTX + + if (HAS_COMMON) begin : common + + // 156.25 * 66 = 10.3125 + // 161.1328125 * 64 = 10.3125 + // 322.265625 * 32 = 10.3125 + localparam QPLL_FBDIV_TOP = 66; + + localparam QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 : + (QPLL_FBDIV_TOP == 20) ? 10'b0000110000 : + (QPLL_FBDIV_TOP == 32) ? 10'b0001100000 : + (QPLL_FBDIV_TOP == 40) ? 10'b0010000000 : + (QPLL_FBDIV_TOP == 64) ? 10'b0011100000 : + (QPLL_FBDIV_TOP == 66) ? 10'b0101000000 : + (QPLL_FBDIV_TOP == 80) ? 10'b0100100000 : + (QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000; + + localparam QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 : + (QPLL_FBDIV_TOP == 20) ? 1'b1 : + (QPLL_FBDIV_TOP == 32) ? 1'b1 : + (QPLL_FBDIV_TOP == 40) ? 1'b1 : + (QPLL_FBDIV_TOP == 64) ? 1'b1 : + (QPLL_FBDIV_TOP == 66) ? 1'b0 : + (QPLL_FBDIV_TOP == 80) ? 1'b1 : + (QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1; + + GTXE2_COMMON # + ( + // Simulation attributes + .SIM_RESET_SPEEDUP (SIM ? "TRUE" : "FALSE"), + .SIM_QPLLREFCLK_SEL (3'b001), + .SIM_VERSION ("4.0"), + //----------------COMMON BLOCK Attributes--------------- + .BIAS_CFG (64'h0000040000001000), + .COMMON_CFG (32'h00000000), + .QPLL_CFG (27'h0680181), + .QPLL_CLKOUT_CFG (4'b0000), + .QPLL_COARSE_FREQ_OVRD (6'b010000), + .QPLL_COARSE_FREQ_OVRD_EN (1'b0), + .QPLL_CP (10'b0000011111), + .QPLL_CP_MONITOR_EN (1'b0), + .QPLL_DMONITOR_SEL (1'b0), + .QPLL_FBDIV (QPLL_FBDIV_IN), + .QPLL_FBDIV_MONITOR_EN (1'b0), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .QPLL_INIT_CFG (24'h000006), + .QPLL_LOCK_CFG (16'h21E8), + .QPLL_LPF (4'b1111), + .QPLL_REFCLK_DIV (1) + ) + gt_common_inst + ( + //----------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- + .DRPADDR (8'd0), + .DRPCLK (1'b0), + .DRPDI (16'd0), + .DRPDO (), + .DRPEN (1'b0), + .DRPRDY (), + .DRPWE (1'b0), + //-------------------- Common Block - Ref Clock Ports --------------------- + .GTGREFCLK (1'b0), + .GTNORTHREFCLK0 (1'b0), + .GTNORTHREFCLK1 (1'b0), + .GTREFCLK0 (xcvr_gtrefclk0_in), + .GTREFCLK1 (1'b0), + .GTSOUTHREFCLK0 (1'b0), + .GTSOUTHREFCLK1 (1'b0), + //----------------------- Common Block - QPLL Ports ----------------------- + .QPLLDMONITOR (), + //--------------------- Common Block - Clocking Ports ---------------------- + .QPLLOUTCLK (xcvr_qpllclk_out), + .QPLLOUTREFCLK (xcvr_qpllrefclk_out), + .REFCLKOUTMONITOR (), + //----------------------- Common Block - QPLL Ports ------------------------ + .QPLLFBCLKLOST (), + .QPLLLOCK (xcvr_qplllock_out), + .QPLLLOCKDETCLK (xcvr_ctrl_clk), + .QPLLLOCKEN (1'b1), + .QPLLOUTRESET (1'b0), + .QPLLPD (QPLL_EXT_CTRL ? xcvr_qpllpd_in : gt_qpll_pd), + .QPLLREFCLKLOST (qpll_refclk_lost), + .QPLLREFCLKSEL (3'b001), + .QPLLRESET (QPLL_EXT_CTRL ? xcvr_qpllreset_in : gt_qpll_reset), + .QPLLRSVD1 (16'b0000000000000000), + .QPLLRSVD2 (5'b11111), + //------------------------------- QPLL Ports ------------------------------- + .BGBYPASSB (1'b1), + .BGMONITORENB (1'b1), + .BGPDB (1'b1), + .BGRCALOVRD (5'b11111), + .PMARSVD (8'b00000000), + .RCALENB (1'b1) + ); + + end else begin + + assign xcvr_qplllock_out = 1'b0; + assign xcvr_qpllclk_out = 1'b0; + assign xcvr_qpllrefclk_out = 1'b0; + + end + + GTXE2_CHANNEL # + ( + //_______________________ Simulation-Only Attributes __________________ + .SIM_RECEIVER_DETECT_PASS ("TRUE"), + .SIM_TX_EIDLE_DRIVE_LEVEL ("X"), + .SIM_RESET_SPEEDUP (SIM ? "TRUE" : "FALSE"), + .SIM_CPLLREFCLK_SEL (3'b001), + .SIM_VERSION ("4.0"), + //----------------RX Byte and Word Alignment Attributes--------------- + .ALIGN_COMMA_DOUBLE ("FALSE"), + .ALIGN_COMMA_ENABLE (10'b1111111111), + .ALIGN_COMMA_WORD (1), + .ALIGN_MCOMMA_DET ("FALSE"), + .ALIGN_MCOMMA_VALUE (10'b1010000011), + .ALIGN_PCOMMA_DET ("FALSE"), + .ALIGN_PCOMMA_VALUE (10'b0101111100), + .SHOW_REALIGN_COMMA ("FALSE"), + .RXSLIDE_AUTO_WAIT (7), + .RXSLIDE_MODE ("OFF"), + .RX_SIG_VALID_DLY (10), + //----------------RX 8B/10B Decoder Attributes--------------- + .RX_DISPERR_SEQ_MATCH ("FALSE"), + .DEC_MCOMMA_DETECT ("FALSE"), + .DEC_PCOMMA_DETECT ("FALSE"), + .DEC_VALID_COMMA_ONLY ("FALSE"), + //----------------------RX Clock Correction Attributes---------------------- + .CBCC_DATA_SOURCE_SEL ("ENCODED"), + .CLK_COR_SEQ_2_USE ("FALSE"), + .CLK_COR_KEEP_IDLE ("FALSE"), + .CLK_COR_MAX_LAT (19), + .CLK_COR_MIN_LAT (15), + .CLK_COR_PRECEDENCE ("TRUE"), + .CLK_COR_REPEAT_WAIT (0), + .CLK_COR_SEQ_LEN (1), + .CLK_COR_SEQ_1_ENABLE (4'b1111), + .CLK_COR_SEQ_1_1 (10'b0100000000), + .CLK_COR_SEQ_1_2 (10'b0000000000), + .CLK_COR_SEQ_1_3 (10'b0000000000), + .CLK_COR_SEQ_1_4 (10'b0000000000), + .CLK_CORRECT_USE ("FALSE"), + .CLK_COR_SEQ_2_ENABLE (4'b1111), + .CLK_COR_SEQ_2_1 (10'b0100000000), + .CLK_COR_SEQ_2_2 (10'b0000000000), + .CLK_COR_SEQ_2_3 (10'b0000000000), + .CLK_COR_SEQ_2_4 (10'b0000000000), + //----------------------RX Channel Bonding Attributes---------------------- + .CHAN_BOND_KEEP_ALIGN ("FALSE"), + .CHAN_BOND_MAX_SKEW (1), + .CHAN_BOND_SEQ_LEN (1), + .CHAN_BOND_SEQ_1_1 (10'b0000000000), + .CHAN_BOND_SEQ_1_2 (10'b0000000000), + .CHAN_BOND_SEQ_1_3 (10'b0000000000), + .CHAN_BOND_SEQ_1_4 (10'b0000000000), + .CHAN_BOND_SEQ_1_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_1 (10'b0000000000), + .CHAN_BOND_SEQ_2_2 (10'b0000000000), + .CHAN_BOND_SEQ_2_3 (10'b0000000000), + .CHAN_BOND_SEQ_2_4 (10'b0000000000), + .CHAN_BOND_SEQ_2_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_USE ("FALSE"), + .FTS_DESKEW_SEQ_ENABLE (4'b1111), + .FTS_LANE_DESKEW_CFG (4'b1111), + .FTS_LANE_DESKEW_EN ("FALSE"), + //-------------------------RX Margin Analysis Attributes---------------------------- + .ES_CONTROL (6'b000000), + .ES_ERRDET_EN ("FALSE"), + .ES_EYE_SCAN_EN ("TRUE"), + .ES_HORZ_OFFSET (12'h000), + .ES_PMA_CFG (10'b0000000000), + .ES_PRESCALE (5'b00000), + .ES_QUALIFIER (80'h00000000000000000000), + .ES_QUAL_MASK (80'h00000000000000000000), + .ES_SDATA_MASK (80'h00000000000000000000), + .ES_VERT_OFFSET (9'b000000000), + //-----------------------FPGA RX Interface Attributes------------------------- + .RX_DATA_WIDTH (32), + //-------------------------PMA Attributes---------------------------- + .OUTREFCLK_SEL_INV (2'b11), + .PMA_RSV (32'h001E7080), + .PMA_RSV2 (16'h2050), + .PMA_RSV3 (2'b00), + .PMA_RSV4 (32'h00000000), + .RX_BIAS_CFG (12'b000000000100), + .DMONITOR_CFG (24'h000A00), + .RX_CM_SEL (2'b11), + .RX_CM_TRIM (3'b010), + .RX_DEBUG_CFG (12'b000000000000), + .RX_OS_CFG (13'b0000010000000), + .TERM_RCAL_CFG (5'b10000), + .TERM_RCAL_OVRD (1'b0), + .TST_RSV (32'h00000000), + .RX_CLK25_DIV (7), + .TX_CLK25_DIV (7), + .UCODEER_CLR (1'b0), + //-------------------------PCI Express Attributes---------------------------- + .PCS_PCIE_EN ("FALSE"), + //-------------------------PCS Attributes---------------------------- + .PCS_RSVD_ATTR (48'h000000000000), + //-----------RX Buffer Attributes------------ + .RXBUF_ADDR_MODE ("FAST"), + .RXBUF_EIDLE_HI_CNT (4'b1000), + .RXBUF_EIDLE_LO_CNT (4'b0000), + .RXBUF_EN ("TRUE"), + .RX_BUFFER_CFG (6'b000000), + .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), + .RXBUF_RESET_ON_EIDLE ("FALSE"), + .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .RXBUFRESET_TIME (5'b00001), + .RXBUF_THRESH_OVFLW (61), + .RXBUF_THRESH_OVRD ("FALSE"), + .RXBUF_THRESH_UNDFLW (4), + .RXDLY_CFG (16'h001F), + .RXDLY_LCFG (9'h030), + .RXDLY_TAP_CFG (16'h0000), + .RXPH_CFG (24'h000000), + .RXPHDLY_CFG (24'h084020), + .RXPH_MONITOR_SEL (5'b00000), + .RX_XCLK_SEL ("RXREC"), + .RX_DDI_SEL (6'b000000), + .RX_DEFER_RESET_BUF_EN ("TRUE"), + //---------------------CDR Attributes------------------------- + //For Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008 + //For Display Port, HBR2 - set RXCDR_CFG=72'h038c008bff20200010 + //For SATA Gen1 GTX- set RXCDR_CFG=72'h03_8000_8BFF_4010_0008 + //For SATA Gen2 GTX- set RXCDR_CFG=72'h03_8800_8BFF_4020_0008 + //For SATA Gen3 GTX- set RXCDR_CFG=72'h03_8000_8BFF_1020_0010 + //For SATA Gen3 GTP- set RXCDR_CFG=83'h0_0000_87FE_2060_2444_1010 + //For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010 + //For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010 + .RXCDR_CFG (72'h0b000023ff10400020), + .RXCDR_FR_RESET_ON_EIDLE (1'b0), + .RXCDR_HOLD_DURING_EIDLE (1'b0), + .RXCDR_PH_RESET_ON_EIDLE (1'b0), + .RXCDR_LOCK_CFG (6'b010101), + //-----------------RX Initialization and Reset Attributes------------------- + .RXCDRFREQRESET_TIME (5'b00001), + .RXCDRPHRESET_TIME (5'b00001), + .RXISCANRESET_TIME (5'b00001), + .RXPCSRESET_TIME (5'b00001), + .RXPMARESET_TIME (5'b00011), + //-----------------RX OOB Signaling Attributes------------------- + .RXOOB_CFG (7'b0000110), + //-----------------------RX Gearbox Attributes--------------------------- + .RXGEARBOX_EN ("TRUE"), + .GEARBOX_MODE (3'b001), + //-----------------------PRBS Detection Attribute----------------------- + .RXPRBS_ERR_LOOPBACK (1'b0), + //-----------Power-Down Attributes---------- + .PD_TRANS_TIME_FROM_P2 (12'h03c), + .PD_TRANS_TIME_NONE_P2 (8'h19), + .PD_TRANS_TIME_TO_P2 (8'h64), + //-----------RX OOB Signaling Attributes---------- + .SAS_MAX_COM (64), + .SAS_MIN_COM (36), + .SATA_BURST_SEQ_LEN (4'b0101), + .SATA_BURST_VAL (3'b100), + .SATA_EIDLE_VAL (3'b100), + .SATA_MAX_BURST (8), + .SATA_MAX_INIT (21), + .SATA_MAX_WAKE (7), + .SATA_MIN_BURST (4), + .SATA_MIN_INIT (12), + .SATA_MIN_WAKE (4), + //-----------RX Fabric Clock Output Control Attributes---------- + .TRANS_TIME_RATE (8'h0E), + //------------TX Buffer Attributes---------------- + .TXBUF_EN ("TRUE"), + .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .TXDLY_CFG (16'h001F), + .TXDLY_LCFG (9'h030), + .TXDLY_TAP_CFG (16'h0000), + .TXPH_CFG (16'h0780), + .TXPHDLY_CFG (24'h084020), + .TXPH_MONITOR_SEL (5'b00000), + .TX_XCLK_SEL ("TXOUT"), + //-----------------------FPGA TX Interface Attributes------------------------- + .TX_DATA_WIDTH (32), + //-----------------------TX Configurable Driver Attributes------------------------- + .TX_DEEMPH0 (5'b00000), + .TX_DEEMPH1 (5'b00000), + .TX_EIDLE_ASSERT_DELAY (3'b110), + .TX_EIDLE_DEASSERT_DELAY (3'b100), + .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), + .TX_MAINCURSOR_SEL (1'b0), + .TX_DRIVE_MODE ("DIRECT"), + .TX_MARGIN_FULL_0 (7'b1001110), + .TX_MARGIN_FULL_1 (7'b1001001), + .TX_MARGIN_FULL_2 (7'b1000101), + .TX_MARGIN_FULL_3 (7'b1000010), + .TX_MARGIN_FULL_4 (7'b1000000), + .TX_MARGIN_LOW_0 (7'b1000110), + .TX_MARGIN_LOW_1 (7'b1000100), + .TX_MARGIN_LOW_2 (7'b1000010), + .TX_MARGIN_LOW_3 (7'b1000000), + .TX_MARGIN_LOW_4 (7'b1000000), + //-----------------------TX Gearbox Attributes-------------------------- + .TXGEARBOX_EN ("TRUE"), + //-----------------------TX Initialization and Reset Attributes-------------------------- + .TXPCSRESET_TIME (5'b00001), + .TXPMARESET_TIME (5'b00001), + //-----------------------TX Receiver Detection Attributes-------------------------- + .TX_RXDETECT_CFG (14'h1832), + .TX_RXDETECT_REF (3'b100), + //--------------------------CPLL Attributes---------------------------- + .CPLL_CFG (24'hBC07DC), + .CPLL_FBDIV (4), + .CPLL_FBDIV_45 (5), + .CPLL_INIT_CFG (24'h00001E), + .CPLL_LOCK_CFG (16'h01E8), + .CPLL_REFCLK_DIV (1), + .RXOUT_DIV (1), + .TXOUT_DIV (1), + .SATA_CPLL_CFG ("VCO_3000MHZ"), + //------------RX Initialization and Reset Attributes------------- + .RXDFELPMRESET_TIME (7'b0001111), + //------------RX Equalizer Attributes------------- + .RXLPM_HF_CFG (14'b00000011110000), + .RXLPM_LF_CFG (14'b00000011110000), + .RX_DFE_GAIN_CFG (23'h020FEA), + .RX_DFE_H2_CFG (12'b000000000000), + .RX_DFE_H3_CFG (12'b000001000000), + .RX_DFE_H4_CFG (11'b00011110000), + .RX_DFE_H5_CFG (11'b00011100000), + .RX_DFE_KL_CFG (13'b0000011111110), + .RX_DFE_LPM_CFG (16'h0954), + .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0), + .RX_DFE_UT_CFG (17'b10001111000000000), + .RX_DFE_VP_CFG (17'b00011111100000011), + //-----------------------Power-Down Attributes------------------------- + .RX_CLKMUX_PD (1'b1), + .TX_CLKMUX_PD (1'b1), + //-----------------------FPGA RX Interface Attribute------------------------- + .RX_INT_DATAWIDTH (1), + //-----------------------FPGA TX Interface Attribute------------------------- + .TX_INT_DATAWIDTH (1), + //----------------TX Configurable Driver Attributes--------------- + .TX_QPI_STATUS_EN (1'b0), + //-----------------------RX Equalizer Attributes-------------------------- + .RX_DFE_KL_CFG2 (32'h301148AC), + .RX_DFE_XYD_CFG (13'b0000000000000), + //-----------------------TX Configurable Driver Attributes-------------------------- + .TX_PREDRIVER_MODE (1'b0) + ) + gt_ch_inst + ( + //------------------------------- CPLL Ports ------------------------------- + .CPLLFBCLKLOST (), + .CPLLLOCK (), + .CPLLLOCKDETCLK (1'b0), + .CPLLLOCKEN (1'b1), + .CPLLPD (1'b1), + .CPLLREFCLKLOST (), + .CPLLREFCLKSEL (3'b001), + .CPLLRESET (1'b0), + .GTRSVD (16'b0000000000000000), + .PCSRSVDIN (16'b0000000000000000), + .PCSRSVDIN2 (5'b00000), + .PMARSVDIN (5'b00000), + .PMARSVDIN2 (5'b00000), + .TSTIN (20'b11111111111111111111), + .TSTOUT (), + //-------------------------------- Channel --------------------------------- + .CLKRSVD (4'd0), + //------------------------ Channel - Clocking Ports ------------------------ + .GTGREFCLK (1'b0), + .GTNORTHREFCLK0 (1'b0), + .GTNORTHREFCLK1 (1'b0), + .GTREFCLK0 (1'b0), + .GTREFCLK1 (1'b0), + .GTSOUTHREFCLK0 (1'b0), + .GTSOUTHREFCLK1 (1'b0), + //-------------------------- Channel - DRP Ports -------------------------- + .DRPADDR ('0), + .DRPCLK ('0), + .DRPDI ('0), + .DRPDO (), + .DRPEN ('0), + .DRPRDY (), + .DRPWE ('0), + //----------------------------- Clocking Ports ----------------------------- + .GTREFCLKMONITOR (), + .QPLLCLK (xcvr_qpllclk_in), + .QPLLREFCLK (xcvr_qpllrefclk_in), + .RXSYSCLKSEL (2'b11), + .TXSYSCLKSEL (2'b11), + //------------------------- Digital Monitor Ports -------------------------- + .DMONITOROUT (), + //--------------- FPGA TX Interface Datapath Configuration ---------------- + .TX8B10BEN (1'b0), + //----------------------------- Loopback Ports ----------------------------- + .LOOPBACK (3'b000), + //--------------------------- PCI Express Ports ---------------------------- + .PHYSTATUS (), + .RXRATE (3'd0), + .RXVALID (), + //---------------------------- Power-Down Ports ---------------------------- + .RXPD (gt_rx_pd ? 2'b11 : 2'b00), + .TXPD (gt_tx_pd ? 2'b11 : 2'b00), + //------------------------ RX 8B/10B Decoder Ports ------------------------- + .SETERRSTATUS (1'b0), + //------------------- RX Initialization and Reset Ports -------------------- + .EYESCANRESET (gt_rx_eyescan_reset), + .RXUSERRDY (gt_rx_userrdy), + //------------------------ RX Margin Analysis Ports ------------------------ + .EYESCANDATAERROR (), + .EYESCANMODE (1'b0), + .EYESCANTRIGGER (1'b0), + //----------------------- Receive Ports - CDR Ports ------------------------ + .RXCDRFREQRESET (1'b0), + .RXCDRHOLD (1'b0), + .RXCDRLOCK (gt_rx_cdr_lock), + .RXCDROVRDEN (1'b0), + .RXCDRRESET (1'b0), + .RXCDRRESETRSV (1'b0), + //----------------- Receive Ports - Clock Correction Ports ----------------- + .RXCLKCORCNT (), + //-------- Receive Ports - FPGA RX Interface Datapath Configuration -------- + .RX8B10BEN (1'b0), + //---------------- Receive Ports - FPGA RX Interface Ports ----------------- + .RXUSRCLK (gt_rxusrclk), + .RXUSRCLK2 (gt_rxusrclk2), + //---------------- Receive Ports - FPGA RX interface Ports ----------------- + .RXDATA (gt_rxdata), + //----------------- Receive Ports - Pattern Checker Ports ------------------ + .RXPRBSERR (), + .RXPRBSSEL (3'd0), + //----------------- Receive Ports - Pattern Checker ports ------------------ + .RXPRBSCNTRESET (1'b0), + //------------------ Receive Ports - RX Equalizer Ports ------------------- + .RXDFEXYDEN (1'b1), + .RXDFEXYDHOLD (1'b0), + .RXDFEXYDOVRDEN (1'b0), + //---------------- Receive Ports - RX 8B/10B Decoder Ports ----------------- + .RXDISPERR (), + .RXNOTINTABLE (), + //---------------------- Receive Ports - RX AFE Ports ---------------------- + .GTXRXN (xcvr_rxn), + .GTXRXP (xcvr_rxp), + //----------------- Receive Ports - RX Buffer Bypass Ports ----------------- + .RXBUFRESET (1'b0), + .RXBUFSTATUS (), + .RXDDIEN (1'b0), + .RXDLYBYPASS (1'b1), + .RXDLYEN (1'b0), + .RXDLYOVRDEN (1'b0), + .RXDLYSRESET (1'b0), + .RXDLYSRESETDONE (), + .RXPHALIGN (1'b0), + .RXPHALIGNDONE (), + .RXPHALIGNEN (1'b0), + .RXPHDLYPD (1'b0), + .RXPHDLYRESET (1'b0), + .RXPHMONITOR (), + .RXPHOVRDEN (1'b0), + .RXPHSLIPMONITOR (), + .RXSTATUS (), + //------------ Receive Ports - RX Byte and Word Alignment Ports ------------ + .RXBYTEISALIGNED (), + .RXBYTEREALIGN (), + .RXCOMMADET (), + .RXCOMMADETEN (1'b0), + .RXMCOMMAALIGNEN (1'b0), + .RXPCOMMAALIGNEN (1'b0), + //---------------- Receive Ports - RX Channel Bonding Ports ---------------- + .RXCHANBONDSEQ (), + .RXCHBONDEN (1'b0), + .RXCHBONDLEVEL (3'd0), + .RXCHBONDMASTER (1'b0), + .RXCHBONDO (), + .RXCHBONDSLAVE (1'b0), + //--------------- Receive Ports - RX Channel Bonding Ports ---------------- + .RXCHANISALIGNED (), + .RXCHANREALIGN (), + //------------------ Receive Ports - RX Equailizer Ports ------------------- + .RXLPMHFHOLD (1'b0), + .RXLPMHFOVRDEN (1'b0), + .RXLPMLFHOLD (1'b0), + //------------------- Receive Ports - RX Equalizer Ports ------------------- + .RXDFEAGCHOLD (1'b0), + .RXDFEAGCOVRDEN (1'b0), + .RXDFECM1EN (1'b0), + .RXDFELFHOLD (1'b0), + .RXDFELFOVRDEN (1'b1), + .RXDFELPMRESET (gt_rx_dfe_lpm_reset), + .RXDFETAP2HOLD (1'b0), + .RXDFETAP2OVRDEN (1'b0), + .RXDFETAP3HOLD (1'b0), + .RXDFETAP3OVRDEN (1'b0), + .RXDFETAP4HOLD (1'b0), + .RXDFETAP4OVRDEN (1'b0), + .RXDFETAP5HOLD (1'b0), + .RXDFETAP5OVRDEN (1'b0), + .RXDFEUTHOLD (1'b0), + .RXDFEUTOVRDEN (1'b0), + .RXDFEVPHOLD (1'b0), + .RXDFEVPOVRDEN (1'b0), + .RXDFEVSEN (1'b0), + .RXLPMLFKLOVRDEN (1'b0), + .RXMONITOROUT (), + .RXMONITORSEL ('0), + .RXOSHOLD (1'b0), + .RXOSOVRDEN (1'b0), + //---------- Receive Ports - RX Fabric ClocK Output Control Ports ---------- + .RXRATEDONE (), + //------------- Receive Ports - RX Fabric Output Control Ports ------------- + .RXOUTCLK (gt_rxoutclk), + .RXOUTCLKFABRIC (), + .RXOUTCLKPCS (), + .RXOUTCLKSEL (3'b010), + //-------------------- Receive Ports - RX Gearbox Ports -------------------- + .RXDATAVALID (gt_rxdatavalid), + .RXHEADER (gt_rxheader), + .RXHEADERVALID (gt_rxheadervalid), + .RXSTARTOFSEQ (), + //------------------- Receive Ports - RX Gearbox Ports -------------------- + .RXGEARBOXSLIP (gt_rxgearboxslip), + //----------- Receive Ports - RX Initialization and Reset Ports ------------ + .GTRXRESET (gt_rx_reset), + .RXOOBRESET (1'b0), + .RXPCSRESET (gt_rx_pcs_reset), + .RXPMARESET (gt_rx_pma_reset), + .RXRESETDONE (gt_rx_reset_done), + //---------------- Receive Ports - RX Margin Analysis ports ---------------- + .RXLPMEN (gt_rx_lpm_en), + //----------------- Receive Ports - RX OOB Signaling ports ----------------- + .RXCOMSASDET (), + .RXCOMWAKEDET (), + //---------------- Receive Ports - RX OOB Signaling ports ----------------- + .RXCOMINITDET (), + //---------------- Receive Ports - RX OOB signalling Ports ----------------- + .RXELECIDLE (), + .RXELECIDLEMODE (2'b11), + //--------------- Receive Ports - RX Polarity Control Ports ---------------- + .RXPOLARITY (GT_RX_POLARITY), + //-------------------- Receive Ports - RX gearbox ports -------------------- + .RXSLIDE (1'b0), + //----------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + .RXCHARISCOMMA (), + .RXCHARISK (), + //---------------- Receive Ports - Rx Channel Bonding Ports ---------------- + .RXCHBONDI (5'b00000), + //------------------------------ Rx AFE Ports ------------------------------ + .RXQPIEN (1'b0), + .RXQPISENN (), + .RXQPISENP (), + //------------------------- TX Buffer Bypass Ports ------------------------- + .TXPHDLYTSTCLK (1'b0), + //---------------------- TX Configurable Driver Ports ---------------------- + .TXPOSTCURSOR (GT_TX_POSTCURSOR), + .TXPOSTCURSORINV (1'b0), + .TXPRECURSOR (GT_TX_PRECURSOR), + .TXPRECURSORINV (1'b0), + .TXQPIBIASEN (1'b0), + .TXQPISTRONGPDOWN (1'b0), + .TXQPIWEAKPUP (1'b0), + //------------------- TX Initialization and Reset Ports -------------------- + .CFGRESET (1'b0), + .GTTXRESET (gt_tx_reset), + .PCSRSVDOUT (), + .TXUSERRDY (gt_tx_userrdy), + //-------------------- Transceiver Reset Mode Operation -------------------- + .GTRESETSEL (1'b0), + .RESETOVRD (1'b0), + //-------------- Transmit Ports - 8b10b Encoder Control Ports -------------- + .TXCHARDISPMODE (8'd0), + .TXCHARDISPVAL (8'd0), + //---------------- Transmit Ports - FPGA TX Interface Ports ---------------- + .TXUSRCLK (gt_txusrclk), + .TXUSRCLK2 (gt_txusrclk2), + //------------------- Transmit Ports - PCI Express Ports ------------------- + .TXELECIDLE (GT_TX_ELECIDLE), + .TXMARGIN (3'd0), + .TXRATE (3'd0), + .TXSWING (1'b0), + //---------------- Transmit Ports - Pattern Generator Ports ---------------- + .TXPRBSFORCEERR (1'b0), + //---------------- Transmit Ports - TX Buffer Bypass Ports ----------------- + .TXDLYBYPASS (1'b1), + .TXDLYEN (1'b0), + .TXDLYHOLD (1'b0), + .TXDLYOVRDEN (1'b0), + .TXDLYSRESET (1'b0), + .TXDLYSRESETDONE (), + .TXDLYUPDOWN (1'b0), + .TXPHALIGN (1'b0), + .TXPHALIGNDONE (), + .TXPHALIGNEN (1'b0), + .TXPHDLYPD (1'b0), + .TXPHDLYRESET (1'b0), + .TXPHINIT (1'b0), + .TXPHINITDONE (), + .TXPHOVRDEN (1'b0), + //-------------------- Transmit Ports - TX Buffer Ports -------------------- + .TXBUFSTATUS (), + //------------- Transmit Ports - TX Configurable Driver Ports -------------- + .TXBUFDIFFCTRL (3'b100), + .TXDEEMPH (1'b0), + .TXDIFFCTRL (GT_TX_DIFFCTRL), + .TXDIFFPD (1'b0), + .TXINHIBIT (GT_TX_INHIBIT), + .TXMAINCURSOR (GT_TX_MAINCURSOR), + .TXPISOPD (1'b0), + //---------------- Transmit Ports - TX Data Path interface ----------------- + .TXDATA (gt_txdata), + //-------------- Transmit Ports - TX Driver and OOB signaling -------------- + .GTXTXN (xcvr_txn), + .GTXTXP (xcvr_txp), + //--------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + .TXOUTCLK (gt_txoutclk), + .TXOUTCLKFABRIC (), + .TXOUTCLKPCS (), + .TXOUTCLKSEL (3'b010), + .TXRATEDONE (), + //------------------- Transmit Ports - TX Gearbox Ports -------------------- + .TXCHARISK (8'd0), + .TXGEARBOXREADY (), + .TXHEADER (gt_txheader), + .TXSEQUENCE (gt_txsequence), + .TXSTARTSEQ (1'b0), + //----------- Transmit Ports - TX Initialization and Reset Ports ----------- + .TXPCSRESET (gt_tx_pcs_reset), + .TXPMARESET (gt_tx_pma_reset), + .TXRESETDONE (gt_tx_reset_done), + //---------------- Transmit Ports - TX OOB signalling Ports ---------------- + .TXCOMFINISH (), + .TXCOMINIT (1'b0), + .TXCOMSAS (1'b0), + .TXCOMWAKE (1'b0), + .TXPDELECIDLEMODE (1'b0), + //--------------- Transmit Ports - TX Polarity Control Ports --------------- + .TXPOLARITY (GT_TX_POLARITY), + //------------- Transmit Ports - TX Receiver Detection Ports -------------- + .TXDETECTRX (1'b0), + //---------------- Transmit Ports - TX8b/10b Encoder Ports ----------------- + .TX8B10BBYPASS (8'd0), + //---------------- Transmit Ports - pattern Generator Ports ---------------- + .TXPRBSSEL (3'd0), + //--------------------- Tx Configurable Driver Ports ---------------------- + .TXQPISENN (), + .TXQPISENP () + ); + + assign gt_tx_pma_reset_done = 1'b1; + assign gt_rx_pma_reset_done = 1'b1; + end else begin $fatal(0, "Error: invalid configuration (%m)"); diff --git a/src/eth/syn/vivado/taxi_eth_phy_10g_7_gt.tcl b/src/eth/syn/vivado/taxi_eth_phy_10g_7_gt.tcl index cb1ce5d..f80bd0f 100644 --- a/src/eth/syn/vivado/taxi_eth_phy_10g_7_gt.tcl +++ b/src/eth/syn/vivado/taxi_eth_phy_10g_7_gt.tcl @@ -12,8 +12,10 @@ foreach inst [get_cells -hier -regexp -filter {(ORIG_REF_NAME =~ "taxi_eth_phy_1 REF_NAME =~ "taxi_eth_phy_10g_7_gt(__\w+__\d+)?")}] { puts "Inserting timing constraints for 7-series 10GBASE-R PHY+GT instance $inst" - create_clock -period 3.10303 [get_pins -filter {REF_PIN_NAME=~*TXOUTCLK} -of_objects [get_cells $inst/xcvr.gthe2_i]] - create_clock -period 6.4 [get_pins -filter {REF_PIN_NAME=~*TXOUTCLKFABRIC} -of_objects [get_cells $inst/xcvr.gthe2_i]] - create_clock -period 3.10303 [get_pins -filter {REF_PIN_NAME=~*RXOUTCLK} -of_objects [get_cells $inst/xcvr.gthe2_i]] - create_clock -period 6.4 [get_pins -filter {REF_PIN_NAME=~*RXOUTCLKFABRIC} -of_objects [get_cells $inst/xcvr.gthe2_i]] + set gt_ch_inst [get_cells "$inst/xcvr.gt_ch_inst"] + + create_clock -period 3.103 [get_pins -filter {REF_PIN_NAME=~*TXOUTCLK} -of_objects $gt_ch_inst] + create_clock -period 6.4 [get_pins -filter {REF_PIN_NAME=~*TXOUTCLKFABRIC} -of_objects $gt_ch_inst] + create_clock -period 3.103 [get_pins -filter {REF_PIN_NAME=~*RXOUTCLK} -of_objects $gt_ch_inst] + create_clock -period 6.4 [get_pins -filter {REF_PIN_NAME=~*RXOUTCLKFABRIC} -of_objects $gt_ch_inst] }