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eth: Rename gearbox start signals to sync

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-06-12 15:45:07 -07:00
parent ca3ee2d197
commit 4e66dd0f98
33 changed files with 137 additions and 137 deletions
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38
src/eth/tb/baser.py
View File

@@ -25,7 +25,7 @@ from cocotbext.eth import XgmiiFrame
class BaseRSerdesSource():
def __init__(self, data, hdr, clock, enable=None, slip=None, data_valid=None, hdr_valid=None,
gbx_start=None, scramble=True, reverse=False, gbx_cfg=None, *args, **kwargs):
gbx_sync=None, scramble=True, reverse=False, gbx_cfg=None, *args, **kwargs):
self.log = logging.getLogger(f"cocotb.{data._path}")
self.data = data
@@ -35,7 +35,7 @@ class BaseRSerdesSource():
self.slip = slip
self.data_valid = data_valid
self.hdr_valid = hdr_valid
self.gbx_start = gbx_start
self.gbx_sync = gbx_sync
self.scramble = scramble
self.reverse = reverse
@@ -92,8 +92,8 @@ class BaseRSerdesSource():
self.hdr.setimmediatevalue(0)
if self.hdr_valid is not None:
self.hdr_valid.setimmediatevalue(0)
if self.gbx_start is not None:
self.gbx_start.setimmediatevalue(0)
if self.gbx_sync is not None:
self.gbx_sync.setimmediatevalue(0)
self._run_cr = cocotb.start_soon(self._run())
@@ -220,8 +220,8 @@ class BaseRSerdesSource():
if self.gbx_seq_len:
self.gbx_seq = (self.gbx_seq + 1) % self.gbx_seq_len
if self.gbx_start is not None:
self.gbx_start.value = (self.gbx_seq == 0)
if self.gbx_sync is not None:
self.gbx_sync.value = (self.gbx_seq == 0)
self.gbx_bit_cnt += self.gbx_in_bits
@@ -242,8 +242,8 @@ class BaseRSerdesSource():
self.gbx_bit_cnt = 0
gbx_delay = 0
if self.gbx_start is not None:
self.gbx_start.value = 0
if self.gbx_sync is not None:
self.gbx_sync.value = 0
if ifg_cnt + deficit_idle_cnt > self.byte_lanes-1 or (not self.enable_dic and ifg_cnt > 4):
# in IFG
@@ -463,7 +463,7 @@ class BaseRSerdesSource():
class BaseRSerdesSink:
def __init__(self, data, hdr, clock, enable=None, data_valid=None, hdr_valid=None,
gbx_req_start=None, gbx_req_stall=None, gbx_start=None,
gbx_req_sync=None, gbx_req_stall=None, gbx_sync=None,
scramble=True, reverse=False, gbx_cfg=None, *args, **kwargs):
self.log = logging.getLogger(f"cocotb.{data._path}")
@@ -473,9 +473,9 @@ class BaseRSerdesSink:
self.enable = enable
self.data_valid = data_valid
self.hdr_valid = hdr_valid
self.gbx_req_start = gbx_req_start
self.gbx_req_sync = gbx_req_sync
self.gbx_req_stall = gbx_req_stall
self.gbx_start = gbx_start
self.gbx_sync = gbx_sync
self.scramble = scramble
self.reverse = reverse
@@ -515,8 +515,8 @@ class BaseRSerdesSink:
if gbx_cfg:
self.set_gbx_cfg(*gbx_cfg)
if self.gbx_req_start is not None:
self.gbx_req_start.setimmediatevalue(0)
if self.gbx_req_sync is not None:
self.gbx_req_sync.setimmediatevalue(0)
if self.gbx_req_stall is not None:
self.gbx_req_stall.setimmediatevalue(0)
@@ -632,8 +632,8 @@ class BaseRSerdesSink:
# generation
self.gbx_seq_gen = (self.gbx_seq_gen + 1) % self.gbx_seq_len
if self.gbx_req_start is not None:
self.gbx_req_start.value = (self.gbx_seq_gen == 0)
if self.gbx_req_sync is not None:
self.gbx_req_sync.value = (self.gbx_seq_gen == 0)
# stall cycle
if self.gbx_req_stall is not None:
@@ -642,8 +642,8 @@ class BaseRSerdesSink:
# sync
self.gbx_seq = (self.gbx_seq + 1) % self.gbx_seq_len
if self.gbx_start is not None:
if self.gbx_start.value.integer:
if self.gbx_sync is not None:
if self.gbx_sync.value.integer:
self.gbx_seq = 0
self.gbx_bit_cnt = max(self.gbx_bit_cnt - self.gbx_out_bits, 0)
@@ -659,8 +659,8 @@ class BaseRSerdesSink:
self.gbx_bit_cnt = 0
gbx_delay = 0
if self.gbx_start is not None:
self.gbx_start.value = 1
if self.gbx_sync is not None:
self.gbx_sync.value = 1
if self.data_valid is not None:
if not self.data_valid.value.integer:

4
src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py
View File

@@ -57,9 +57,9 @@ class TB:
data_valid=dut.encoded_tx_data_valid,
hdr=dut.encoded_tx_hdr,
hdr_valid=dut.encoded_tx_hdr_valid,
gbx_req_start=dut.tx_gbx_req_start,
gbx_req_sync=dut.tx_gbx_req_sync,
gbx_req_stall=dut.tx_gbx_req_stall,
gbx_start=dut.tx_gbx_start,
gbx_sync=dut.tx_gbx_sync,
clock=dut.clk,
scramble=False,
gbx_cfg=gbx_cfg

8
src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.sv
View File

@@ -46,9 +46,9 @@ logic [DATA_W-1:0] encoded_tx_data;
logic encoded_tx_data_valid;
logic [HDR_W-1:0] encoded_tx_hdr;
logic encoded_tx_hdr_valid;
logic [GBX_CNT-1:0] tx_gbx_req_start;
logic [GBX_CNT-1:0] tx_gbx_req_sync;
logic tx_gbx_req_stall;
logic [GBX_CNT-1:0] tx_gbx_start;
logic [GBX_CNT-1:0] tx_gbx_sync;
logic [PTP_TS_W-1:0] ptp_ts;
@@ -97,9 +97,9 @@ uut (
.encoded_tx_data_valid(encoded_tx_data_valid),
.encoded_tx_hdr(encoded_tx_hdr),
.encoded_tx_hdr_valid(encoded_tx_hdr_valid),
.tx_gbx_req_start(tx_gbx_req_start),
.tx_gbx_req_sync(tx_gbx_req_sync),
.tx_gbx_req_stall(tx_gbx_req_stall),
.tx_gbx_start(tx_gbx_start),
.tx_gbx_sync(tx_gbx_sync),
/*
* PTP

4
src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py
View File

@@ -76,9 +76,9 @@ class TB:
data_valid=dut.serdes_tx_data_valid,
hdr=dut.serdes_tx_hdr,
hdr_valid=dut.serdes_tx_hdr_valid,
gbx_req_start=dut.serdes_tx_gbx_req_start,
gbx_req_sync=dut.serdes_tx_gbx_req_sync,
gbx_req_stall=dut.serdes_tx_gbx_req_stall,
gbx_start=dut.serdes_tx_gbx_start,
gbx_sync=dut.serdes_tx_gbx_sync,
clock=dut.tx_clk,
gbx_cfg=gbx_cfg
)

8
src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.sv
View File

@@ -66,9 +66,9 @@ logic [DATA_W-1:0] serdes_tx_data;
logic serdes_tx_data_valid;
logic [HDR_W-1:0] serdes_tx_hdr;
logic serdes_tx_hdr_valid;
logic serdes_tx_gbx_req_start;
logic serdes_tx_gbx_req_sync;
logic serdes_tx_gbx_req_stall;
logic serdes_tx_gbx_start;
logic serdes_tx_gbx_sync;
logic [DATA_W-1:0] serdes_rx_data;
logic serdes_rx_data_valid;
logic [HDR_W-1:0] serdes_rx_hdr;
@@ -243,9 +243,9 @@ uut (
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),

4
src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py
View File

@@ -75,9 +75,9 @@ class TB:
data_valid=dut.serdes_tx_data_valid,
hdr=dut.serdes_tx_hdr,
hdr_valid=dut.serdes_tx_hdr_valid,
gbx_req_start=dut.serdes_tx_gbx_req_start,
gbx_req_sync=dut.serdes_tx_gbx_req_sync,
gbx_req_stall=dut.serdes_tx_gbx_req_stall,
gbx_start=dut.serdes_tx_gbx_start,
gbx_sync=dut.serdes_tx_gbx_sync,
clock=dut.tx_clk,
gbx_cfg=gbx_cfg
)

8
src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.sv
View File

@@ -81,9 +81,9 @@ logic [DATA_W-1:0] serdes_tx_data;
logic serdes_tx_data_valid;
logic [HDR_W-1:0] serdes_tx_hdr;
logic serdes_tx_hdr_valid;
logic serdes_tx_gbx_req_start;
logic serdes_tx_gbx_req_sync;
logic serdes_tx_gbx_req_stall;
logic serdes_tx_gbx_start;
logic serdes_tx_gbx_sync;
logic [DATA_W-1:0] serdes_rx_data;
logic serdes_rx_data_valid;
logic [HDR_W-1:0] serdes_rx_hdr;
@@ -188,9 +188,9 @@ uut (
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),

4
src/eth/tb/taxi_eth_phy_10g/test_taxi_eth_phy_10g.py
View File

@@ -61,9 +61,9 @@ class TB:
data_valid=dut.serdes_tx_data_valid,
hdr=dut.serdes_tx_hdr,
hdr_valid=dut.serdes_tx_hdr_valid,
gbx_req_start=dut.serdes_tx_gbx_req_start,
gbx_req_sync=dut.serdes_tx_gbx_req_sync,
gbx_req_stall=dut.serdes_tx_gbx_req_stall,
gbx_start=dut.serdes_tx_gbx_start,
gbx_sync=dut.serdes_tx_gbx_sync,
clock=dut.tx_clk,
gbx_cfg=gbx_cfg
)

2
src/eth/tb/taxi_xgmii_baser_enc_64/test_taxi_xgmii_baser_enc_64.py
View File

@@ -47,7 +47,7 @@ class TB:
self.sink = BaseRSerdesSink(dut.encoded_tx_data, dut.encoded_tx_hdr, dut.clk, scramble=False)
dut.xgmii_tx_valid.setimmediatevalue(1)
dut.tx_gbx_start_in.setimmediatevalue(0)
dut.tx_gbx_sync_in.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)