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eth: Rename gearbox start signals to sync

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-06-12 15:45:07 -07:00
parent ca3ee2d197
commit 4e66dd0f98
33 changed files with 137 additions and 137 deletions
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2
src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
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@@ -75,7 +75,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py
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@@ -78,7 +78,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py
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@@ -98,7 +98,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/KR260/fpga/tb/fpga_core/test_fpga_core.py
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@@ -89,7 +89,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py
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@@ -75,7 +75,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py
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@@ -74,7 +74,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py
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@@ -85,7 +85,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py
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@@ -86,7 +86,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py
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@@ -82,7 +82,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
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@@ -104,7 +104,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
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@@ -92,7 +92,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py
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@@ -76,7 +76,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py
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@@ -76,7 +76,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

12
src/eth/rtl/taxi_axis_baser_tx_64.sv
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@@ -46,9 +46,9 @@ module taxi_axis_baser_tx_64 #
output wire logic encoded_tx_data_valid,
output wire logic [HDR_W-1:0] encoded_tx_hdr,
output wire logic encoded_tx_hdr_valid,
input wire logic [GBX_CNT-1:0] tx_gbx_req_start = '0,
input wire logic [GBX_CNT-1:0] tx_gbx_req_sync = '0,
input wire logic tx_gbx_req_stall = '0,
output wire logic [GBX_CNT-1:0] tx_gbx_start,
output wire logic [GBX_CNT-1:0] tx_gbx_sync,
/*
* PTP
@@ -223,7 +223,7 @@ logic [DATA_W-1:0] encoded_tx_data_reg = {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
logic encoded_tx_data_valid_reg = 1'b0;
logic [HDR_W-1:0] encoded_tx_hdr_reg = SYNC_CTRL;
logic encoded_tx_hdr_valid_reg = 1'b0;
logic [GBX_CNT-1:0] tx_gbx_start_reg = '0;
logic [GBX_CNT-1:0] tx_gbx_sync_reg = '0;
logic [DATA_W-1:0] output_data_reg = '0, output_data_next;
logic [3:0] output_type_reg = OUTPUT_TYPE_IDLE, output_type_next;
@@ -251,7 +251,7 @@ assign encoded_tx_data = encoded_tx_data_reg;
assign encoded_tx_data_valid = GBX_IF_EN ? encoded_tx_data_valid_reg : 1'b1;
assign encoded_tx_hdr = encoded_tx_hdr_reg;
assign encoded_tx_hdr_valid = GBX_IF_EN ? encoded_tx_hdr_valid_reg : 1'b1;
assign tx_gbx_start = GBX_IF_EN ? tx_gbx_start_reg : '0;
assign tx_gbx_sync = GBX_IF_EN ? tx_gbx_sync_reg : '0;
assign m_axis_tx_cpl.tdata = PTP_TS_EN ? ((!PTP_TS_FMT_TOD || m_axis_tx_cpl_ts_borrow_reg) ? m_axis_tx_cpl_ts_reg : m_axis_tx_cpl_ts_adj_reg) : '0;
assign m_axis_tx_cpl.tkeep = 1'b1;
@@ -920,7 +920,7 @@ always_ff @(posedge clk) begin
end
end
tx_gbx_start_reg <= tx_gbx_req_start;
tx_gbx_sync_reg <= tx_gbx_req_sync;
last_ts_reg <= (4+16)'(ptp_ts);
ts_inc_reg <= (4+16)'(ptp_ts) - last_ts_reg;
@@ -945,7 +945,7 @@ always_ff @(posedge clk) begin
encoded_tx_data_valid_reg <= 1'b0;
encoded_tx_hdr_reg <= SYNC_CTRL;
encoded_tx_hdr_valid_reg <= 1'b0;
tx_gbx_start_reg <= '0;
tx_gbx_sync_reg <= '0;
output_data_reg <= '0;
output_type_reg <= OUTPUT_TYPE_IDLE;

8
src/eth/rtl/taxi_eth_mac_phy_10g.sv
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@@ -69,9 +69,9 @@ module taxi_eth_mac_phy_10g #
output wire logic serdes_tx_data_valid,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
output wire logic serdes_tx_hdr_valid,
input wire logic serdes_tx_gbx_req_start = 1'b0,
input wire logic serdes_tx_gbx_req_sync = 1'b0,
input wire logic serdes_tx_gbx_req_stall = 1'b0,
output wire logic serdes_tx_gbx_start,
output wire logic serdes_tx_gbx_sync,
input wire logic [DATA_W-1:0] serdes_rx_data,
input wire logic serdes_rx_data_valid = 1'b1,
input wire logic [HDR_W-1:0] serdes_rx_hdr,
@@ -330,9 +330,9 @@ eth_mac_phy_10g_tx_inst (
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
/*
* PTP

8
src/eth/rtl/taxi_eth_mac_phy_10g_fifo.sv
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@@ -83,9 +83,9 @@ module taxi_eth_mac_phy_10g_fifo #
output wire logic serdes_tx_data_valid,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
output wire logic serdes_tx_hdr_valid,
input wire logic serdes_tx_gbx_req_start = 1'b0,
input wire logic serdes_tx_gbx_req_sync = 1'b0,
input wire logic serdes_tx_gbx_req_stall = 1'b0,
output wire logic serdes_tx_gbx_start,
output wire logic serdes_tx_gbx_sync,
input wire logic [DATA_W-1:0] serdes_rx_data,
input wire logic serdes_rx_data_valid = 1'b1,
input wire logic [HDR_W-1:0] serdes_rx_hdr,
@@ -332,9 +332,9 @@ eth_mac_phy_10g_inst (
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),

20
src/eth/rtl/taxi_eth_mac_phy_10g_tx.sv
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@@ -49,9 +49,9 @@ module taxi_eth_mac_phy_10g_tx #
output wire logic serdes_tx_data_valid,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
output wire logic serdes_tx_hdr_valid,
input wire logic serdes_tx_gbx_req_start = 1'b0,
input wire logic serdes_tx_gbx_req_sync = 1'b0,
input wire logic serdes_tx_gbx_req_stall = 1'b0,
output wire logic serdes_tx_gbx_start,
output wire logic serdes_tx_gbx_sync,
/*
* PTP
@@ -88,9 +88,9 @@ wire encoded_tx_data_valid;
wire [HDR_W-1:0] encoded_tx_hdr;
wire encoded_tx_hdr_valid;
wire tx_gbx_req_start;
wire tx_gbx_req_sync;
wire tx_gbx_req_stall;
wire tx_gbx_start;
wire tx_gbx_sync;
taxi_axis_baser_tx_64 #(
.DATA_W(DATA_W),
@@ -122,9 +122,9 @@ axis_baser_tx_inst (
.encoded_tx_data_valid(encoded_tx_data_valid),
.encoded_tx_hdr(encoded_tx_hdr),
.encoded_tx_hdr_valid(encoded_tx_hdr_valid),
.tx_gbx_req_start(tx_gbx_req_start),
.tx_gbx_req_sync(tx_gbx_req_sync),
.tx_gbx_req_stall(tx_gbx_req_stall),
.tx_gbx_start(tx_gbx_start),
.tx_gbx_sync(tx_gbx_sync),
/*
* PTP
@@ -175,9 +175,9 @@ eth_phy_10g_tx_if_inst (
.encoded_tx_data_valid(encoded_tx_data_valid),
.encoded_tx_hdr(encoded_tx_hdr),
.encoded_tx_hdr_valid(encoded_tx_hdr_valid),
.tx_gbx_req_start(tx_gbx_req_start),
.tx_gbx_req_sync(tx_gbx_req_sync),
.tx_gbx_req_stall(tx_gbx_req_stall),
.tx_gbx_start(tx_gbx_start),
.tx_gbx_sync(tx_gbx_sync),
/*
* SERDES interface
@@ -186,9 +186,9 @@ eth_phy_10g_tx_if_inst (
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
/*
* Configuration

16
src/eth/rtl/taxi_eth_phy_10g.sv
View File

@@ -46,9 +46,9 @@ module taxi_eth_phy_10g #
output wire logic [DATA_W-1:0] xgmii_rxd,
output wire logic [CTRL_W-1:0] xgmii_rxc,
output wire logic xgmii_rx_valid = 1'b1,
output wire logic tx_gbx_req_start,
output wire logic tx_gbx_req_sync,
output wire logic tx_gbx_req_stall,
input wire logic tx_gbx_start = 1'b0,
input wire logic tx_gbx_sync = 1'b0,
/*
* SERDES interface
@@ -57,9 +57,9 @@ module taxi_eth_phy_10g #
output wire logic serdes_tx_data_valid,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
output wire logic serdes_tx_hdr_valid,
input wire logic serdes_tx_gbx_req_start = 1'b0,
input wire logic serdes_tx_gbx_req_sync = 1'b0,
input wire logic serdes_tx_gbx_req_stall = 1'b0,
output wire logic serdes_tx_gbx_start,
output wire logic serdes_tx_gbx_sync,
input wire logic [DATA_W-1:0] serdes_rx_data,
input wire logic serdes_rx_data_valid = 1'b1,
input wire logic [HDR_W-1:0] serdes_rx_hdr,
@@ -155,9 +155,9 @@ eth_phy_10g_tx_inst (
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.xgmii_tx_valid(xgmii_tx_valid),
.tx_gbx_req_start(tx_gbx_req_start),
.tx_gbx_req_sync(tx_gbx_req_sync),
.tx_gbx_req_stall(tx_gbx_req_stall),
.tx_gbx_start(tx_gbx_start),
.tx_gbx_sync(tx_gbx_sync),
/*
* SERDES interface
@@ -166,9 +166,9 @@ eth_phy_10g_tx_inst (
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
/*
* Status

22
src/eth/rtl/taxi_eth_phy_10g_tx.sv
View File

@@ -36,9 +36,9 @@ module taxi_eth_phy_10g_tx #
input wire logic [DATA_W-1:0] xgmii_txd,
input wire logic [CTRL_W-1:0] xgmii_txc,
input wire logic xgmii_tx_valid = 1'b1,
output wire logic tx_gbx_req_start,
output wire logic tx_gbx_req_sync,
output wire logic tx_gbx_req_stall,
input wire logic tx_gbx_start = 1'b0,
input wire logic tx_gbx_sync = 1'b0,
/*
* SERDES interface
@@ -47,9 +47,9 @@ module taxi_eth_phy_10g_tx #
output wire logic serdes_tx_data_valid,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
output wire logic serdes_tx_hdr_valid,
input wire logic serdes_tx_gbx_req_start = 1'b0,
input wire logic serdes_tx_gbx_req_sync = 1'b0,
input wire logic serdes_tx_gbx_req_stall = 1'b0,
output wire logic serdes_tx_gbx_start,
output wire logic serdes_tx_gbx_sync,
/*
* Status
@@ -77,7 +77,7 @@ wire encoded_tx_data_valid;
wire [HDR_W-1:0] encoded_tx_hdr;
wire encoded_tx_hdr_valid;
wire tx_gbx_start_int;
wire tx_gbx_sync_int;
taxi_xgmii_baser_enc_64 #(
.DATA_W(DATA_W),
@@ -96,7 +96,7 @@ xgmii_baser_enc_inst (
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.xgmii_tx_valid(xgmii_tx_valid),
.tx_gbx_start_in(tx_gbx_start),
.tx_gbx_sync_in(tx_gbx_sync),
/*
* 10GBASE-R encoded interface
@@ -105,7 +105,7 @@ xgmii_baser_enc_inst (
.encoded_tx_data_valid(encoded_tx_data_valid),
.encoded_tx_hdr(encoded_tx_hdr),
.encoded_tx_hdr_valid(encoded_tx_hdr_valid),
.tx_gbx_start_out(tx_gbx_start_int),
.tx_gbx_sync_out(tx_gbx_sync_int),
/*
* Status
@@ -133,9 +133,9 @@ eth_phy_10g_tx_if_inst (
.encoded_tx_data_valid(encoded_tx_data_valid),
.encoded_tx_hdr(encoded_tx_hdr),
.encoded_tx_hdr_valid(encoded_tx_hdr_valid),
.tx_gbx_req_start(tx_gbx_req_start),
.tx_gbx_req_sync(tx_gbx_req_sync),
.tx_gbx_req_stall(tx_gbx_req_stall),
.tx_gbx_start(tx_gbx_start_int),
.tx_gbx_sync(tx_gbx_sync_int),
/*
* SERDES interface
@@ -144,9 +144,9 @@ eth_phy_10g_tx_if_inst (
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
/*
* Configuration

24
src/eth/rtl/taxi_eth_phy_10g_tx_if.sv
View File

@@ -36,9 +36,9 @@ module taxi_eth_phy_10g_tx_if #
input wire logic encoded_tx_data_valid = 1'b1,
input wire logic [HDR_W-1:0] encoded_tx_hdr,
input wire logic encoded_tx_hdr_valid = 1'b1,
output wire logic tx_gbx_req_start,
output wire logic tx_gbx_req_sync,
output wire logic tx_gbx_req_stall,
input wire logic tx_gbx_start = 1'b0,
input wire logic tx_gbx_sync = 1'b0,
/*
* SERDES interface
*/
@@ -46,9 +46,9 @@ module taxi_eth_phy_10g_tx_if #
output wire logic serdes_tx_data_valid,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
output wire logic serdes_tx_hdr_valid,
input wire logic serdes_tx_gbx_req_start = 1'b0,
input wire logic serdes_tx_gbx_req_sync = 1'b0,
input wire logic serdes_tx_gbx_req_stall = 1'b0,
output wire logic serdes_tx_gbx_start,
output wire logic serdes_tx_gbx_sync,
/*
* Configuration
@@ -63,7 +63,7 @@ if (DATA_W != 64)
if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
assign tx_gbx_req_start = GBX_IF_EN ? serdes_tx_gbx_req_start : '0;
assign tx_gbx_req_sync = GBX_IF_EN ? serdes_tx_gbx_req_sync : '0;
assign tx_gbx_req_stall = GBX_IF_EN ? serdes_tx_gbx_req_stall : '0;
logic [57:0] scrambler_state_reg = '1;
@@ -78,7 +78,7 @@ logic [DATA_W-1:0] serdes_tx_data_reg = '0;
logic serdes_tx_data_valid_reg = 1'b0;
logic [HDR_W-1:0] serdes_tx_hdr_reg = '0;
logic serdes_tx_hdr_valid_reg = 1'b0;
logic serdes_tx_gbx_start_reg = 1'b0;
logic serdes_tx_gbx_sync_reg = 1'b0;
wire [DATA_W-1:0] serdes_tx_data_int;
wire [HDR_W-1:0] serdes_tx_hdr_int;
@@ -106,7 +106,7 @@ if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *)
reg serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg serdes_tx_gbx_start_pipe_reg[SERDES_PIPELINE-1:0];
reg serdes_tx_gbx_sync_pipe_reg[SERDES_PIPELINE-1:0];
for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin
@@ -114,7 +114,7 @@ if (SERDES_PIPELINE > 0) begin
serdes_tx_data_valid_pipe_reg[n] = '0;
serdes_tx_hdr_pipe_reg[n] = '0;
serdes_tx_hdr_valid_pipe_reg[n] = '0;
serdes_tx_gbx_start_pipe_reg[n] = '0;
serdes_tx_gbx_sync_pipe_reg[n] = '0;
end
always @(posedge clk) begin
@@ -122,7 +122,7 @@ if (SERDES_PIPELINE > 0) begin
serdes_tx_data_valid_pipe_reg[n] <= n == 0 ? serdes_tx_data_valid_reg : serdes_tx_data_valid_pipe_reg[n-1];
serdes_tx_hdr_pipe_reg[n] <= n == 0 ? serdes_tx_hdr_int : serdes_tx_hdr_pipe_reg[n-1];
serdes_tx_hdr_valid_pipe_reg[n] <= n == 0 ? serdes_tx_hdr_valid_reg : serdes_tx_hdr_valid_pipe_reg[n-1];
serdes_tx_gbx_start_pipe_reg[n] <= n == 0 ? serdes_tx_gbx_start_reg : serdes_tx_gbx_start_pipe_reg[n-1];
serdes_tx_gbx_sync_pipe_reg[n] <= n == 0 ? serdes_tx_gbx_sync_reg : serdes_tx_gbx_sync_pipe_reg[n-1];
end
end
@@ -130,13 +130,13 @@ if (SERDES_PIPELINE > 0) begin
assign serdes_tx_data_valid = GBX_IF_EN ? serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1] : 1'b1;
assign serdes_tx_hdr = serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1];
assign serdes_tx_hdr_valid = GBX_IF_EN ? serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1] : 1'b1;
assign serdes_tx_gbx_start = GBX_IF_EN ? serdes_tx_gbx_start_pipe_reg[SERDES_PIPELINE-1] : 1'b0;
assign serdes_tx_gbx_sync = GBX_IF_EN ? serdes_tx_gbx_sync_pipe_reg[SERDES_PIPELINE-1] : 1'b0;
end else begin
assign serdes_tx_data = serdes_tx_data_int;
assign serdes_tx_data_valid = GBX_IF_EN ? serdes_tx_data_valid_reg : 1'b1;
assign serdes_tx_hdr = serdes_tx_hdr_int;
assign serdes_tx_hdr_valid = GBX_IF_EN ? serdes_tx_hdr_valid_reg : 1'b1;
assign serdes_tx_gbx_start = GBX_IF_EN ? serdes_tx_gbx_start_reg : 1'b0;
assign serdes_tx_gbx_sync = GBX_IF_EN ? serdes_tx_gbx_sync_reg : 1'b0;
end
taxi_lfsr #(
@@ -194,7 +194,7 @@ always_ff @(posedge clk) begin
serdes_tx_data_valid_reg <= encoded_tx_data_valid;
serdes_tx_hdr_valid_reg <= encoded_tx_hdr_valid;
serdes_tx_gbx_start_reg <= tx_gbx_start;
serdes_tx_gbx_sync_reg <= tx_gbx_sync;
end
endmodule

12
src/eth/rtl/taxi_xgmii_baser_enc_64.sv
View File

@@ -33,7 +33,7 @@ module taxi_xgmii_baser_enc_64 #
input wire logic [DATA_W-1:0] xgmii_txd,
input wire logic [CTRL_W-1:0] xgmii_txc,
input wire logic xgmii_tx_valid = 1'b1,
input wire logic [GBX_CNT-1:0] tx_gbx_start_in = '0,
input wire logic [GBX_CNT-1:0] tx_gbx_sync_in = '0,
/*
* 10GBASE-R encoded interface
@@ -42,7 +42,7 @@ module taxi_xgmii_baser_enc_64 #
output wire logic encoded_tx_data_valid,
output wire logic [HDR_W-1:0] encoded_tx_hdr,
output wire logic encoded_tx_hdr_valid,
output wire logic [GBX_CNT-1:0] tx_gbx_start_out,
output wire logic [GBX_CNT-1:0] tx_gbx_sync_out,
/*
* Status
@@ -118,7 +118,7 @@ logic [DATA_W-1:0] encoded_tx_data_reg = '0, encoded_tx_data_next;
logic encoded_tx_data_valid_reg = 1'b0, encoded_tx_data_valid_next;
logic [HDR_W-1:0] encoded_tx_hdr_reg = '0, encoded_tx_hdr_next;
logic encoded_tx_hdr_valid_reg = 1'b0, encoded_tx_hdr_valid_next;
logic [GBX_CNT-1:0] tx_gbx_start_reg = '0, tx_gbx_start_next;
logic [GBX_CNT-1:0] tx_gbx_sync_reg = '0, tx_gbx_sync_next;
logic tx_bad_block_reg = 1'b0, tx_bad_block_next;
@@ -126,7 +126,7 @@ assign encoded_tx_data = encoded_tx_data_reg;
assign encoded_tx_data_valid = GBX_IF_EN ? encoded_tx_data_valid_reg : 1'b1;
assign encoded_tx_hdr = encoded_tx_hdr_reg;
assign encoded_tx_hdr_valid = GBX_IF_EN ? encoded_tx_hdr_valid_reg : 1'b1;
assign tx_gbx_start_out = GBX_IF_EN ? tx_gbx_start_reg : '0;
assign tx_gbx_sync_out = GBX_IF_EN ? tx_gbx_sync_reg : '0;
assign tx_bad_block = tx_bad_block_reg;
@@ -264,7 +264,7 @@ always_comb begin
encoded_tx_data_valid_next = xgmii_tx_valid;
encoded_tx_hdr_valid_next = xgmii_tx_valid;
tx_gbx_start_next = tx_gbx_start_in;
tx_gbx_sync_next = tx_gbx_sync_in;
end
always_ff @(posedge clk) begin
@@ -272,7 +272,7 @@ always_ff @(posedge clk) begin
encoded_tx_data_valid_reg <= encoded_tx_data_valid_next;
encoded_tx_hdr_reg <= encoded_tx_hdr_next;
encoded_tx_hdr_valid_reg <= encoded_tx_hdr_valid_next;
tx_gbx_start_reg <= tx_gbx_start_next;
tx_gbx_sync_reg <= tx_gbx_sync_next;
tx_bad_block_reg <= tx_bad_block_next;
end

16
src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv
View File

@@ -287,9 +287,9 @@ wire [DATA_W-1:0] serdes_tx_data;
wire serdes_tx_data_valid;
wire [HDR_W-1:0] serdes_tx_hdr;
wire serdes_tx_hdr_valid;
wire serdes_tx_gbx_req_start;
wire serdes_tx_gbx_req_sync;
wire serdes_tx_gbx_req_stall;
wire serdes_tx_gbx_start;
wire serdes_tx_gbx_sync;
wire [DATA_W-1:0] serdes_rx_data;
wire serdes_rx_data_valid;
wire [HDR_W-1:0] serdes_rx_hdr;
@@ -395,9 +395,9 @@ if (CFG_LOW_LATENCY) begin : gt
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),
@@ -504,9 +504,9 @@ end else begin : gt
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),
@@ -569,9 +569,9 @@ eth_mac_phy_10g_inst (
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),

6
src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv
View File

@@ -113,9 +113,9 @@ module taxi_eth_phy_25g_us_gt #
input wire logic serdes_tx_data_valid,
input wire logic [HDR_W-1:0] serdes_tx_hdr,
input wire logic serdes_tx_hdr_valid,
output wire logic serdes_tx_gbx_req_start,
output wire logic serdes_tx_gbx_req_sync,
output wire logic serdes_tx_gbx_req_stall,
input wire logic serdes_tx_gbx_start,
input wire logic serdes_tx_gbx_sync,
output wire logic [DATA_W-1:0] serdes_rx_data,
output wire logic serdes_rx_data_valid,
output wire logic [HDR_W-1:0] serdes_rx_hdr,
@@ -370,7 +370,7 @@ if (!SIM) begin
assign serdes_rx_hdr_valid = gt_rxheadervalid[0];
end
assign serdes_tx_gbx_req_start = 1'b0;
assign serdes_tx_gbx_req_sync = 1'b0;
assign serdes_tx_gbx_req_stall = 1'b0;
if (SIM) begin : xcvr

24
src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv
View File

@@ -113,9 +113,9 @@ module taxi_eth_phy_25g_us_gt_ll #
input wire logic serdes_tx_data_valid,
input wire logic [HDR_W-1:0] serdes_tx_hdr,
input wire logic serdes_tx_hdr_valid,
output wire logic serdes_tx_gbx_req_start,
output wire logic serdes_tx_gbx_req_sync,
output wire logic serdes_tx_gbx_req_stall,
input wire logic serdes_tx_gbx_start,
input wire logic serdes_tx_gbx_sync,
output wire logic [DATA_W-1:0] serdes_rx_data,
output wire logic serdes_rx_data_valid,
output wire logic [HDR_W-1:0] serdes_rx_hdr,
@@ -376,20 +376,20 @@ if (GT_TYPE == "GTY") begin : tx_seq
// Generate gearbox request signals
logic [6:0] tx_seq_gen_reg = '0;
logic tx_req_start_reg = 1'b0;
logic tx_req_sync_reg = 1'b0;
logic tx_req_stall_reg = 1'b0;
assign serdes_tx_gbx_req_start = tx_req_start_reg;
assign serdes_tx_gbx_req_sync = tx_req_sync_reg;
assign serdes_tx_gbx_req_stall = tx_req_stall_reg;
always @(posedge tx_clk) begin
tx_req_start_reg <= 1'b0;
tx_req_sync_reg <= 1'b0;
tx_req_stall_reg <= 1'b0;
tx_seq_gen_reg <= tx_seq_gen_reg - 1;
if (tx_seq_gen_reg == 0) begin
tx_seq_gen_reg <= 65;
tx_req_start_reg <= 1'b1;
tx_req_sync_reg <= 1'b1;
end
if (tx_seq_gen_reg == 2 || tx_seq_gen_reg == 1) begin
tx_req_stall_reg <= 1'b1;
@@ -406,7 +406,7 @@ if (GT_TYPE == "GTY") begin : tx_seq
if (tx_seq_reg == 65) begin
tx_seq_reg <= '0;
end
if (serdes_tx_gbx_start) begin
if (serdes_tx_gbx_sync) begin
tx_seq_reg <= 1;
end
end
@@ -417,20 +417,20 @@ end else begin : tx_seq
// Generate gearbox request signals
logic [5:0] tx_seq_gen_reg = '0;
logic tx_req_start_reg = 1'b0;
logic tx_req_sync_reg = 1'b0;
logic tx_req_stall_reg = 1'b0;
assign serdes_tx_gbx_req_start = tx_req_start_reg;
assign serdes_tx_gbx_req_sync = tx_req_sync_reg;
assign serdes_tx_gbx_req_stall = tx_req_stall_reg;
always @(posedge tx_clk) begin
tx_req_start_reg <= 1'b0;
tx_req_sync_reg <= 1'b0;
tx_req_stall_reg <= 1'b0;
tx_seq_gen_reg <= tx_seq_gen_reg - 1;
if (tx_seq_gen_reg == 0) begin
tx_seq_gen_reg <= 32;
tx_req_start_reg <= 1'b1;
tx_req_sync_reg <= 1'b1;
end
if (tx_seq_gen_reg == 1) begin
tx_req_stall_reg <= 1'b1;
@@ -447,7 +447,7 @@ end else begin : tx_seq
if (tx_seq_reg == 32) begin
tx_seq_reg <= '0;
end
if (serdes_tx_gbx_start) begin
if (serdes_tx_gbx_sync) begin
tx_seq_reg <= 1;
end
end

38
src/eth/tb/baser.py
View File

@@ -25,7 +25,7 @@ from cocotbext.eth import XgmiiFrame
class BaseRSerdesSource():
def __init__(self, data, hdr, clock, enable=None, slip=None, data_valid=None, hdr_valid=None,
gbx_start=None, scramble=True, reverse=False, gbx_cfg=None, *args, **kwargs):
gbx_sync=None, scramble=True, reverse=False, gbx_cfg=None, *args, **kwargs):
self.log = logging.getLogger(f"cocotb.{data._path}")
self.data = data
@@ -35,7 +35,7 @@ class BaseRSerdesSource():
self.slip = slip
self.data_valid = data_valid
self.hdr_valid = hdr_valid
self.gbx_start = gbx_start
self.gbx_sync = gbx_sync
self.scramble = scramble
self.reverse = reverse
@@ -92,8 +92,8 @@ class BaseRSerdesSource():
self.hdr.setimmediatevalue(0)
if self.hdr_valid is not None:
self.hdr_valid.setimmediatevalue(0)
if self.gbx_start is not None:
self.gbx_start.setimmediatevalue(0)
if self.gbx_sync is not None:
self.gbx_sync.setimmediatevalue(0)
self._run_cr = cocotb.start_soon(self._run())
@@ -220,8 +220,8 @@ class BaseRSerdesSource():
if self.gbx_seq_len:
self.gbx_seq = (self.gbx_seq + 1) % self.gbx_seq_len
if self.gbx_start is not None:
self.gbx_start.value = (self.gbx_seq == 0)
if self.gbx_sync is not None:
self.gbx_sync.value = (self.gbx_seq == 0)
self.gbx_bit_cnt += self.gbx_in_bits
@@ -242,8 +242,8 @@ class BaseRSerdesSource():
self.gbx_bit_cnt = 0
gbx_delay = 0
if self.gbx_start is not None:
self.gbx_start.value = 0
if self.gbx_sync is not None:
self.gbx_sync.value = 0
if ifg_cnt + deficit_idle_cnt > self.byte_lanes-1 or (not self.enable_dic and ifg_cnt > 4):
# in IFG
@@ -463,7 +463,7 @@ class BaseRSerdesSource():
class BaseRSerdesSink:
def __init__(self, data, hdr, clock, enable=None, data_valid=None, hdr_valid=None,
gbx_req_start=None, gbx_req_stall=None, gbx_start=None,
gbx_req_sync=None, gbx_req_stall=None, gbx_sync=None,
scramble=True, reverse=False, gbx_cfg=None, *args, **kwargs):
self.log = logging.getLogger(f"cocotb.{data._path}")
@@ -473,9 +473,9 @@ class BaseRSerdesSink:
self.enable = enable
self.data_valid = data_valid
self.hdr_valid = hdr_valid
self.gbx_req_start = gbx_req_start
self.gbx_req_sync = gbx_req_sync
self.gbx_req_stall = gbx_req_stall
self.gbx_start = gbx_start
self.gbx_sync = gbx_sync
self.scramble = scramble
self.reverse = reverse
@@ -515,8 +515,8 @@ class BaseRSerdesSink:
if gbx_cfg:
self.set_gbx_cfg(*gbx_cfg)
if self.gbx_req_start is not None:
self.gbx_req_start.setimmediatevalue(0)
if self.gbx_req_sync is not None:
self.gbx_req_sync.setimmediatevalue(0)
if self.gbx_req_stall is not None:
self.gbx_req_stall.setimmediatevalue(0)
@@ -632,8 +632,8 @@ class BaseRSerdesSink:
# generation
self.gbx_seq_gen = (self.gbx_seq_gen + 1) % self.gbx_seq_len
if self.gbx_req_start is not None:
self.gbx_req_start.value = (self.gbx_seq_gen == 0)
if self.gbx_req_sync is not None:
self.gbx_req_sync.value = (self.gbx_seq_gen == 0)
# stall cycle
if self.gbx_req_stall is not None:
@@ -642,8 +642,8 @@ class BaseRSerdesSink:
# sync
self.gbx_seq = (self.gbx_seq + 1) % self.gbx_seq_len
if self.gbx_start is not None:
if self.gbx_start.value.integer:
if self.gbx_sync is not None:
if self.gbx_sync.value.integer:
self.gbx_seq = 0
self.gbx_bit_cnt = max(self.gbx_bit_cnt - self.gbx_out_bits, 0)
@@ -659,8 +659,8 @@ class BaseRSerdesSink:
self.gbx_bit_cnt = 0
gbx_delay = 0
if self.gbx_start is not None:
self.gbx_start.value = 1
if self.gbx_sync is not None:
self.gbx_sync.value = 1
if self.data_valid is not None:
if not self.data_valid.value.integer:

4
src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py
View File

@@ -57,9 +57,9 @@ class TB:
data_valid=dut.encoded_tx_data_valid,
hdr=dut.encoded_tx_hdr,
hdr_valid=dut.encoded_tx_hdr_valid,
gbx_req_start=dut.tx_gbx_req_start,
gbx_req_sync=dut.tx_gbx_req_sync,
gbx_req_stall=dut.tx_gbx_req_stall,
gbx_start=dut.tx_gbx_start,
gbx_sync=dut.tx_gbx_sync,
clock=dut.clk,
scramble=False,
gbx_cfg=gbx_cfg

8
src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.sv
View File

@@ -46,9 +46,9 @@ logic [DATA_W-1:0] encoded_tx_data;
logic encoded_tx_data_valid;
logic [HDR_W-1:0] encoded_tx_hdr;
logic encoded_tx_hdr_valid;
logic [GBX_CNT-1:0] tx_gbx_req_start;
logic [GBX_CNT-1:0] tx_gbx_req_sync;
logic tx_gbx_req_stall;
logic [GBX_CNT-1:0] tx_gbx_start;
logic [GBX_CNT-1:0] tx_gbx_sync;
logic [PTP_TS_W-1:0] ptp_ts;
@@ -97,9 +97,9 @@ uut (
.encoded_tx_data_valid(encoded_tx_data_valid),
.encoded_tx_hdr(encoded_tx_hdr),
.encoded_tx_hdr_valid(encoded_tx_hdr_valid),
.tx_gbx_req_start(tx_gbx_req_start),
.tx_gbx_req_sync(tx_gbx_req_sync),
.tx_gbx_req_stall(tx_gbx_req_stall),
.tx_gbx_start(tx_gbx_start),
.tx_gbx_sync(tx_gbx_sync),
/*
* PTP

4
src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py
View File

@@ -76,9 +76,9 @@ class TB:
data_valid=dut.serdes_tx_data_valid,
hdr=dut.serdes_tx_hdr,
hdr_valid=dut.serdes_tx_hdr_valid,
gbx_req_start=dut.serdes_tx_gbx_req_start,
gbx_req_sync=dut.serdes_tx_gbx_req_sync,
gbx_req_stall=dut.serdes_tx_gbx_req_stall,
gbx_start=dut.serdes_tx_gbx_start,
gbx_sync=dut.serdes_tx_gbx_sync,
clock=dut.tx_clk,
gbx_cfg=gbx_cfg
)

8
src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.sv
View File

@@ -66,9 +66,9 @@ logic [DATA_W-1:0] serdes_tx_data;
logic serdes_tx_data_valid;
logic [HDR_W-1:0] serdes_tx_hdr;
logic serdes_tx_hdr_valid;
logic serdes_tx_gbx_req_start;
logic serdes_tx_gbx_req_sync;
logic serdes_tx_gbx_req_stall;
logic serdes_tx_gbx_start;
logic serdes_tx_gbx_sync;
logic [DATA_W-1:0] serdes_rx_data;
logic serdes_rx_data_valid;
logic [HDR_W-1:0] serdes_rx_hdr;
@@ -243,9 +243,9 @@ uut (
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),

4
src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py
View File

@@ -75,9 +75,9 @@ class TB:
data_valid=dut.serdes_tx_data_valid,
hdr=dut.serdes_tx_hdr,
hdr_valid=dut.serdes_tx_hdr_valid,
gbx_req_start=dut.serdes_tx_gbx_req_start,
gbx_req_sync=dut.serdes_tx_gbx_req_sync,
gbx_req_stall=dut.serdes_tx_gbx_req_stall,
gbx_start=dut.serdes_tx_gbx_start,
gbx_sync=dut.serdes_tx_gbx_sync,
clock=dut.tx_clk,
gbx_cfg=gbx_cfg
)

8
src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.sv
View File

@@ -81,9 +81,9 @@ logic [DATA_W-1:0] serdes_tx_data;
logic serdes_tx_data_valid;
logic [HDR_W-1:0] serdes_tx_hdr;
logic serdes_tx_hdr_valid;
logic serdes_tx_gbx_req_start;
logic serdes_tx_gbx_req_sync;
logic serdes_tx_gbx_req_stall;
logic serdes_tx_gbx_start;
logic serdes_tx_gbx_sync;
logic [DATA_W-1:0] serdes_rx_data;
logic serdes_rx_data_valid;
logic [HDR_W-1:0] serdes_rx_hdr;
@@ -188,9 +188,9 @@ uut (
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),

4
src/eth/tb/taxi_eth_phy_10g/test_taxi_eth_phy_10g.py
View File

@@ -61,9 +61,9 @@ class TB:
data_valid=dut.serdes_tx_data_valid,
hdr=dut.serdes_tx_hdr,
hdr_valid=dut.serdes_tx_hdr_valid,
gbx_req_start=dut.serdes_tx_gbx_req_start,
gbx_req_sync=dut.serdes_tx_gbx_req_sync,
gbx_req_stall=dut.serdes_tx_gbx_req_stall,
gbx_start=dut.serdes_tx_gbx_start,
gbx_sync=dut.serdes_tx_gbx_sync,
clock=dut.tx_clk,
gbx_cfg=gbx_cfg
)

2
src/eth/tb/taxi_xgmii_baser_enc_64/test_taxi_xgmii_baser_enc_64.py
View File

@@ -47,7 +47,7 @@ class TB:
self.sink = BaseRSerdesSink(dut.encoded_tx_data, dut.encoded_tx_hdr, dut.clk, scramble=False)
dut.xgmii_tx_valid.setimmediatevalue(1)
dut.tx_gbx_start_in.setimmediatevalue(0)
dut.tx_gbx_sync_in.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)