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cndm: Make IRQ assignments configurable, add IRQ rate limiter

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-08 21:21:09 -07:00
parent 8773672f26
commit 50ba1d4c89
8 changed files with 201 additions and 24 deletions
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34
src/cndm/rtl/cndm_micro_cpl_wr.sv
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@@ -40,15 +40,22 @@ module cndm_micro_cpl_wr #(
taxi_dma_desc_if.sts_snk dma_wr_desc_sts,
taxi_dma_ram_if.rd_slv dma_ram_rd,
taxi_axis_if.snk s_axis_cpl,
output wire logic irq
/*
* Interrupts
*/
taxi_axis_if.src m_axis_irq,
taxi_axis_if.snk s_axis_cpl
);
localparam DMA_ADDR_W = dma_wr_desc_req.DST_ADDR_W;
localparam IRQN_W = m_axis_irq.DATA_W;
logic [CQN_W-1:0] cq_req_cqn_reg = '0;
logic cq_req_valid_reg = 1'b0;
logic cq_req_ready;
logic [IRQN_W-1:0] cq_rsp_irqn;
logic [DMA_ADDR_W-1:0] cq_rsp_addr;
logic cq_rsp_phase_tag;
logic cq_rsp_error;
@@ -57,7 +64,7 @@ logic cq_rsp_ready_reg = 1'b0;
cndm_micro_queue_state #(
.QN_W(CQN_W),
.DQN_W(CQN_W), // TODO
.DQN_W(IRQN_W),
.IS_CQ(1),
.QTYPE_EN(0),
.QE_SIZE(16),
@@ -86,7 +93,7 @@ cq_mgr_inst (
.req_valid(cq_req_valid_reg),
.req_ready(cq_req_ready),
.rsp_qn(),
.rsp_dqn(),
.rsp_dqn(cq_rsp_irqn),
.rsp_addr(cq_rsp_addr),
.rsp_phase_tag(cq_rsp_phase_tag),
.rsp_error(cq_rsp_error),
@@ -104,9 +111,17 @@ state_t state_reg = STATE_IDLE;
logic phase_tag_reg = 1'b0;
logic irq_reg = 1'b0;
logic [IRQN_W-1:0] m_axis_irq_irqn_reg = '0;
logic m_axis_irq_tvalid_reg = 1'b0;
assign irq = irq_reg;
assign m_axis_irq.tdata = m_axis_irq_irqn_reg;
assign m_axis_irq.tkeep = '1;
assign m_axis_irq.tstrb = m_axis_irq.tkeep;
assign m_axis_irq.tvalid = m_axis_irq_tvalid_reg;
assign m_axis_irq.tlast = 1'b1;
assign m_axis_irq.tid = '0;
assign m_axis_irq.tdest = '0;
assign m_axis_irq.tuser = '0;
always_ff @(posedge clk) begin
s_axis_cpl.tready <= 1'b0;
@@ -127,7 +142,7 @@ always_ff @(posedge clk) begin
cq_req_valid_reg <= cq_req_valid_reg && !cq_req_ready;
cq_rsp_ready_reg <= 1'b0;
irq_reg <= 1'b0;
m_axis_irq_tvalid_reg <= m_axis_irq_tvalid_reg && !m_axis_irq.tready;
case (state_reg)
STATE_IDLE: begin
@@ -149,6 +164,7 @@ always_ff @(posedge clk) begin
if (cq_rsp_valid && cq_rsp_ready_reg) begin
cq_rsp_ready_reg <= 1'b0;
m_axis_irq_irqn_reg <= cq_rsp_irqn;
dma_wr_desc_req.req_dst_addr <= cq_rsp_addr;
phase_tag_reg <= cq_rsp_phase_tag;
@@ -165,7 +181,7 @@ always_ff @(posedge clk) begin
STATE_WRITE_DATA: begin
if (dma_wr_desc_sts.sts_valid) begin
s_axis_cpl.tready <= 1'b1;
irq_reg <= 1'b1;
m_axis_irq_tvalid_reg <= 1'b1;
state_reg <= STATE_IDLE;
end
end
@@ -178,7 +194,7 @@ always_ff @(posedge clk) begin
state_reg <= STATE_IDLE;
cq_req_valid_reg <= 1'b0;
cq_rsp_ready_reg <= 1'b0;
irq_reg <= 1'b0;
m_axis_irq_tvalid_reg <= 1'b0;
end
end