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example/KC705: Add example design for Xilinx KC705

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-18 09:45:36 -08:00
parent 36ea9fb8d4
commit 53688afeb5
20 changed files with 2125 additions and 0 deletions
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example/KC705/fpga/eth_rgmii.xdc Normal file
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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# Ethernet constraints
# IDELAY from PHY chip (RGMII)
set_property IDELAY_VALUE 0 [get_cells {phy_if.phy_rx_ctl_idelay phy_if.phy_rxd_idelay_bit[*].idelay_inst}]
# MMCM phase (RGMII)
set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]