example/KC705: Add example design for Xilinx KC705

Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-18 09:45:36 -08:00
parent 36ea9fb8d4
commit 53688afeb5
20 changed files with 2125 additions and 0 deletions

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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
set params [dict create]
# Type of PHY on RJ-45 10/100/1000BASE-T port (GMII, RGMII, or SGMII)
dict set params BASET_PHY_TYPE "GMII"
# Invert polarity for SFP+ cage
# KC705 rev 1.0: diff pairs to SFP+ are polarity-swapped
dict set params SFP_INVERT "1"
# KC705 rev 1.1: diff pairs to SFP+ are correct
#dict set params SFP_INVERT "0"
# apply parameters to top-level
set param_list {}
dict for {name value} $params {
lappend param_list $name=$value
}
set_property generic $param_list [get_filesets sources_1]