example/KC705: Add example design for Xilinx KC705

Signed-off-by: Alex Forencich <alex@alexforencich.com>

example/KC705/fpga/fpga_rgmii_1g/Makefile

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+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xc7k325tffg900-2
+FPGA_TOP = fpga
+FPGA_ARCH = kintex7
+
+# Files for synthesis
+SYN_FILES = ../rtl/fpga.sv
+SYN_FILES += ../rtl/fpga_core.sv
+SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f
+SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f
+SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f
+SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
+SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
+SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga.xdc
+XDC_FILES += ../eth_rgmii.xdc
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_rgmii_phy_if.tcl
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_1g_rgmii.tcl
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
+
+# IP
+IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
+IP_TCL_FILES += ../ip/basex_pcs_pma_0.tcl
+
+# Configuration
+CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(PROJECT).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl

example/KC705/fpga/fpga_rgmii_1g/config.tcl

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+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# Type of PHY on RJ-45 10/100/1000BASE-T port (GMII, RGMII, or SGMII)
+dict set params BASET_PHY_TYPE "RGMII"
+
+# Invert polarity for SFP+ cage
+# KC705 rev 1.0: diff pairs to SFP+ are polarity-swapped
+dict set params SFP_INVERT "1"
+# KC705 rev 1.1: diff pairs to SFP+ are correct
+#dict set params SFP_INVERT "0"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

example/KC705/fpga/fpga_rgmii_1g/generate_bit_iodelay.tcl

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+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# Generate bit file with different IODELAY settings without rebuilding the full project
+
+open_project fpga.xpr
+open_run impl_1
+
+# IDELAY from PHY chip (RGMII)
+set_property IDELAY_VALUE 0 [get_cells {phy_if.phy_rx_ctl_idelay phy_if.phy_rxd_idelay_bit[*].idelay_inst}]
+
+# MMCM phase (RGMII)
+set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]
+
+write_bitstream -force fpga.bit
+exit