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example/KC705: Add example design for Xilinx KC705

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-18 09:45:36 -08:00
parent 36ea9fb8d4
commit 53688afeb5
20 changed files with 2125 additions and 0 deletions
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example/KC705/fpga/ip/basex_pcs_pma_0.tcl Normal file
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# SPDX-License-Identifier: MIT
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_0
set_property -dict [list \
CONFIG.Standard {1000BASEX} \
CONFIG.Physical_Interface {Transceiver} \
CONFIG.Management_Interface {false} \
CONFIG.Auto_Negotiation {false} \
CONFIG.TransceiverControl {true} \
CONFIG.SupportLevel {Include_Shared_Logic_in_Example_Design} \
] [get_ips basex_pcs_pma_0]