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example/KC705: Add example design for Xilinx KC705
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
708
example/KC705/fpga/rtl/fpga.sv
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708
example/KC705/fpga/rtl/fpga.sv
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@@ -0,0 +1,708 @@
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter VENDOR = "XILINX",
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// device family
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parameter FAMILY = "kintex7",
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// Use 90 degree clock for RGMII transmit
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parameter logic USE_CLK90 = 1'b1,
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// BASE-T PHY type (GMII, RGMII, SGMII)
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parameter BASET_PHY_TYPE = "GMII",
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// Invert SFP data pins
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parameter logic SFP_INVERT = 1'b1
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)
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(
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/*
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* Clock: 200MHz
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* Reset: Push button, active high
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*/
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input wire logic clk_200mhz_p,
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input wire logic clk_200mhz_n,
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input wire logic reset,
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/*
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* GPIO
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*/
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input wire logic btnu,
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input wire logic btnl,
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input wire logic btnd,
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input wire logic btnr,
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input wire logic btnc,
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input wire logic [3:0] sw,
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output wire logic [7:0] led,
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/*
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* UART: 115200 bps, 8N1
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*/
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input wire logic uart_rxd,
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output wire logic uart_txd,
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output wire logic uart_rts,
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input wire logic uart_cts,
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/*
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* Ethernet: SFP+
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*/
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input wire logic sfp_rx_p,
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input wire logic sfp_rx_n,
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output wire logic sfp_tx_p,
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output wire logic sfp_tx_n,
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input wire logic phy_sgmii_rx_p,
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input wire logic phy_sgmii_rx_n,
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output wire logic phy_sgmii_tx_p,
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output wire logic phy_sgmii_tx_n,
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input wire logic sgmii_clk_p,
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input wire logic sgmii_clk_n,
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output wire logic sfp_tx_disable_b,
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/*
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* Ethernet: 1000BASE-T GMII, RGMII, or SGMII
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*/
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input wire logic phy_rx_clk,
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input wire logic [7:0] phy_rxd,
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input wire logic phy_rx_dv,
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input wire logic phy_rx_er,
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output wire logic phy_gtx_clk,
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input wire logic phy_tx_clk,
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output wire logic [7:0] phy_txd,
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output wire logic phy_tx_en,
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output wire logic phy_tx_er,
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output wire logic phy_reset_n,
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input wire logic phy_int_n
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);
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// Clock and reset
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wire clk_200mhz_ibufg;
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// Internal 125 MHz clock
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wire clk_mmcm_out;
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wire clk_int;
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wire clk90_mmcm_out;
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wire clk90_int;
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wire rst_int;
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wire clk_200mhz_mmcm_out;
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wire clk_200mhz_int;
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wire mmcm_rst = reset;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS
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clk_200mhz_ibufgds_inst(
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.I(clk_200mhz_p),
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.IB(clk_200mhz_n),
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.O(clk_200mhz_ibufg)
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);
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// MMCM instance
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MMCME2_BASE #(
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// 200 MHz input
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.CLKIN1_PERIOD(5.0),
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.REF_JITTER1(0.010),
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// 200 MHz input / 1 = 200 MHz PFD (range 10 MHz to 500 MHz)
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.DIVCLK_DIVIDE(1),
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// 200 MHz PFD * 5 = 1000 MHz VCO (range 600 MHz to 1440 MHz)
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.CLKFBOUT_MULT_F(5),
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.CLKFBOUT_PHASE(0),
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// 1250 MHz VCO / 8 = 125 MHz, 0 degrees
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.CLKOUT0_DIVIDE_F(8),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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// 1250 MHz VCO / 8 = 125 MHz, 90 degrees
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.CLKOUT1_DIVIDE(8),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(90),
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// 1250 MHz VCO / 5 = 200 MHz, 0 degrees
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.CLKOUT2_DIVIDE(5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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// Not used
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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// Not used
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT4_CASCADE("FALSE"),
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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// Not used
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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// optimized bandwidth
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.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
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)
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clk_mmcm_inst (
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// 200 MHz input
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.CLKIN1(clk_200mhz_ibufg),
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// direct clkfb feeback
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.CLKFBIN(mmcm_clkfb),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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// 125 MHz, 0 degrees
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.CLKOUT0(clk_mmcm_out),
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.CLKOUT0B(),
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// 125 MHz, 90 degrees
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.CLKOUT1(clk90_mmcm_out),
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.CLKOUT1B(),
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// 200 MHz, 0 degrees
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.CLKOUT2(clk_200mhz_mmcm_out),
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.CLKOUT2B(),
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// Not used
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.CLKOUT3(),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(mmcm_rst),
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// don't power down
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.PWRDWN(1'b0),
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// locked output
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_bufg_inst (
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.I(clk_mmcm_out),
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.O(clk_int)
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);
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BUFG
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clk90_bufg_inst (
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.I(clk90_mmcm_out),
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.O(clk90_int)
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);
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BUFG
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clk_200mhz_bufg_inst (
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.I(clk_200mhz_mmcm_out),
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.O(clk_200mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_inst (
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.clk(clk_int),
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.rst(~mmcm_locked),
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.out(rst_int)
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);
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// GPIO
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wire btnu_int;
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wire btnl_int;
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wire btnd_int;
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wire btnr_int;
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wire btnc_int;
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wire [3:0] sw_int;
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taxi_debounce_switch #(
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.WIDTH(9),
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.N(4),
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.RATE(125000)
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)
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debounce_switch_inst (
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.clk(clk_int),
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.rst(rst_int),
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.in({btnu,
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btnl,
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btnd,
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btnr,
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btnc,
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sw}),
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.out({btnu_int,
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btnl_int,
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btnd_int,
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btnr_int,
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btnc_int,
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sw_int})
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);
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wire uart_rxd_int;
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wire uart_cts_int;
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taxi_sync_signal #(
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.WIDTH(2),
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.N(2)
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)
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sync_signal_inst (
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.clk(clk_int),
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.in({uart_rxd, uart_cts}),
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.out({uart_rxd_int, uart_cts_int})
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);
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wire [7:0] led_int;
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// SGMII interface to PHY
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wire phy_sgmii_clk_int;
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wire phy_sgmii_rst_int;
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wire phy_sgmii_clk_en_int;
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wire [7:0] phy_sgmii_txd_int;
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wire phy_sgmii_tx_en_int;
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wire phy_sgmii_tx_er_int;
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wire [7:0] phy_sgmii_rxd_int;
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wire phy_sgmii_rx_dv_int;
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wire phy_sgmii_rx_er_int;
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wire sgmii_gtrefclk;
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wire sgmii_gtrefclk_bufg;
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wire sgmii_txuserclk;
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wire sgmii_txuserclk2;
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wire sgmii_rxuserclk;
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wire sgmii_rxuserclk2;
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wire sgmii_pma_reset;
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wire sgmii_mmcm_locked;
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wire phy_sgmii_resetdone;
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assign phy_sgmii_clk_int = sgmii_txuserclk2;
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_sgmii_inst (
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.clk(phy_sgmii_clk_int),
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.rst(rst_int || !phy_sgmii_resetdone),
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.out(phy_sgmii_rst_int)
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);
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wire [15:0] sgmii_status_vect;
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wire sgmii_status_link_status = sgmii_status_vect[0];
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wire sgmii_status_link_synchronization = sgmii_status_vect[1];
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wire sgmii_status_rudi_c = sgmii_status_vect[2];
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wire sgmii_status_rudi_i = sgmii_status_vect[3];
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wire sgmii_status_rudi_invalid = sgmii_status_vect[4];
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wire sgmii_status_rxdisperr = sgmii_status_vect[5];
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wire sgmii_status_rxnotintable = sgmii_status_vect[6];
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wire sgmii_status_phy_link_status = sgmii_status_vect[7];
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wire [1:0] sgmii_status_remote_fault_encdg = sgmii_status_vect[9:8];
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wire [1:0] sgmii_status_speed = sgmii_status_vect[11:10];
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wire sgmii_status_duplex = sgmii_status_vect[12];
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wire sgmii_status_remote_fault = sgmii_status_vect[13];
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wire [1:0] sgmii_status_pause = sgmii_status_vect[15:14];
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wire [4:0] sgmii_config_vect;
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assign sgmii_config_vect[4] = 1'b1; // autonegotiation enable
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assign sgmii_config_vect[3] = 1'b0; // isolate
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assign sgmii_config_vect[2] = 1'b0; // power down
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assign sgmii_config_vect[1] = 1'b0; // loopback enable
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assign sgmii_config_vect[0] = 1'b0; // unidirectional enable
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wire [15:0] sgmii_an_config_vect;
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assign sgmii_an_config_vect[15] = 1'b1; // SGMII link status
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assign sgmii_an_config_vect[14] = 1'b1; // SGMII Acknowledge
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assign sgmii_an_config_vect[13:12] = 2'b01; // full duplex
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assign sgmii_an_config_vect[11:10] = 2'b10; // SGMII speed
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assign sgmii_an_config_vect[9] = 1'b0; // reserved
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assign sgmii_an_config_vect[8:7] = 2'b00; // pause frames - SGMII reserved
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assign sgmii_an_config_vect[6] = 1'b0; // reserved
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assign sgmii_an_config_vect[5] = 1'b0; // full duplex - SGMII reserved
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assign sgmii_an_config_vect[4:1] = 4'b0000; // reserved
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assign sgmii_an_config_vect[0] = 1'b1; // SGMII
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sgmii_pcs_pma_0
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sgmii_pcspma (
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// Transceiver Interface
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.gtrefclk_p (sgmii_clk_p),
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.gtrefclk_n (sgmii_clk_n),
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.gtrefclk_out (sgmii_gtrefclk),
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.gtrefclk_bufg_out (sgmii_gtrefclk_bufg),
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.txp (phy_sgmii_tx_p),
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.txn (phy_sgmii_tx_n),
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.rxp (phy_sgmii_rx_p),
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.rxn (phy_sgmii_rx_n),
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.resetdone (phy_sgmii_resetdone),
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.userclk_out (sgmii_txuserclk),
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.userclk2_out (sgmii_txuserclk2),
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.rxuserclk_out (sgmii_rxuserclk),
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.rxuserclk2_out (sgmii_rxuserclk2),
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.independent_clock_bufg(clk_int),
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.pma_reset_out (sgmii_pma_reset),
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.mmcm_locked_out (sgmii_mmcm_locked),
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.gt0_qplloutclk_out (),
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.gt0_qplloutrefclk_out (),
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// GMII Interface
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.sgmii_clk_r (),
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.sgmii_clk_f (),
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.sgmii_clk_en (phy_sgmii_clk_en_int),
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.gmii_txd (phy_sgmii_txd_int),
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.gmii_tx_en (phy_sgmii_tx_en_int),
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.gmii_tx_er (phy_sgmii_tx_er_int),
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.gmii_rxd (phy_sgmii_rxd_int),
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.gmii_rx_dv (phy_sgmii_rx_dv_int),
|
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.gmii_rx_er (phy_sgmii_rx_er_int),
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.gmii_isolate (),
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// Management: Alternative to MDIO Interface
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.configuration_vector (sgmii_config_vect),
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.an_interrupt (),
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.an_adv_config_vector (sgmii_an_config_vect),
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.an_restart_config (1'b0),
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// Speed Control
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.speed_is_10_100 (sgmii_status_speed != 2'b10),
|
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.speed_is_100 (sgmii_status_speed == 2'b01),
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// General IO's
|
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.status_vector (sgmii_status_vect),
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.reset (rst_int),
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.signal_detect (1'b1)
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);
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// 1000BASE-X SFP
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wire sfp_gmii_clk_int;
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wire sfp_gmii_rst_int;
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wire sfp_gmii_clk_en_int;
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wire [7:0] sfp_gmii_txd_int;
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wire sfp_gmii_tx_en_int;
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wire sfp_gmii_tx_er_int;
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wire [7:0] sfp_gmii_rxd_int;
|
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wire sfp_gmii_rx_dv_int;
|
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wire sfp_gmii_rx_er_int;
|
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wire sfp_gmii_txuserclk2 = sgmii_txuserclk2;
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wire sfp_gmii_resetdone;
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assign sfp_gmii_clk_int = sfp_gmii_txuserclk2;
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taxi_sync_reset #(
|
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.N(4)
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)
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sync_reset_sfp_inst (
|
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.clk(sfp_gmii_clk_int),
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.rst(rst_int || !sfp_gmii_resetdone),
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.out(sfp_gmii_rst_int)
|
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);
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wire [15:0] sfp_status_vect;
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wire sfp_status_link_status = sfp_status_vect[0];
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wire sfp_status_link_synchronization = sfp_status_vect[1];
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wire sfp_status_rudi_c = sfp_status_vect[2];
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wire sfp_status_rudi_i = sfp_status_vect[3];
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wire sfp_status_rudi_invalid = sfp_status_vect[4];
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wire sfp_status_rxdisperr = sfp_status_vect[5];
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wire sfp_status_rxnotintable = sfp_status_vect[6];
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wire sfp_status_phy_link_status = sfp_status_vect[7];
|
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wire [1:0] sfp_status_remote_fault_encdg = sfp_status_vect[9:8];
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wire [1:0] sfp_status_speed = sfp_status_vect[11:10];
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wire sfp_status_duplex = sfp_status_vect[12];
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wire sfp_status_remote_fault = sfp_status_vect[13];
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wire [1:0] sfp_status_pause = sfp_status_vect[15:14];
|
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wire [4:0] sfp_config_vect;
|
||||
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assign sfp_config_vect[4] = 1'b0; // autonegotiation enable
|
||||
assign sfp_config_vect[3] = 1'b0; // isolate
|
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assign sfp_config_vect[2] = 1'b0; // power down
|
||||
assign sfp_config_vect[1] = 1'b0; // loopback enable
|
||||
assign sfp_config_vect[0] = 1'b0; // unidirectional enable
|
||||
|
||||
basex_pcs_pma_0 your_instance_name (
|
||||
// Transceiver Interface
|
||||
.gtrefclk(sgmii_gtrefclk),
|
||||
.gtrefclk_bufg(sgmii_gtrefclk_bufg),
|
||||
.txp(sfp_tx_p),
|
||||
.txn(sfp_tx_n),
|
||||
.rxp(sfp_rx_p),
|
||||
.rxn(sfp_rx_n),
|
||||
.independent_clock_bufg(clk_int),
|
||||
.txoutclk(),
|
||||
.rxoutclk(),
|
||||
.resetdone(sfp_gmii_resetdone),
|
||||
.cplllock(),
|
||||
.mmcm_reset(),
|
||||
.userclk(sgmii_txuserclk),
|
||||
.userclk2(sgmii_txuserclk2),
|
||||
.pma_reset(sgmii_pma_reset),
|
||||
.mmcm_locked(sgmii_mmcm_locked),
|
||||
.rxuserclk(sgmii_rxuserclk),
|
||||
.rxuserclk2(sgmii_rxuserclk2),
|
||||
// GMII Interface
|
||||
.gmii_txd(sfp_gmii_txd_int),
|
||||
.gmii_tx_en(sfp_gmii_tx_en_int),
|
||||
.gmii_tx_er(sfp_gmii_tx_er_int),
|
||||
.gmii_rxd(sfp_gmii_rxd_int),
|
||||
.gmii_rx_dv(sfp_gmii_rx_dv_int),
|
||||
.gmii_rx_er(sfp_gmii_rx_er_int),
|
||||
.gmii_isolate(),
|
||||
// Management: Alternative to MDIO Interface
|
||||
.configuration_vector(sfp_config_vect),
|
||||
// General IO's
|
||||
.status_vector(sfp_status_vect),
|
||||
.reset(rst_int),
|
||||
.signal_detect(1'b1),
|
||||
|
||||
.gt0_qplloutclk_in(1'b0),
|
||||
.gt0_qplloutrefclk_in(1'b0),
|
||||
.gt0_rxchariscomma_out(),
|
||||
.gt0_rxcharisk_out(),
|
||||
.gt0_rxbyteisaligned_out(),
|
||||
.gt0_rxbyterealign_out(),
|
||||
.gt0_rxcommadet_out(),
|
||||
.gt0_txpolarity_in(SFP_INVERT),
|
||||
.gt0_txdiffctrl_in(4'b1000),
|
||||
.gt0_txpostcursor_in(5'b00000),
|
||||
.gt0_txprecursor_in(5'b00000),
|
||||
.gt0_rxpolarity_in(SFP_INVERT),
|
||||
.gt0_txinhibit_in(1'b0),
|
||||
.gt0_txprbssel_in(3'b000),
|
||||
.gt0_txprbsforceerr_in(1'b0),
|
||||
.gt0_rxprbscntreset_in(1'b0),
|
||||
.gt0_rxprbserr_out(),
|
||||
.gt0_rxprbssel_in(3'b000),
|
||||
.gt0_loopback_in(3'b000),
|
||||
.gt0_txresetdone_out(),
|
||||
.gt0_rxresetdone_out(),
|
||||
.gt0_rxdisperr_out(),
|
||||
.gt0_txbufstatus_out(),
|
||||
.gt0_rxnotintable_out(),
|
||||
.gt0_eyescanreset_in(1'b0),
|
||||
.gt0_eyescandataerror_out(),
|
||||
.gt0_eyescantrigger_in(1'b0),
|
||||
.gt0_rxcdrhold_in(1'b0),
|
||||
.gt0_rxpmareset_in(1'b0),
|
||||
.gt0_txpmareset_in(1'b0),
|
||||
.gt0_rxpcsreset_in(1'b0),
|
||||
.gt0_txpcsreset_in(1'b0),
|
||||
.gt0_rxbufreset_in(1'b0),
|
||||
.gt0_rxbufstatus_out(),
|
||||
.gt0_rxdfelpmreset_in(1'b0),
|
||||
.gt0_rxdfeagcovrden_in(1'b0),
|
||||
.gt0_rxlpmen_in(1'b1),
|
||||
.gt0_rxmonitorout_out(),
|
||||
.gt0_rxmonitorsel_in(2'b00),
|
||||
.gt0_drpaddr_in(9'd0),
|
||||
.gt0_drpclk_in(1'b0),
|
||||
.gt0_drpdi_in(9'd0),
|
||||
.gt0_drpdo_out(),
|
||||
.gt0_drpen_in(1'b0),
|
||||
.gt0_drprdy_out(),
|
||||
.gt0_drpwe_in(1'b0),
|
||||
.gt0_dmonitorout_out()
|
||||
);
|
||||
|
||||
assign sfp_gmii_clk_en_int = 1'b1;
|
||||
|
||||
// SGMII interface debug:
|
||||
// SW1:1 (sw[0]) off for payload byte, on for status vector
|
||||
// SW1:2 (sw[1]) off for LSB of status vector, on for MSB
|
||||
assign led = sw[3] ? (sw[2] ? sfp_status_vect[15:8] : sfp_status_vect[7:0]) : led_int;
|
||||
|
||||
wire phy_rgmii_rx_clk_int;
|
||||
wire [3:0] phy_rgmii_rxd_int;
|
||||
wire phy_rgmii_rx_ctl_int;
|
||||
wire phy_rgmii_tx_clk_int;
|
||||
wire [3:0] phy_rgmii_txd_int;
|
||||
wire phy_rgmii_tx_ctl_int;
|
||||
|
||||
wire phy_gmii_rx_clk_int;
|
||||
wire [7:0] phy_gmii_rxd_int;
|
||||
wire phy_gmii_rx_dv_int;
|
||||
wire phy_gmii_rx_er_int;
|
||||
wire phy_gmii_gtx_clk_int;
|
||||
wire phy_gmii_tx_clk_int;
|
||||
wire [7:0] phy_gmii_txd_int;
|
||||
wire phy_gmii_tx_en_int;
|
||||
wire phy_gmii_tx_er_int;
|
||||
|
||||
if (BASET_PHY_TYPE == "RGMII") begin : phy_if
|
||||
|
||||
assign phy_rgmii_rx_clk_int = phy_rx_clk;
|
||||
|
||||
// IODELAY elements for RGMII interface to PHY
|
||||
IDELAYCTRL
|
||||
idelayctrl_inst (
|
||||
.REFCLK(clk_200mhz_int),
|
||||
.RST(rst_int),
|
||||
.RDY()
|
||||
);
|
||||
|
||||
for (genvar n = 0; n < 4; n = n + 1) begin : phy_rxd_idelay_bit
|
||||
|
||||
IDELAYE2 #(
|
||||
.IDELAY_TYPE("FIXED")
|
||||
)
|
||||
idelay_inst (
|
||||
.IDATAIN(phy_rxd[n]),
|
||||
.DATAOUT(phy_rgmii_rxd_int[n]),
|
||||
.DATAIN(1'b0),
|
||||
.C(1'b0),
|
||||
.CE(1'b0),
|
||||
.INC(1'b0),
|
||||
.CINVCTRL(1'b0),
|
||||
.CNTVALUEIN(5'd0),
|
||||
.CNTVALUEOUT(),
|
||||
.LD(1'b0),
|
||||
.LDPIPEEN(1'b0),
|
||||
.REGRST(1'b0)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
IDELAYE2 #(
|
||||
.IDELAY_TYPE("FIXED")
|
||||
)
|
||||
phy_rx_ctl_idelay (
|
||||
.IDATAIN(phy_rx_dv),
|
||||
.DATAOUT(phy_rgmii_rx_ctl_int),
|
||||
.DATAIN(1'b0),
|
||||
.C(1'b0),
|
||||
.CE(1'b0),
|
||||
.INC(1'b0),
|
||||
.CINVCTRL(1'b0),
|
||||
.CNTVALUEIN(5'd0),
|
||||
.CNTVALUEOUT(),
|
||||
.LD(1'b0),
|
||||
.LDPIPEEN(1'b0),
|
||||
.REGRST(1'b0)
|
||||
);
|
||||
|
||||
assign phy_gtx_clk = phy_rgmii_tx_clk_int;
|
||||
assign phy_txd[3:0] = phy_rgmii_txd_int;
|
||||
assign phy_tx_en = phy_rgmii_tx_ctl_int;
|
||||
|
||||
assign phy_txd[7:4] = '0;
|
||||
assign phy_tx_er = 1'b0;
|
||||
|
||||
assign phy_gmii_rx_clk_int = 1'b0;
|
||||
assign phy_gmii_rxd_int = '0;
|
||||
assign phy_gmii_rx_dv_int = 1'b0;
|
||||
assign phy_gmii_rx_er_int = 1'b0;
|
||||
assign phy_gmii_tx_clk_int = 1'b0;
|
||||
|
||||
end else begin : phy_if
|
||||
|
||||
assign phy_rgmii_rx_clk_int = 1'b0;
|
||||
assign phy_rgmii_rxd_int = '0;
|
||||
assign phy_rgmii_rx_ctl_int = 1'b0;
|
||||
|
||||
assign phy_gmii_rx_clk_int = phy_rx_clk;
|
||||
assign phy_gmii_rxd_int = phy_rxd;
|
||||
assign phy_gmii_rx_dv_int = phy_rx_dv;
|
||||
assign phy_gmii_rx_er_int = phy_rx_er;
|
||||
|
||||
assign phy_gtx_clk = phy_gmii_gtx_clk_int;
|
||||
assign phy_gmii_tx_clk_int = phy_tx_clk;
|
||||
assign phy_txd = phy_gmii_txd_int;
|
||||
assign phy_tx_en = phy_gmii_tx_en_int;
|
||||
assign phy_tx_er = phy_gmii_tx_er_int;
|
||||
|
||||
end
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.USE_CLK90(USE_CLK90),
|
||||
.BASET_PHY_TYPE(BASET_PHY_TYPE),
|
||||
.SFP_INVERT(SFP_INVERT)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk(clk_int),
|
||||
.clk90(clk90_int),
|
||||
.rst(rst_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.btnu(btnu_int),
|
||||
.btnl(btnl_int),
|
||||
.btnd(btnd_int),
|
||||
.btnr(btnr_int),
|
||||
.btnc(btnc_int),
|
||||
.sw(sw_int),
|
||||
.led(led_int),
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
.uart_rxd(uart_rxd_int),
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rts(uart_rts),
|
||||
.uart_cts(uart_cts_int),
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-X SFP
|
||||
*/
|
||||
.sfp_gmii_clk(sfp_gmii_clk_int),
|
||||
.sfp_gmii_rst(sfp_gmii_rst_int),
|
||||
.sfp_gmii_clk_en(sfp_gmii_clk_en_int),
|
||||
.sfp_gmii_rxd(sfp_gmii_rxd_int),
|
||||
.sfp_gmii_rx_dv(sfp_gmii_rx_dv_int),
|
||||
.sfp_gmii_rx_er(sfp_gmii_rx_er_int),
|
||||
.sfp_gmii_txd(sfp_gmii_txd_int),
|
||||
.sfp_gmii_tx_en(sfp_gmii_tx_en_int),
|
||||
.sfp_gmii_tx_er(sfp_gmii_tx_er_int),
|
||||
.sfp_tx_disable_b(sfp_tx_disable_b),
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T GMII/RGMII/SGMII
|
||||
*/
|
||||
.phy_sgmii_clk(phy_sgmii_clk_int),
|
||||
.phy_sgmii_rst(phy_sgmii_rst_int),
|
||||
.phy_sgmii_clk_en(phy_sgmii_clk_en_int),
|
||||
.phy_sgmii_rxd(phy_sgmii_rxd_int),
|
||||
.phy_sgmii_rx_dv(phy_sgmii_rx_dv_int),
|
||||
.phy_sgmii_rx_er(phy_sgmii_rx_er_int),
|
||||
.phy_sgmii_txd(phy_sgmii_txd_int),
|
||||
.phy_sgmii_tx_en(phy_sgmii_tx_en_int),
|
||||
.phy_sgmii_tx_er(phy_sgmii_tx_er_int),
|
||||
.phy_rgmii_rx_clk(phy_rgmii_rx_clk_int),
|
||||
.phy_rgmii_rxd(phy_rgmii_rxd_int),
|
||||
.phy_rgmii_rx_ctl(phy_rgmii_rx_ctl_int),
|
||||
.phy_rgmii_tx_clk(phy_rgmii_tx_clk_int),
|
||||
.phy_rgmii_txd(phy_rgmii_txd_int),
|
||||
.phy_rgmii_tx_ctl(phy_rgmii_tx_ctl_int),
|
||||
.phy_gmii_rx_clk(phy_gmii_rx_clk_int),
|
||||
.phy_gmii_rxd(phy_gmii_rxd_int),
|
||||
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
|
||||
.phy_gmii_rx_er(phy_gmii_rx_er_int),
|
||||
.phy_gmii_gtx_clk(phy_gmii_gtx_clk_int),
|
||||
.phy_gmii_tx_clk(phy_gmii_tx_clk_int),
|
||||
.phy_gmii_txd(phy_gmii_txd_int),
|
||||
.phy_gmii_tx_en(phy_gmii_tx_en_int),
|
||||
.phy_gmii_tx_er(phy_gmii_tx_er_int),
|
||||
.phy_reset_n(phy_reset_n),
|
||||
.phy_int_n(phy_int_n)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
453
example/KC705/fpga/rtl/fpga_core.sv
Normal file
453
example/KC705/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,453 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter FAMILY = "kintex7",
|
||||
// Use 90 degree clock for RGMII transmit
|
||||
parameter logic USE_CLK90 = 1'b1,
|
||||
// BASE-T PHY type (GMII, RGMII, SGMII)
|
||||
parameter BASET_PHY_TYPE = "GMII",
|
||||
// Invert SFP data pins
|
||||
parameter logic SFP_INVERT = 1'b1
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire logic clk,
|
||||
input wire logic clk90,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
input wire logic btnu,
|
||||
input wire logic btnl,
|
||||
input wire logic btnd,
|
||||
input wire logic btnr,
|
||||
input wire logic btnc,
|
||||
input wire logic [7:0] sw,
|
||||
output wire logic [7:0] led,
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
input wire logic uart_rxd,
|
||||
output wire logic uart_txd,
|
||||
output wire logic uart_rts,
|
||||
input wire logic uart_cts,
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-X SFP
|
||||
*/
|
||||
input wire logic sfp_gmii_clk,
|
||||
input wire logic sfp_gmii_rst,
|
||||
input wire logic sfp_gmii_clk_en,
|
||||
input wire logic [7:0] sfp_gmii_rxd,
|
||||
input wire logic sfp_gmii_rx_dv,
|
||||
input wire logic sfp_gmii_rx_er,
|
||||
output wire logic [7:0] sfp_gmii_txd,
|
||||
output wire logic sfp_gmii_tx_en,
|
||||
output wire logic sfp_gmii_tx_er,
|
||||
output wire logic sfp_tx_disable_b,
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T
|
||||
*/
|
||||
input wire logic phy_sgmii_clk,
|
||||
input wire logic phy_sgmii_rst,
|
||||
input wire logic phy_sgmii_clk_en,
|
||||
input wire logic [7:0] phy_sgmii_rxd,
|
||||
input wire logic phy_sgmii_rx_dv,
|
||||
input wire logic phy_sgmii_rx_er,
|
||||
output wire logic [7:0] phy_sgmii_txd,
|
||||
output wire logic phy_sgmii_tx_en,
|
||||
output wire logic phy_sgmii_tx_er,
|
||||
input wire logic phy_rgmii_rx_clk,
|
||||
input wire logic [3:0] phy_rgmii_rxd,
|
||||
input wire logic phy_rgmii_rx_ctl,
|
||||
output wire logic phy_rgmii_tx_clk,
|
||||
output wire logic [3:0] phy_rgmii_txd,
|
||||
output wire logic phy_rgmii_tx_ctl,
|
||||
input wire logic phy_gmii_rx_clk,
|
||||
input wire logic [7:0] phy_gmii_rxd,
|
||||
input wire logic phy_gmii_rx_dv,
|
||||
input wire logic phy_gmii_rx_er,
|
||||
output wire logic phy_gmii_gtx_clk,
|
||||
input wire logic phy_gmii_tx_clk,
|
||||
output wire logic [7:0] phy_gmii_txd,
|
||||
output wire logic phy_gmii_tx_en,
|
||||
output wire logic phy_gmii_tx_er,
|
||||
output wire logic phy_reset_n,
|
||||
input wire logic phy_int_n
|
||||
);
|
||||
|
||||
assign led = sw;
|
||||
|
||||
// UART
|
||||
assign uart_rts = 0;
|
||||
|
||||
taxi_axis_if #(.DATA_W(8)) axis_uart();
|
||||
|
||||
taxi_uart
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis_tx(axis_uart),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis_rx(axis_uart),
|
||||
|
||||
/*
|
||||
* UART interface
|
||||
*/
|
||||
.rxd(uart_rxd),
|
||||
.txd(uart_txd),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_busy(),
|
||||
.rx_busy(),
|
||||
.rx_overrun_error(),
|
||||
.rx_frame_error(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.prescale(16'(125000000/115200/8))
|
||||
);
|
||||
|
||||
// BASE-T PHY
|
||||
assign phy_reset_n = !rst;
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
|
||||
|
||||
if (BASET_PHY_TYPE == "GMII") begin : baset_mac_gmii
|
||||
|
||||
taxi_eth_mac_1g_gmii_fifo #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
eth_mac_inst (
|
||||
.gtx_clk(clk),
|
||||
.gtx_rst(rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_eth),
|
||||
.m_axis_tx_cpl(axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_eth),
|
||||
|
||||
/*
|
||||
* GMII interface
|
||||
*/
|
||||
.gmii_rx_clk(phy_gmii_rx_clk),
|
||||
.gmii_rxd(phy_gmii_rxd),
|
||||
.gmii_rx_dv(phy_gmii_rx_dv),
|
||||
.gmii_rx_er(phy_gmii_rx_er),
|
||||
.gmii_tx_clk(phy_gmii_gtx_clk),
|
||||
.mii_tx_clk(phy_gmii_tx_clk),
|
||||
.gmii_txd(phy_gmii_txd),
|
||||
.gmii_tx_en(phy_gmii_tx_en),
|
||||
.gmii_tx_er(phy_gmii_tx_er),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
.link_speed(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
assign phy_sgmii_txd = '0;
|
||||
assign phy_sgmii_tx_en = 1'b0;
|
||||
assign phy_sgmii_tx_er = 1'b0;
|
||||
|
||||
assign phy_rgmii_tx_clk = 1'b0;
|
||||
assign phy_rgmii_txd = '0;
|
||||
assign phy_rgmii_tx_ctl = 1'b0;
|
||||
|
||||
end else if (BASET_PHY_TYPE == "RGMII") begin : baset_mac_rgmii
|
||||
|
||||
taxi_eth_mac_1g_rgmii_fifo #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.USE_CLK90(USE_CLK90),
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
eth_mac_inst (
|
||||
.gtx_clk(clk),
|
||||
.gtx_clk90(clk90),
|
||||
.gtx_rst(rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_eth),
|
||||
.m_axis_tx_cpl(axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_eth),
|
||||
|
||||
/*
|
||||
* RGMII interface
|
||||
*/
|
||||
.rgmii_rx_clk(phy_rgmii_rx_clk),
|
||||
.rgmii_rxd(phy_rgmii_rxd),
|
||||
.rgmii_rx_ctl(phy_rgmii_rx_ctl),
|
||||
.rgmii_tx_clk(phy_rgmii_tx_clk),
|
||||
.rgmii_txd(phy_rgmii_txd),
|
||||
.rgmii_tx_ctl(phy_rgmii_tx_ctl),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
.link_speed(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
assign phy_gmii_gtx_clk = 1'b0;
|
||||
assign phy_gmii_txd = '0;
|
||||
assign phy_gmii_tx_en = 1'b0;
|
||||
assign phy_gmii_tx_er = 1'b0;
|
||||
|
||||
assign phy_sgmii_txd = '0;
|
||||
assign phy_sgmii_tx_en = 1'b0;
|
||||
assign phy_sgmii_tx_er = 1'b0;
|
||||
|
||||
end else if (BASET_PHY_TYPE == "SGMII") begin : baset_mac_sgmii
|
||||
|
||||
taxi_eth_mac_1g_fifo #(
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
eth_mac_inst (
|
||||
.rx_clk(phy_sgmii_clk),
|
||||
.rx_rst(phy_sgmii_rst),
|
||||
.tx_clk(phy_sgmii_clk),
|
||||
.tx_rst(phy_sgmii_rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_eth),
|
||||
.m_axis_tx_cpl(axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_eth),
|
||||
|
||||
/*
|
||||
* GMII interface
|
||||
*/
|
||||
.gmii_rxd(phy_sgmii_rxd),
|
||||
.gmii_rx_dv(phy_sgmii_rx_dv),
|
||||
.gmii_rx_er(phy_sgmii_rx_er),
|
||||
.gmii_txd(phy_sgmii_txd),
|
||||
.gmii_tx_en(phy_sgmii_tx_en),
|
||||
.gmii_tx_er(phy_sgmii_tx_er),
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
.rx_clk_enable(phy_sgmii_clk_en),
|
||||
.tx_clk_enable(phy_sgmii_clk_en),
|
||||
.rx_mii_select(1'b0),
|
||||
.tx_mii_select(1'b0),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
assign phy_gmii_gtx_clk = 1'b0;
|
||||
assign phy_gmii_txd = '0;
|
||||
assign phy_gmii_tx_en = 1'b0;
|
||||
assign phy_gmii_tx_er = 1'b0;
|
||||
|
||||
assign phy_rgmii_tx_clk = 1'b0;
|
||||
assign phy_rgmii_txd = '0;
|
||||
assign phy_rgmii_tx_ctl = 1'b0;
|
||||
|
||||
end
|
||||
|
||||
// SFP+
|
||||
assign sfp_tx_disable_b = 1'b1;
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp_eth();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl();
|
||||
|
||||
taxi_eth_mac_1g_fifo #(
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
eth_mac_inst (
|
||||
.rx_clk(sfp_gmii_clk),
|
||||
.rx_rst(sfp_gmii_rst),
|
||||
.tx_clk(sfp_gmii_clk),
|
||||
.tx_rst(sfp_gmii_rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_sfp_eth),
|
||||
.m_axis_tx_cpl(axis_sfp_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_sfp_eth),
|
||||
|
||||
/*
|
||||
* GMII interface
|
||||
*/
|
||||
.gmii_rxd(sfp_gmii_rxd),
|
||||
.gmii_rx_dv(sfp_gmii_rx_dv),
|
||||
.gmii_rx_er(sfp_gmii_rx_er),
|
||||
.gmii_txd(sfp_gmii_txd),
|
||||
.gmii_tx_en(sfp_gmii_tx_en),
|
||||
.gmii_tx_er(sfp_gmii_tx_er),
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
.rx_clk_enable(sfp_gmii_clk_en),
|
||||
.tx_clk_enable(sfp_gmii_clk_en),
|
||||
.rx_mii_select(1'b0),
|
||||
.tx_mii_select(1'b0),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user