From 544ae2e2ca6c7b8c14038f5313a2bf328f322d26 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 11 Jul 2026 01:01:49 -0700 Subject: [PATCH] eth: Add ordered set and idle match outputs to BASE-R/XGMII modules for USXGMII Signed-off-by: Alex Forencich --- src/eth/rtl/taxi_axis_baser_rx_32.sv | 49 +++++++++--- src/eth/rtl/taxi_axis_baser_rx_64.sv | 38 +++++++-- src/eth/rtl/taxi_axis_xgmii_rx_32.sv | 24 +++++- src/eth/rtl/taxi_axis_xgmii_rx_64.sv | 34 ++++++-- src/eth/rtl/taxi_xgmii_baser_dec.sv | 80 ++++++++++++++++--- .../test_taxi_axis_baser_rx_32.sv | 4 + .../test_taxi_axis_baser_rx_64.sv | 4 + .../test_taxi_axis_xgmii_rx_32.sv | 4 + .../test_taxi_axis_xgmii_rx_64.sv | 4 + 9 files changed, 198 insertions(+), 43 deletions(-) diff --git a/src/eth/rtl/taxi_axis_baser_rx_32.sv b/src/eth/rtl/taxi_axis_baser_rx_32.sv index abc5fb7..291f29a 100644 --- a/src/eth/rtl/taxi_axis_baser_rx_32.sv +++ b/src/eth/rtl/taxi_axis_baser_rx_32.sv @@ -47,6 +47,8 @@ module taxi_axis_baser_rx_32 # output wire logic [23:0] rx_os, output wire logic rx_os_sig, output wire logic rx_os_valid, + output wire logic rx_os_match, + output wire logic rx_idle_match, /* * PTP @@ -209,6 +211,8 @@ logic rx_os_0_reg = 1'b0; logic rx_os_4_reg = 1'b0; logic rx_os_sig_reg = 1'b0; logic rx_os_valid_reg = 1'b0; +logic [1:0] rx_os_match_reg = '0; +logic [1:0] rx_idle_match_reg = '0; logic start_packet_reg = 1'b0, start_packet_next; logic frame_reg = 1'b0; @@ -255,9 +259,11 @@ if (PTP_TS_EN) begin assign m_axis_rx.tuser[1 +: PTP_TS_W] = ptp_ts_out_reg; end -assign rx_os = rx_os_reg; +assign rx_os = {rx_os_reg[7:0], rx_os_reg[15:8], rx_os_reg[23:16]}; assign rx_os_sig = rx_os_sig_reg; assign rx_os_valid = rx_os_valid_reg; +assign rx_os_match = rx_os_match_reg[1]; +assign rx_idle_match = rx_idle_match_reg[1]; assign rx_start_packet = start_packet_reg; @@ -655,6 +661,8 @@ always_ff @(posedge clk) begin input_data_d0_reg <= encoded_rx_data_reg; framing_error_reg <= frame_reg; frame_reg <= 1'b0; + rx_os_match_reg <= '0; + rx_idle_match_reg <= {rx_idle_match_reg[0], 1'b1}; end BLOCK_TYPE_OS_4[7:4]: begin input_data_d0_reg <= encoded_rx_data_reg; @@ -674,9 +682,13 @@ always_ff @(posedge clk) begin framing_error_reg <= frame_reg; frame_reg <= 1'b1; rx_os_0_reg <= 1'b1; - rx_os_reg[7:0] <= encoded_rx_data_reg[31:24]; - rx_os_reg[15:8] <= encoded_rx_data_reg[23:16]; - rx_os_reg[23:16] <= encoded_rx_data_reg[15:8]; + rx_os_reg <= encoded_rx_data_reg[31:8]; + if (rx_os_reg == encoded_rx_data_reg[31:8]) begin + rx_os_match_reg <= {rx_os_match_reg[0], 1'b1}; + end else begin + rx_os_match_reg <= '0; + end + rx_idle_match_reg <= '0; end BLOCK_TYPE_OS_04[7:4]: begin input_data_d0_reg <= encoded_rx_data_reg; @@ -695,9 +707,7 @@ always_ff @(posedge clk) begin framing_error_reg <= frame_reg; frame_reg <= 1'b0; rx_os_0_reg <= 1'b1; - rx_os_reg[7:0] <= encoded_rx_data_reg[31:24]; - rx_os_reg[15:8] <= encoded_rx_data_reg[23:16]; - rx_os_reg[23:16] <= encoded_rx_data_reg[15:8]; + rx_os_reg <= encoded_rx_data_reg[31:8]; end BLOCK_TYPE_TERM_0[7:4]: begin input_data_d0_reg <= encoded_rx_data_reg; // don't care @@ -809,13 +819,26 @@ always_ff @(posedge clk) begin if (rx_os_0_reg) begin rx_os_sig_reg <= encoded_rx_data_reg[3:0] == O_SIG_OS; - rx_os_valid_reg <= encoded_rx_data_reg[3:0] == O_SEQ_OS || encoded_rx_data_reg[3:0] == O_SIG_OS; + if (encoded_rx_data_reg[3:0] == O_SEQ_OS || encoded_rx_data_reg[3:0] == O_SIG_OS) begin + rx_os_valid_reg <= 1'b1; + end else begin + rx_os_match_reg <= '0; + end + rx_idle_match_reg <= '0; end else if (rx_os_4_reg) begin - rx_os_reg[7:0] <= encoded_rx_data_reg[31:24]; - rx_os_reg[15:8] <= encoded_rx_data_reg[23:16]; - rx_os_reg[23:16] <= encoded_rx_data_reg[15:8]; + rx_os_reg <= encoded_rx_data_reg[31:8]; rx_os_sig_reg <= encoded_rx_data_reg[7:4] == O_SIG_OS; - rx_os_valid_reg <= encoded_rx_data_reg[7:4] == O_SEQ_OS || encoded_rx_data_reg[7:4] == O_SIG_OS; + if (encoded_rx_data_reg[7:4] == O_SEQ_OS || encoded_rx_data_reg[7:4] == O_SIG_OS) begin + rx_os_valid_reg <= 1'b1; + if (rx_os_reg == encoded_rx_data_reg[31:8]) begin + rx_os_match_reg <= {rx_os_match_reg[0], 1'b1}; + end else begin + rx_os_match_reg <= '0; + end + end else begin + rx_os_match_reg <= '0; + end + rx_idle_match_reg <= '0; end end @@ -874,6 +897,8 @@ always_ff @(posedge clk) begin rx_os_0_reg <= 1'b0; rx_os_4_reg <= 1'b0; rx_os_valid_reg <= 1'b0; + rx_os_match_reg <= '0; + rx_idle_match_reg <= '0; start_packet_reg <= 1'b0; frame_reg <= 1'b0; diff --git a/src/eth/rtl/taxi_axis_baser_rx_64.sv b/src/eth/rtl/taxi_axis_baser_rx_64.sv index d2a18a5..c36d5af 100644 --- a/src/eth/rtl/taxi_axis_baser_rx_64.sv +++ b/src/eth/rtl/taxi_axis_baser_rx_64.sv @@ -47,6 +47,8 @@ module taxi_axis_baser_rx_64 # output wire logic [23:0] rx_os, output wire logic rx_os_sig, output wire logic rx_os_valid, + output wire logic rx_os_match, + output wire logic rx_idle_match, /* * PTP @@ -193,6 +195,8 @@ logic m_axis_rx_tuser_reg = 1'b0, m_axis_rx_tuser_next; logic [23:0] rx_os_reg = '0; logic rx_os_sig_reg = 1'b0; logic rx_os_valid_reg = 1'b0; +logic [1:0] rx_os_match_reg = '0; +logic [1:0] rx_idle_match_reg = '0; logic [1:0] start_packet_reg = 2'b00; logic frame_reg = 1'b0; @@ -249,9 +253,11 @@ if (PTP_TS_EN) begin assign m_axis_rx.tuser[1 +: PTP_TS_W] = ptp_ts_out_reg; end -assign rx_os = rx_os_reg; +assign rx_os = {rx_os_reg[7:0], rx_os_reg[15:8], rx_os_reg[23:16]}; assign rx_os_sig = rx_os_sig_reg; assign rx_os_valid = rx_os_valid_reg; +assign rx_os_match = rx_os_match_reg[1]; +assign rx_idle_match = rx_idle_match_reg[1]; assign rx_start_packet = start_packet_reg; @@ -737,22 +743,38 @@ always_ff @(posedge clk) begin end // ordered sets + if (encoded_rx_data[7:4] == BLOCK_TYPE_CTRL[7:4]) begin + rx_os_match_reg <= '0; + rx_idle_match_reg <= {rx_idle_match_reg[0], 1'b1}; + end if (encoded_rx_data[7:4] == BLOCK_TYPE_OS_4[7:4] || encoded_rx_data[7:4] == BLOCK_TYPE_OS_04[7:4]) begin - rx_os_reg[7:0] <= encoded_rx_data[63:56]; - rx_os_reg[15:8] <= encoded_rx_data[55:48]; - rx_os_reg[23:16] <= encoded_rx_data[47:40]; + rx_os_reg <= encoded_rx_data[63:40]; rx_os_sig_reg <= encoded_rx_data[39:36] == O_SIG_OS; if ((encoded_rx_data[7:0] == BLOCK_TYPE_OS_4 || encoded_rx_data[7:0] == BLOCK_TYPE_OS_04) || (encoded_rx_data[39:36] == O_SEQ_OS || encoded_rx_data[39:36] == O_SIG_OS)) begin rx_os_valid_reg <= 1'b1; + if (rx_os_reg == encoded_rx_data[63:40]) begin + rx_os_match_reg <= {rx_os_match_reg[0], 1'b1}; + end else begin + rx_os_match_reg <= '0; + end + end else begin + rx_os_match_reg <= '0; end + rx_idle_match_reg <= '0; end else if (encoded_rx_data[7:4] == BLOCK_TYPE_OS_0[7:4] || encoded_rx_data[7:4] == BLOCK_TYPE_OS_START[7:4]) begin - rx_os_reg[7:0] <= encoded_rx_data[31:24]; - rx_os_reg[15:8] <= encoded_rx_data[23:16]; - rx_os_reg[23:16] <= encoded_rx_data[15:8]; + rx_os_reg <= encoded_rx_data[31:8]; rx_os_sig_reg <= encoded_rx_data[35:32] == O_SIG_OS; if ((encoded_rx_data[7:0] == BLOCK_TYPE_OS_0 || encoded_rx_data[7:0] == BLOCK_TYPE_OS_START) || (encoded_rx_data[35:32] == O_SEQ_OS || encoded_rx_data[35:32] == O_SIG_OS)) begin rx_os_valid_reg <= 1'b1; + if (rx_os_reg == encoded_rx_data[31:8]) begin + rx_os_match_reg <= {rx_os_match_reg[0], 1'b1}; + end else begin + rx_os_match_reg <= '0; + end + end else begin + rx_os_match_reg <= '0; end + rx_idle_match_reg <= '0; end // check for framing errors @@ -891,6 +913,8 @@ always_ff @(posedge clk) begin m_axis_rx_tvalid_reg <= 1'b0; rx_os_valid_reg <= 1'b0; + rx_os_match_reg <= '0; + rx_idle_match_reg <= '0; start_packet_reg <= 2'b00; frame_reg <= 1'b0; diff --git a/src/eth/rtl/taxi_axis_xgmii_rx_32.sv b/src/eth/rtl/taxi_axis_xgmii_rx_32.sv index c633590..697d4f5 100644 --- a/src/eth/rtl/taxi_axis_xgmii_rx_32.sv +++ b/src/eth/rtl/taxi_axis_xgmii_rx_32.sv @@ -45,6 +45,8 @@ module taxi_axis_xgmii_rx_32 # output wire logic [23:0] rx_os, output wire logic rx_os_sig, output wire logic rx_os_valid, + output wire logic rx_os_match, + output wire logic rx_idle_match, /* * PTP @@ -158,6 +160,8 @@ logic m_axis_rx_tuser_reg = 1'b0, m_axis_rx_tuser_next; logic [23:0] rx_os_reg = '0; logic rx_os_sig_reg = 1'b0; logic rx_os_valid_reg = 1'b0; +logic [1:0] rx_os_match_reg = '0; +logic [1:0] rx_idle_match_reg = '0; logic start_packet_reg = 1'b0, start_packet_next; @@ -203,9 +207,11 @@ if (PTP_TS_EN) begin assign m_axis_rx.tuser[1 +: PTP_TS_W] = ptp_ts_out_reg; end -assign rx_os = rx_os_reg; +assign rx_os = {rx_os_reg[7:0], rx_os_reg[15:8], rx_os_reg[23:16]}; assign rx_os_sig = rx_os_sig_reg; assign rx_os_valid = rx_os_valid_reg; +assign rx_os_match = rx_os_match_reg[1]; +assign rx_idle_match = rx_idle_match_reg[1]; assign rx_start_packet = start_packet_reg; @@ -585,12 +591,20 @@ always_ff @(posedge clk) begin end // ordered sets + if (xgmii_rxc == 4'b1111) begin + rx_os_match_reg <= '0; + rx_idle_match_reg <= {rx_idle_match_reg[0], 1'b1}; + end if (xgmii_rxc == 4'b0001 && (xgmii_rxd[7:0] == XGMII_SEQ_OS || xgmii_rxd[7:0] == XGMII_SIG_OS)) begin - rx_os_reg[7:0] <= xgmii_rxd[31:24]; - rx_os_reg[15:8] <= xgmii_rxd[23:16]; - rx_os_reg[23:16] <= xgmii_rxd[15:8]; + rx_os_reg <= xgmii_rxd[31:8]; rx_os_sig_reg <= xgmii_rxd[7:0] == XGMII_SIG_OS; rx_os_valid_reg <= 1'b1; + if (rx_os_reg == xgmii_rxd[31:8]) begin + rx_os_match_reg <= {rx_os_match_reg[0], 1'b1}; + end else begin + rx_os_match_reg <= '0; + end + rx_idle_match_reg <= '0; end term_lane_d0_reg <= term_lane_reg; @@ -611,6 +625,8 @@ always_ff @(posedge clk) begin m_axis_rx_tvalid_reg <= 1'b0; rx_os_valid_reg <= 1'b0; + rx_os_match_reg <= '0; + rx_idle_match_reg <= '0; start_packet_reg <= 1'b0; diff --git a/src/eth/rtl/taxi_axis_xgmii_rx_64.sv b/src/eth/rtl/taxi_axis_xgmii_rx_64.sv index cd764bf..a5edfaa 100644 --- a/src/eth/rtl/taxi_axis_xgmii_rx_64.sv +++ b/src/eth/rtl/taxi_axis_xgmii_rx_64.sv @@ -46,6 +46,8 @@ module taxi_axis_xgmii_rx_64 # output wire logic [23:0] rx_os, output wire logic rx_os_sig, output wire logic rx_os_valid, + output wire logic rx_os_match, + output wire logic rx_idle_match, /* * PTP @@ -163,6 +165,8 @@ logic m_axis_rx_tuser_reg = 1'b0, m_axis_rx_tuser_next; logic [23:0] rx_os_reg = '0; logic rx_os_sig_reg = 1'b0; logic rx_os_valid_reg = 1'b0; +logic [1:0] rx_os_match_reg = '0; +logic [1:0] rx_idle_match_reg = '0; logic [1:0] start_packet_reg = 2'b00; @@ -218,9 +222,11 @@ if (PTP_TS_EN) begin assign m_axis_rx.tuser[1 +: PTP_TS_W] = ptp_ts_out_reg; end -assign rx_os = rx_os_reg; +assign rx_os = {rx_os_reg[7:0], rx_os_reg[15:8], rx_os_reg[23:16]}; assign rx_os_sig = rx_os_sig_reg; assign rx_os_valid = rx_os_valid_reg; +assign rx_os_match = rx_os_match_reg[1]; +assign rx_idle_match = rx_idle_match_reg[1]; assign rx_start_packet = start_packet_reg; @@ -644,18 +650,30 @@ always_ff @(posedge clk) begin end // ordered sets + if (xgmii_rxc == 8'b11111111) begin + rx_os_match_reg <= '0; + rx_idle_match_reg <= {rx_idle_match_reg[0], 1'b1}; + end if (xgmii_rxc[7:4] == 4'b0001 && (xgmii_rxd[39:32] == XGMII_SEQ_OS || xgmii_rxd[39:32] == XGMII_SIG_OS)) begin - rx_os_reg[7:0] <= xgmii_rxd[63:56]; - rx_os_reg[15:8] <= xgmii_rxd[55:48]; - rx_os_reg[23:16] <= xgmii_rxd[47:40]; + rx_os_reg <= xgmii_rxd[63:40]; rx_os_sig_reg <= xgmii_rxd[39:32] == XGMII_SIG_OS; rx_os_valid_reg <= 1'b1; + if (rx_os_reg == xgmii_rxd[63:40]) begin + rx_os_match_reg <= {rx_os_match_reg[0], 1'b1}; + end else begin + rx_os_match_reg <= '0; + end + rx_idle_match_reg <= '0; end else if (xgmii_rxc[3:0] == 4'b0001 && (xgmii_rxd[7:0] == XGMII_SEQ_OS || xgmii_rxd[7:0] == XGMII_SIG_OS)) begin - rx_os_reg[7:0] <= xgmii_rxd[31:24]; - rx_os_reg[15:8] <= xgmii_rxd[23:16]; - rx_os_reg[23:16] <= xgmii_rxd[15:8]; + rx_os_reg <= xgmii_rxd[31:8]; rx_os_sig_reg <= xgmii_rxd[7:0] == XGMII_SIG_OS; rx_os_valid_reg <= 1'b1; + if (rx_os_reg == xgmii_rxd[31:8]) begin + rx_os_match_reg <= {rx_os_match_reg[0], 1'b1}; + end else begin + rx_os_match_reg <= '0; + end + rx_idle_match_reg <= '0; end lanes_swapped_d1_reg <= lanes_swapped_reg; @@ -678,6 +696,8 @@ always_ff @(posedge clk) begin m_axis_rx_tvalid_reg <= 1'b0; rx_os_valid_reg <= 1'b0; + rx_os_match_reg <= '0; + rx_idle_match_reg <= '0; start_packet_reg <= 2'b00; diff --git a/src/eth/rtl/taxi_xgmii_baser_dec.sv b/src/eth/rtl/taxi_xgmii_baser_dec.sv index 6bb35ca..3405690 100644 --- a/src/eth/rtl/taxi_xgmii_baser_dec.sv +++ b/src/eth/rtl/taxi_xgmii_baser_dec.sv @@ -47,6 +47,8 @@ module taxi_xgmii_baser_dec # output wire logic [23:0] rx_os, output wire logic rx_os_sig, output wire logic rx_os_valid, + output wire logic rx_os_match, + output wire logic rx_idle_match, /* * Status @@ -140,6 +142,8 @@ logic [SEG_CNT-1:0] xgmii_rx_valid_reg = '0, xgmii_rx_valid_next; logic [23:0] rx_os_reg = '0, rx_os_next; logic rx_os_sig_reg = 1'b0, rx_os_sig_next; logic rx_os_valid_reg = 1'b0, rx_os_valid_next; +logic [1:0] rx_os_match_reg = '0, rx_os_match_next; +logic [1:0] rx_idle_match_reg = '0, rx_idle_match_next; logic rx_bad_block_reg = 1'b0, rx_bad_block_next; logic rx_sequence_error_reg = 1'b0, rx_sequence_error_next; @@ -149,9 +153,11 @@ assign xgmii_rxd = xgmii_rxd_reg[DATA_W-1:0]; assign xgmii_rxc = xgmii_rxc_reg[CTRL_W-1:0]; assign xgmii_rx_valid = GBX_IF_EN ? xgmii_rx_valid_reg[0] : 1'b1; -assign rx_os = rx_os_reg; +assign rx_os = {rx_os_reg[7:0], rx_os_reg[15:8], rx_os_reg[23:16]}; assign rx_os_sig = rx_os_sig_reg; assign rx_os_valid = rx_os_valid_reg; +assign rx_os_match = rx_os_match_reg[1]; +assign rx_idle_match = rx_idle_match_reg[1]; assign rx_bad_block = rx_bad_block_reg; assign rx_sequence_error = rx_sequence_error_reg; @@ -196,6 +202,8 @@ always_comb begin rx_os_next = '0; rx_os_sig_next = 1'b0; rx_os_valid_next = 1'b0; + rx_os_match_next = rx_os_match_reg; + rx_idle_match_next = rx_idle_match_reg; rx_bad_block_next = 1'b0; rx_sequence_error_next = 1'b0; @@ -276,6 +284,8 @@ always_comb begin xgmii_rxd_next = decoded_ctrl; xgmii_rxc_next = 8'hff; rx_bad_block_next = decode_err != 0; + rx_os_match_next = '0; + rx_idle_match_next = {rx_idle_match_reg[0], 1'b1}; end BLOCK_TYPE_OS_4[7:4]: begin // D7 D6 D5 O4 C3 C2 C1 C0 BT @@ -283,23 +293,33 @@ always_comb begin xgmii_rxc_next[3:0] = 4'hf; xgmii_rxd_next[63:40] = encoded_rx_data_int[63:40]; xgmii_rxc_next[7:4] = 4'h1; - rx_os_next[7:0] = encoded_rx_data_int[63:56]; - rx_os_next[15:8] = encoded_rx_data_int[55:48]; - rx_os_next[23:16] = encoded_rx_data_int[47:40]; + rx_os_next = encoded_rx_data_int[63:40]; if (encoded_rx_data_int[39:36] == O_SEQ_OS) begin xgmii_rxd_next[39:32] = XGMII_SEQ_OS; rx_bad_block_next = decode_err[3:0] != 0; rx_os_sig_next = 1'b0; rx_os_valid_next = 1'b1; + if (rx_os_reg == encoded_rx_data_int[63:40]) begin + rx_os_match_next = {rx_os_match_reg[0], 1'b1}; + end else begin + rx_os_match_next = '0; + end end else if (encoded_rx_data_int[39:36] == O_SIG_OS) begin xgmii_rxd_next[39:32] = XGMII_SIG_OS; rx_bad_block_next = decode_err[3:0] != 0; rx_os_sig_next = 1'b1; rx_os_valid_next = 1'b1; + if (rx_os_reg == encoded_rx_data_int[63:40]) begin + rx_os_match_next = {rx_os_match_reg[0], 1'b1}; + end else begin + rx_os_match_next = '0; + end end else begin xgmii_rxd_next[39:32] = XGMII_ERROR; rx_bad_block_next = 1'b1; + rx_os_match_next = '0; end + rx_idle_match_next = '0; end BLOCK_TYPE_START_4[7:4]: begin // D7 D6 D5 C3 C2 C1 C0 BT @@ -313,27 +333,37 @@ always_comb begin // D7 D6 D5 O0 D3 D2 D1 BT xgmii_rxd_next[31:8] = encoded_rx_data_int[31:8]; xgmii_rxc_next[3:0] = 4'h1; - rx_os_next[7:0] = encoded_rx_data_int[31:24]; - rx_os_next[15:8] = encoded_rx_data_int[23:16]; - rx_os_next[23:16] = encoded_rx_data_int[15:8]; + rx_os_next = encoded_rx_data_int[31:8]; if (encoded_rx_data_int[35:32] == O_SEQ_OS) begin xgmii_rxd_next[7:0] = XGMII_SEQ_OS; rx_bad_block_next = 1'b0; rx_os_sig_next = 1'b0; rx_os_valid_next = 1'b1; + if (rx_os_reg == encoded_rx_data_int[31:8]) begin + rx_os_match_next = {rx_os_match_reg[0], 1'b1}; + end else begin + rx_os_match_next = '0; + end end else if (encoded_rx_data_int[35:32] == O_SIG_OS) begin xgmii_rxd_next[7:0] = XGMII_SIG_OS; rx_bad_block_next = 1'b0; rx_os_sig_next = 1'b1; rx_os_valid_next = 1'b1; + if (rx_os_reg == encoded_rx_data_int[31:8]) begin + rx_os_match_next = {rx_os_match_reg[0], 1'b1}; + end else begin + rx_os_match_next = '0; + end end else begin xgmii_rxd_next[7:0] = XGMII_ERROR; rx_bad_block_next = 1'b1; + rx_os_match_next = '0; end xgmii_rxd_next[63:32] = {encoded_rx_data_int[63:40], XGMII_START}; xgmii_rxc_next[7:4] = 4'h1; rx_sequence_error_next = frame_reg; frame_next = 1'b1; + rx_idle_match_next = '0; end BLOCK_TYPE_OS_04[7:4]: begin // D7 D6 D5 O4 O0 D3 D2 D1 BT @@ -350,21 +380,31 @@ always_comb begin end xgmii_rxd_next[63:40] = encoded_rx_data_int[63:40]; xgmii_rxc_next[7:4] = 4'h1; - rx_os_next[7:0] = encoded_rx_data_int[63:56]; - rx_os_next[15:8] = encoded_rx_data_int[55:48]; - rx_os_next[23:16] = encoded_rx_data_int[47:40]; + rx_os_next = encoded_rx_data_int[63:40]; if (encoded_rx_data_int[39:36] == O_SEQ_OS) begin xgmii_rxd_next[39:32] = XGMII_SEQ_OS; rx_os_sig_next = 1'b0; rx_os_valid_next = 1'b1; + if (rx_os_reg == encoded_rx_data_int[63:40]) begin + rx_os_match_next = {rx_os_match_reg[0], 1'b1}; + end else begin + rx_os_match_next = '0; + end end else if (encoded_rx_data_int[39:36] == O_SIG_OS) begin xgmii_rxd_next[39:32] = XGMII_SIG_OS; rx_os_sig_next = 1'b1; rx_os_valid_next = 1'b1; + if (rx_os_reg == encoded_rx_data_int[63:40]) begin + rx_os_match_next = {rx_os_match_reg[0], 1'b1}; + end else begin + rx_os_match_next = '0; + end end else begin xgmii_rxd_next[39:32] = XGMII_ERROR; rx_bad_block_next = 1'b1; + rx_os_match_next = '0; end + rx_idle_match_next = '0; end BLOCK_TYPE_START_0[7:4]: begin // D7 D6 D5 D4 D3 D2 D1 BT @@ -378,25 +418,35 @@ always_comb begin // C7 C6 C5 C4 O0 D3 D2 D1 BT xgmii_rxd_next[31:8] = encoded_rx_data_int[31:8]; xgmii_rxc_next[3:0] = 4'h1; - rx_os_next[7:0] = encoded_rx_data_int[31:24]; - rx_os_next[15:8] = encoded_rx_data_int[23:16]; - rx_os_next[23:16] = encoded_rx_data_int[15:8]; + rx_os_next = encoded_rx_data_int[31:8]; if (encoded_rx_data_int[35:32] == O_SEQ_OS) begin xgmii_rxd_next[7:0] = XGMII_SEQ_OS; rx_bad_block_next = decode_err[7:4] != 0; rx_os_sig_next = 1'b0; rx_os_valid_next = 1'b1; + if (rx_os_reg == encoded_rx_data_int[31:8]) begin + rx_os_match_next = {rx_os_match_reg[0], 1'b1}; + end else begin + rx_os_match_next = '0; + end end else if (encoded_rx_data_int[35:32] == O_SIG_OS) begin xgmii_rxd_next[7:0] = XGMII_SIG_OS; rx_bad_block_next = decode_err[7:4] != 0; rx_os_sig_next = 1'b1; rx_os_valid_next = 1'b1; + if (rx_os_reg == encoded_rx_data_int[31:8]) begin + rx_os_match_next = {rx_os_match_reg[0], 1'b1}; + end else begin + rx_os_match_next = '0; + end end else begin xgmii_rxd_next[7:0] = XGMII_ERROR; rx_bad_block_next = 1'b1; + rx_os_match_next = '0; end xgmii_rxd_next[63:32] = decoded_ctrl[63:32]; xgmii_rxc_next[7:4] = 4'hf; + rx_idle_match_next = '0; end BLOCK_TYPE_TERM_0[7:4]: begin // C7 C6 C5 C4 C3 C2 C1 BT @@ -517,6 +567,8 @@ always_ff @(posedge clk) begin rx_os_reg <= rx_os_next; rx_os_sig_reg <= rx_os_sig_next; rx_os_valid_reg <= rx_os_valid_next; + rx_os_match_reg <= rx_os_match_next; + rx_idle_match_reg <= rx_idle_match_next; rx_bad_block_reg <= rx_bad_block_next; rx_sequence_error_reg <= rx_sequence_error_next; @@ -525,6 +577,8 @@ always_ff @(posedge clk) begin if (rst) begin xgmii_rx_valid_reg <= '0; rx_os_valid_reg <= 1'b0; + rx_os_match_reg <= '0; + rx_idle_match_reg <= '0; frame_reg <= 1'b0; end end diff --git a/src/eth/tb/taxi_axis_baser_rx_32/test_taxi_axis_baser_rx_32.sv b/src/eth/tb/taxi_axis_baser_rx_32/test_taxi_axis_baser_rx_32.sv index 252af60..c92dc40 100644 --- a/src/eth/tb/taxi_axis_baser_rx_32/test_taxi_axis_baser_rx_32.sv +++ b/src/eth/tb/taxi_axis_baser_rx_32/test_taxi_axis_baser_rx_32.sv @@ -44,6 +44,8 @@ taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W)) m_axis_rx(); logic [23:0] rx_os; logic rx_os_sig; logic rx_os_valid; +logic rx_os_match; +logic rx_idle_match; logic [PTP_TS_W-1:0] ptp_ts; @@ -101,6 +103,8 @@ uut ( .rx_os(rx_os), .rx_os_sig(rx_os_sig), .rx_os_valid(rx_os_valid), + .rx_os_match(rx_os_match), + .rx_idle_match(rx_idle_match), /* * PTP diff --git a/src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.sv b/src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.sv index 2bdd509..39d85a8 100644 --- a/src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.sv +++ b/src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.sv @@ -43,6 +43,8 @@ taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W)) m_axis_rx(); logic [23:0] rx_os; logic rx_os_sig; logic rx_os_valid; +logic rx_os_match; +logic rx_idle_match; logic [PTP_TS_W-1:0] ptp_ts; @@ -97,6 +99,8 @@ uut ( .rx_os(rx_os), .rx_os_sig(rx_os_sig), .rx_os_valid(rx_os_valid), + .rx_os_match(rx_os_match), + .rx_idle_match(rx_idle_match), /* * PTP diff --git a/src/eth/tb/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.sv b/src/eth/tb/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.sv index 908200a..16899db 100644 --- a/src/eth/tb/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.sv +++ b/src/eth/tb/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.sv @@ -41,6 +41,8 @@ taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W)) m_axis_rx(); logic [23:0] rx_os; logic rx_os_sig; logic rx_os_valid; +logic rx_os_match; +logic rx_idle_match; logic [PTP_TS_W-1:0] ptp_ts; @@ -93,6 +95,8 @@ uut ( .rx_os(rx_os), .rx_os_sig(rx_os_sig), .rx_os_valid(rx_os_valid), + .rx_os_match(rx_os_match), + .rx_idle_match(rx_idle_match), /* * PTP diff --git a/src/eth/tb/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.sv b/src/eth/tb/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.sv index 9b1ca76..f286233 100644 --- a/src/eth/tb/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.sv +++ b/src/eth/tb/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.sv @@ -42,6 +42,8 @@ taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W)) m_axis_rx(); logic [23:0] rx_os; logic rx_os_sig; logic rx_os_valid; +logic rx_os_match; +logic rx_idle_match; logic [PTP_TS_W-1:0] ptp_ts; @@ -95,6 +97,8 @@ uut ( .rx_os(rx_os), .rx_os_sig(rx_os_sig), .rx_os_valid(rx_os_valid), + .rx_os_match(rx_os_match), + .rx_idle_match(rx_idle_match), /* * PTP