eth/example/HTG_ZRF8: Add example design for HTG-ZRF8-EM and HTG-ZRF8-R2

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/eth/example/HTG_ZRF8/fpga/README.md

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+# Taxi Example Design for HTG-ZRF8
+
+## Introduction
+
+This example design targets the HiTech Global HTG-ZRF8-R2 and HTG-ZRF8-EM FPGA boards.
+
+The design places looped-back MACs on the FMC+ for use with SFP and QSFP FMC adapters, as well as XFCP on the USB UART for monitoring and control.  The RF data converters are also enabled at 1 Gsps per channel.
+
+*  USB UART
+    *  XFCP (921600 baud)
+*  QSFP28
+    *  Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
+
+## Board details
+
+*  FPGA: xczu48dr-ffvg1517-2-e
+*  USB UART: Silicon Labs CP2103
+
+## Licensing
+
+*  Toolchain
+    *  Vivado Enterprise (requires license)
+*  IP
+    *  No licensed vendor IP or 3rd party IP
+
+## How to build
+
+Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensure that the Xilinx Vivado toolchain components are in PATH.
+
+## FMC
+
+All variants of the HTG-ZRF8 only connect 8 MGT lanes to the FMC+, DP0-7, so on some FMC/FMC+ boards, not all of the connectors will be usable.
+
+Another complicating factor is that the FMC+ connector has GA0/GA1 wired to ground, which causes an address conflict between the FMC EEPROM and any SFP/QSFP modules that can be connected to the FMC I2C pins.  Fixing the address conflict necessitates modification of either the FPGA board or the FMC board.
+
+Additionally, the HTG-ZRF8-EM only connects LA0-LA9, which can cause some problems with driving module control lines on FMC/FMC+.  In some cases, alternative approaches might be required to use a given FMC/FMC+, including module configuration via I2C as well as modifications to the FMC/FMC+ board.  
+
+This design has been tested with:
+
+*  HTG-FMC-QSFP28-DEG90
+    *  QSFP on DP0-3, DP4-7 not connected
+    *  resetl: on disconnected pin LA31_P, pulled high via R10 (OK)
+    *  lpmode: on disconnected pin LA32_N, pulled high via R3 (no good on -EM)
+    *  modsell: on disconnected pin LA31_N, pulled low via R8 (OK)
+
+Since the Si5341 PLL is directly connected to the MGTREFCLK pins for the sites connected to the FMC+, no reference clocks are required from the FMC+ and as such any reference PLL on the FMC does not need to be configured and any oscillators can be disabled.
+
+## Board configuration (HTG-ZRF8-R2)
+
+For correct operation, several DIP switches need to be set correctly.  Additionally, some other component-level modifications may be required.
+
+DIP switch settings:
+
+*  S2.1-4: all ON for JTAG boot
+*  S3.1: OFF (enable U19 outputs)
+*  S3.2: don't care (U19 IN_SEL1)
+*  S3.4: don't care (ON to disable PS ref clock)
+
+The PLL configuration in this design ignores the IN_SEL pins, so S3.2 has no effect.  The other DIP switches do not affect the operation of this design.  A simple "safe" configuration is S3 all OFF and S2 all ON.
+
+When using optical modules or active optical cables, it is necessary to pull the lpmode pins low and the resetl pins high to enable the lasers.  For I2C communication with the module, modsell must be pulled low.
+
+Additionally, the standard SFP/QSFP I2C address of 0x50 conflicts with the address 0 FMC EEPROM address.  The FMC address pins (GA0 and GA1) are controlled by R430/R411 and R441/R451.  See the table below for how to configure these resistors.
+
+| Address | R430 | R411 | R441 | R451 | 
+| ------- | ---- | ---- | ---- | ---- |
+| 0       | 0    | DNP  | 0    | DNP  |
+| 1       | DNP  | 4.7K | 0    | DNP  |
+| 2       | 0    | DNP  | DNP  | 4.7K |
+| 3       | DNP  | 4.7K | DNP  | 4.7K |
+
+## Board configuration (HTG-ZRF8-EM)
+
+For correct operation, several DIP switches need to be set correctly.  Additionally, some other component-level modifications may be required.
+
+DIP switch settings:
+
+*  S2.1: OFF (enable U48 outputs)
+*  S2.3: don't care (U48 IN_SEL0)
+*  S2.2: don't care (U48 IN_SEL1)
+*  S2.4: don't care (ON to disable PS ref clock)
+*  S3.1-4: all ON for JTAG boot
+
+The PLL configuration in this design ignores the IN_SEL pins, so S2.2 and S2.3 have no effect.  The other DIP switches do not affect the operation of this design.  A simple "safe" configuration is S2 all OFF and S3 all ON.
+
+When using optical modules or active optical cables, it is necessary to pull the lpmode pins low and the resetl pins high to enable the lasers.  For I2C communication with the module, modsell must be pulled low.  On the HTG-ZRF8-EM, only the first 20 LA pins (pairs LA0-LA9) are connected on the FMC+, so for some adapters, the lpmode and reset pins may not be connected to the FPGA.
+
+Additionally, the standard SFP/QSFP I2C address of 0x50 conflicts with the address 0 FMC EEPROM address.  The FMC address pins (GA0 and GA1) are controlled by R471/R472 and R478/R479.  See the table below for how to configure these resistors.
+
+| Address | R471 | R472 | R478 | R479 | 
+| ------- | ---- | ---- | ---- | ---- |
+| 0       | 0    | DNP  | 0    | DNP  |
+| 1       | DNP  | 4.7K | 0    | DNP  |
+| 2       | 0    | DNP  | DNP  | 4.7K |
+| 3       | DNP  | 4.7K | DNP  | 4.7K |
+
+## How to test
+
+Run `make program` to program the board with Vivado.
+
+To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback.  Do not connect the looped-back MAC to a network as the reflected packets may cause problems.

src/eth/example/HTG_ZRF8/fpga/cfgmclk.xdc

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+# Timing constraints for cfgmclk
+
+# Fcfgmclk is 50 MHz +/- 15%, rounding to 15 ns period
+create_clock -period 15.000 -name cfgmclk [get_pins startupe3_inst/CFGMCLK]
+

src/eth/example/HTG_ZRF8/fpga/common/vivado.mk

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+# SPDX-License-Identifier: MIT
+###################################################################
+#
+# Xilinx Vivado FPGA Makefile
+#
+# Copyright (c) 2016-2025 Alex Forencich
+#
+###################################################################
+#
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - list of source files
+# INC_FILES - list of include files
+# XDC_FILES - list of timing constraint files
+# XCI_FILES - list of IP XCI files
+# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
+# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
+#
+# Note: both SYN_FILES and INC_FILES support file list files.  File list
+# files are files with a .f extension that contain a list of additional
+# files to include, one path relative to the .f file location per line.
+# The .f files are processed recursively, and then the complete file list
+# is de-duplicated, with later files in the list taking precedence.
+#
+# Example:
+#
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+#
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include $(CONFIG)
+
+FPGA_TOP ?= fpga
+PROJECT ?= $(FPGA_TOP)
+XDC_FILES ?= $(PROJECT).xdc
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
+INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
+
+###################################################################
+# Main Targets
+#
+# all: build everything (fpga)
+# fpga: build FPGA config
+# vivado: open project in Vivado
+# tmpclean: remove intermediate files
+# clean: remove output files and project files
+# distclean: remove archived output files
+###################################################################
+
+all: fpga
+
+fpga: $(PROJECT).bit
+
+vivado: $(PROJECT).xpr
+	vivado $(PROJECT).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+	-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+
+# create fresh project if Makefile or IP files have changed
+create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
+	echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
+	for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+# source config TCL scripts if any source file has changed
+update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
+	echo "open_project -quiet $(PROJECT).xpr" > $@
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+$(PROJECT).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
+	echo "open_project $(PROJECT).xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
+	echo "open_project $(PROJECT).xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "open_run impl_1" >> run_impl.tcl
+	echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
+	echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# output files (including potentially bit, bin, ltx, and xsa)
+$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
+	echo "open_project $(PROJECT).xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
+	echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
+	echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
+	if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi

src/eth/example/HTG_ZRF8/fpga/fpga_10g_EM_ZU48DR/Makefile

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+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xczu48dr-ffvg1517-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = zynquplusRFSOC
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga_em.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/../pll/pll_i2c_init_em.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga_em.xdc
+XDC_FILES += ../cfgmclk.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl
+IP_TCL_FILES += ../ip/usp_rfdc_1ghz_1gsps.tcl
+
+# Configuration
+# CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl

src/eth/example/HTG_ZRF8/fpga/fpga_10g_R2_ZU48DR/Makefile

@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xczu48dr-ffvg1517-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = zynquplusRFSOC
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga_r2.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/../pll/pll_i2c_init_r2.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga_r2.xdc
+XDC_FILES += ../cfgmclk.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl
+IP_TCL_FILES += ../ip/usp_rfdc_1ghz_1gsps.tcl
+
+# Configuration
+# CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl

src/eth/example/HTG_ZRF8/fpga/fpga_EM_ZU48DR/Makefile

@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xczu48dr-ffvg1517-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = zynquplusRFSOC
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga_em.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/../pll/pll_i2c_init_em.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga_em.xdc
+XDC_FILES += ../cfgmclk.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl
+IP_TCL_FILES += ../ip/usp_rfdc_1ghz_1gsps.tcl
+
+# Configuration
+# CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl

src/eth/example/HTG_ZRF8/fpga/fpga_R2_ZU48DR/Makefile

@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xczu48dr-ffvg1517-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = zynquplusRFSOC
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga_r2.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(RTL_DIR)/../pll/pll_i2c_init_r2.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga_r2.xdc
+XDC_FILES += ../cfgmclk.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl
+IP_TCL_FILES += ../ip/usp_rfdc_1ghz_1gsps.tcl
+
+# Configuration
+# CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl

src/eth/example/HTG_ZRF8/fpga/fpga_em.xdc

@@ -0,0 +1,554 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the HiTech Global HTG-ZRF8-EM board
+# part: xczu28dr-ffvg1517-2-e
+# part: xczu48dr-ffvg1517-2-e
+
+# General configuration
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+
+# System clocks
+# DDR4 clocks from U48 (300 MHz)
+#set_property -dict {LOC G13  IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_p] ;# U48.59 OUT9_P
+#set_property -dict {LOC G12  IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_n] ;# U48.58 OUT9_N
+#create_clock -period 3.333 -name sys_clk_ddr4 [get_ports sys_clk_ddr4_p]
+
+#set_property -dict {LOC AP8  IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_c_p] ;# U48.51 OUT7_P
+#set_property -dict {LOC AR9  IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_c_n] ;# U48.50 OUT7_N
+#create_clock -period 3.333 -name sys_clk_ddr4_c [get_ports sys_clk_ddr4_c_p]
+
+# User clock from U48 (200 MHz)
+set_property -dict {LOC AV6  IOSTANDARD LVDS_25} [get_ports clk_pl_user_p] ;# U48.54 OUT8_P
+set_property -dict {LOC AV5  IOSTANDARD LVDS_25} [get_ports clk_pl_user_n] ;# U48.53 OUT8_N
+create_clock -period 5.000 -name clk_pl_user [get_ports clk_pl_user_p]
+
+# Source pin is in an HDIO bank, so it must be routed to an MMCM via a BUFG
+set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets clk_pl_user_bufg]
+
+# PLL refclk from U2 (250 MHz)
+set_property -dict {LOC AU4  IOSTANDARD LVDS_25} [get_ports fpga_refclk_p] ;# U2.60 CLKout13_P
+set_property -dict {LOC AU3  IOSTANDARD LVDS_25} [get_ports fpga_refclk_n] ;# U2.61 CLKout13_N
+create_clock -period 4.000 -name fpga_refclk [get_ports fpga_refclk_p]
+
+# Source pin is in an HDIO bank, so it must be routed to an MMCM via a BUFG
+set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets fpga_refclk_int fpga_refclk_bufg_inst_n_0]
+
+# PLL sysref from U2
+set_property -dict {LOC AT5  IOSTANDARD LVDS_25} [get_ports fpga_sysref_p] ;# U2.62 CLKout12_P
+set_property -dict {LOC AU5  IOSTANDARD LVDS_25} [get_ports fpga_sysref_n] ;# U2.63 CLKout12_N
+create_clock -period 100.000 -name fpga_sysref [get_ports fpga_sysref_p]
+
+# LEDs
+set_property -dict {LOC AP6  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[0]}] ;# D16
+set_property -dict {LOC AW5  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[1]}] ;# D15
+set_property -dict {LOC AW6  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[2]}] ;# D14
+set_property -dict {LOC AR6  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[3]}] ;# D3
+
+set_false_path -to [get_ports {led[*]}]
+set_output_delay 0 [get_ports {led[*]}]
+
+# Push buttons
+set_property -dict {LOC AG14 IOSTANDARD LVCMOS12} [get_ports {btn}] ;# PB4
+
+set_false_path -from [get_ports {btn}]
+set_input_delay 0 [get_ports {btn}]
+
+# DIP switches
+set_property -dict {LOC E19  IOSTANDARD LVCMOS12} [get_ports {sw[0]}] ;# S1.1
+set_property -dict {LOC D19  IOSTANDARD LVCMOS12} [get_ports {sw[1]}] ;# S1.2
+set_property -dict {LOC C18  IOSTANDARD LVCMOS12} [get_ports {sw[2]}] ;# S1.3
+set_property -dict {LOC A25  IOSTANDARD LVCMOS12} [get_ports {sw[3]}] ;# S1.4
+
+set_false_path -from [get_ports {sw[*]}]
+set_input_delay 0 [get_ports {sw[*]}]
+
+# GPIO
+set_property -dict {LOC N21  IOSTANDARD LVCMOS12} [get_ports {gpio[0]}] ;# J32.1
+set_property -dict {LOC M12  IOSTANDARD LVCMOS12} [get_ports {gpio[1]}] ;# J32.3
+set_property -dict {LOC F22  IOSTANDARD LVCMOS12} [get_ports {gpio[2]}] ;# J32.5
+set_property -dict {LOC B23  IOSTANDARD LVCMOS12} [get_ports {gpio[3]}] ;# J32.7
+set_property -dict {LOC G24  IOSTANDARD LVCMOS12} [get_ports {gpio[4]}] ;# J32.9
+set_property -dict {LOC D20  IOSTANDARD LVCMOS12} [get_ports {gpio[5]}] ;# J32.11
+set_property -dict {LOC J24  IOSTANDARD LVCMOS12} [get_ports {gpio[6]}] ;# J32.13
+set_property -dict {LOC H15  IOSTANDARD LVCMOS12} [get_ports {gpio[7]}] ;# J32.15
+
+set_false_path -to [get_ports {gpio[*]}]
+set_output_delay 0 [get_ports {gpio[*]}]
+
+# UART
+set_property -dict {LOC AV7  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_rxd]
+set_property -dict {LOC AV8  IOSTANDARD LVCMOS33} [get_ports uart_txd]
+set_property -dict {LOC AU8  IOSTANDARD LVCMOS33} [get_ports uart_rts]
+set_property -dict {LOC AU7  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_cts]
+set_property -dict {LOC AT6  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_rst_n]
+set_property -dict {LOC AT7  IOSTANDARD LVCMOS33} [get_ports uart_suspend_n]
+
+set_false_path -to [get_ports {uart_rxd uart_cts uart_rst_n}]
+set_output_delay 0 [get_ports {uart_rxd uart_cts uart_rst_n}]
+set_false_path -from [get_ports {uart_txd uart_rts uart_suspend_n}]
+set_input_delay 0 [get_ports {uart_txd uart_rts uart_suspend_n}]
+
+# I2C
+set_property -dict {LOC AU2  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
+set_property -dict {LOC AU1  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
+set_property -dict {LOC AV2  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c_rst_n]
+
+set_false_path -to [get_ports {i2c_sda i2c_scl i2c_rst_n}]
+set_output_delay 0 [get_ports {i2c_sda i2c_scl i2c_rst_n}]
+set_false_path -from [get_ports {i2c_sda i2c_scl}]
+set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
+
+# DDR4 SODIMM
+#set_property -dict {LOC E13  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[0]}]
+#set_property -dict {LOC A12  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[1]}]
+#set_property -dict {LOC F12  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[2]}]
+#set_property -dict {LOC A11  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[3]}]
+#set_property -dict {LOC F10  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[4]}]
+#set_property -dict {LOC G10  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[5]}]
+#set_property -dict {LOC D11  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[6]}]
+#set_property -dict {LOC H13  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[7]}]
+#set_property -dict {LOC C12  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[8]}]
+#set_property -dict {LOC F11  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[9]}]
+#set_property -dict {LOC B12  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[10]}]
+#set_property -dict {LOC H10  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[11]}]
+#set_property -dict {LOC E12  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[12]}]
+#set_property -dict {LOC C13  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[13]}]
+#set_property -dict {LOC D13  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[14]}]
+#set_property -dict {LOC B13  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[15]}]
+#set_property -dict {LOC A14  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[16]}]
+
+#set_property -dict {LOC J10  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_act_n}]
+#set_property -dict {LOC K11  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_alert_n}]
+
+#set_property -dict {LOC E11  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_ba[0]}]
+#set_property -dict {LOC B15  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_ba[1]}]
+#set_property -dict {LOC H11  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_bg[0]}]
+#set_property -dict {LOC H12  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_bg[1]}]
+
+#set_property -dict {LOC J11  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_cke[0]}]
+#set_property -dict {LOC K10  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_cke[1]}]
+#set_property -dict {LOC J14  IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_ck_t[0]}]
+#set_property -dict {LOC J13  IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_ck_c[0]}]
+#set_property -dict {LOC K13  IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_ck_t[1]}]
+#set_property -dict {LOC K12  IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_ck_c[1]}]
+#set_property -dict {LOC A15  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_cs_n[0]}]
+#set_property -dict {LOC C15  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_cs_n[1]}]
+#set_property -dict {LOC D14  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_cs_n[2]}]
+#set_property -dict {LOC G14  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_cs_n[3]}]
+
+#set_property -dict {LOC C21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[0]}]
+#set_property -dict {LOC A21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[1]}]
+#set_property -dict {LOC B24  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[2]}]
+#set_property -dict {LOC C22  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[3]}]
+#set_property -dict {LOC C20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[4]}]
+#set_property -dict {LOC A20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[5]}]
+#set_property -dict {LOC A24  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[6]}]
+#set_property -dict {LOC B20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[7]}]
+#set_property -dict {LOC D21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[8]}]
+#set_property -dict {LOC E21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[9]}]
+#set_property -dict {LOC E23  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[10]}]
+#set_property -dict {LOC E24  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[11]}]
+#set_property -dict {LOC G20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[12]}]
+#set_property -dict {LOC F20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[13]}]
+#set_property -dict {LOC F24  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[14]}]
+#set_property -dict {LOC E22  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[15]}]
+#set_property -dict {LOC G23  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[16]}]
+#set_property -dict {LOC H22  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[17]}]
+#set_property -dict {LOC J21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[18]}]
+#set_property -dict {LOC K24  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[19]}]
+#set_property -dict {LOC H21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[20]}]
+#set_property -dict {LOC G22  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[21]}]
+#set_property -dict {LOC L24  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[22]}]
+#set_property -dict {LOC H23  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[23]}]
+#set_property -dict {LOC L20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[24]}]
+#set_property -dict {LOC L23  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[25]}]
+#set_property -dict {LOC N19  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[26]}]
+#set_property -dict {LOC M20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[27]}]
+#set_property -dict {LOC L19  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[28]}]
+#set_property -dict {LOC L21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[29]}]
+#set_property -dict {LOC M19  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[30]}]
+#set_property -dict {LOC L22  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[31]}]
+#set_property -dict {LOC A19  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[32]}]
+#set_property -dict {LOC B19  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[33]}]
+#set_property -dict {LOC D15  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[34]}]
+#set_property -dict {LOC D16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[35]}]
+#set_property -dict {LOC A17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[36]}]
+#set_property -dict {LOC A16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[37]}]
+#set_property -dict {LOC C16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[38]}]
+#set_property -dict {LOC C17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[39]}]
+#set_property -dict {LOC G18  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[40]}]
+#set_property -dict {LOC E18  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[41]}]
+#set_property -dict {LOC F15  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[42]}]
+#set_property -dict {LOC G15  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[43]}]
+#set_property -dict {LOC E16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[44]}]
+#set_property -dict {LOC E17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[45]}]
+#set_property -dict {LOC F16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[46]}]
+#set_property -dict {LOC H18  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[47]}]
+#set_property -dict {LOC K17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[48]}]
+#set_property -dict {LOC J18  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[49]}]
+#set_property -dict {LOC H16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[50]}]
+#set_property -dict {LOC J16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[51]}]
+#set_property -dict {LOC J19  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[52]}]
+#set_property -dict {LOC H17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[53]}]
+#set_property -dict {LOC L17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[54]}]
+#set_property -dict {LOC K16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[55]}]
+#set_property -dict {LOC N15  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[56]}]
+#set_property -dict {LOC N17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[57]}]
+#set_property -dict {LOC L12  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[58]}]
+#set_property -dict {LOC M12  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[59]}]
+#set_property -dict {LOC M17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[60]}]
+#set_property -dict {LOC M15  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[61]}]
+#set_property -dict {LOC M13  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[62]}]
+#set_property -dict {LOC N13  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[63]}]
+#set_property -dict {LOC G9   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[64]}]
+#set_property -dict {LOC J9   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[65]}]
+#set_property -dict {LOC K9   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[66]}]
+#set_property -dict {LOC G7   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[67]}]
+#set_property -dict {LOC F9   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[68]}]
+#set_property -dict {LOC G6   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[69]}]
+#set_property -dict {LOC H7   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[70]}]
+#set_property -dict {LOC H6   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[71]}]
+
+#set_property -dict {LOC B22  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[0]}]
+#set_property -dict {LOC A22  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[0]}]
+#set_property -dict {LOC D23  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[1]}]
+#set_property -dict {LOC D24  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[1]}]
+#set_property -dict {LOC J20  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[2]}]
+#set_property -dict {LOC H20  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[2]}]
+#set_property -dict {LOC K21  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[3]}]
+#set_property -dict {LOC K22  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[3]}]
+#set_property -dict {LOC B18  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[4]}]
+#set_property -dict {LOC B17  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[4]}]
+#set_property -dict {LOC G19  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[5]}]
+#set_property -dict {LOC F19  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[5]}]
+#set_property -dict {LOC K19  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[6]}]
+#set_property -dict {LOC K18  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[6]}]
+#set_property -dict {LOC L15  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[7]}]
+#set_property -dict {LOC L14  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[7]}]
+#set_property -dict {LOC H8   IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[8]}]
+#set_property -dict {LOC G8   IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[8]}]
+
+#set_property -dict {LOC C23  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[0]}]
+#set_property -dict {LOC F21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[1]}]
+#set_property -dict {LOC J23  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[2]}]
+#set_property -dict {LOC N20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[3]}]
+#set_property -dict {LOC D18  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[4]}]
+#set_property -dict {LOC G17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[5]}]
+#set_property -dict {LOC J15  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[6]}]
+#set_property -dict {LOC N14  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[7]}]
+#set_property -dict {LOC J8   IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[8]}]
+
+#set_property -dict {LOC E14  IOSTANDARD LVCMOS12} [get_ports {ddr4_odt[0]}]
+#set_property -dict {LOC F14  IOSTANDARD LVCMOS12} [get_ports {ddr4_odt[1]}]
+#set_property -dict {LOC J7   IOSTANDARD LVCMOS12} [get_ports {ddr4_rst_n}]
+#set_property -dict {LOC B14  IOSTANDARD LVCMOS12} [get_ports {ddr4_par}]
+#set_property -dict {LOC C11  IOSTANDARD LVCMOS12} [get_ports {ddr4_event_n}]
+
+# DDR4 components
+#set_property -dict {LOC AN11 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[0]}]
+#set_property -dict {LOC AM14 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[1]}]
+#set_property -dict {LOC AM7  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[2]}]
+#set_property -dict {LOC AL14 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[3]}]
+#set_property -dict {LOC AL10 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[4]}]
+#set_property -dict {LOC AM12 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[5]}]
+#set_property -dict {LOC AN7  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[6]}]
+#set_property -dict {LOC AR11 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[7]}]
+#set_property -dict {LOC AM8  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[8]}]
+#set_property -dict {LOC AN12 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[9]}]
+#set_property -dict {LOC AN10 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[10]}]
+#set_property -dict {LOC AL7  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[11]}]
+#set_property -dict {LOC AK14 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[12]}]
+#set_property -dict {LOC AP11 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[13]}]
+#set_property -dict {LOC AM10 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[14]}]
+#set_property -dict {LOC AJ14 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[15]}]
+#set_property -dict {LOC AH13 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_a[16]}]
+
+#set_property -dict {LOC AP10 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_act_n}]
+#set_property -dict {LOC AM9  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_alert_n}]
+
+#set_property -dict {LOC AL8  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_ba[0]}]
+#set_property -dict {LOC AK13 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_ba[1]}]
+#set_property -dict {LOC AN8  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_bg[0]}]
+
+#set_property -dict {LOC AR9  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_cke}]
+#set_property -dict {LOC AM13 IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_c_ck_t}]
+#set_property -dict {LOC AN13 IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_c_ck_c}]
+#set_property -dict {LOC AL12 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_c_cs_n}]
+
+#set_property -dict {LOC AT10 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[0]}]
+#set_property -dict {LOC AW11 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[1]}]
+#set_property -dict {LOC AU10 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[2]}]
+#set_property -dict {LOC AV11 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[3]}]
+#set_property -dict {LOC AW8  IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[4]}]
+#set_property -dict {LOC AV12 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[5]}]
+#set_property -dict {LOC AW9  IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[6]}]
+#set_property -dict {LOC AU12 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[7]}]
+#set_property -dict {LOC AH16 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[8]}]
+#set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[9]}]
+#set_property -dict {LOC AF16 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[10]}]
+#set_property -dict {LOC AJ15 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[11]}]
+#set_property -dict {LOC AF17 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[12]}]
+#set_property -dict {LOC AK16 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[13]}]
+#set_property -dict {LOC AH15 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[14]}]
+#set_property -dict {LOC AK17 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[15]}]
+#set_property -dict {LOC AV15 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[16]}]
+#set_property -dict {LOC AU15 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[17]}]
+#set_property -dict {LOC AV13 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[18]}]
+#set_property -dict {LOC AW15 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[19]}]
+#set_property -dict {LOC AT15 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[20]}]
+#set_property -dict {LOC AT16 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[21]}]
+#set_property -dict {LOC AU14 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[22]}]
+#set_property -dict {LOC AU13 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[23]}]
+#set_property -dict {LOC AN15 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[24]}]
+#set_property -dict {LOC AR16 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[25]}]
+#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[26]}]
+#set_property -dict {LOC AP14 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[27]}]
+#set_property -dict {LOC AM17 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[28]}]
+#set_property -dict {LOC AR14 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[29]}]
+#set_property -dict {LOC AL17 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[30]}]
+#set_property -dict {LOC AP16 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[31]}]
+#set_property -dict {LOC AV18 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[32]}]
+#set_property -dict {LOC AU19 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[33]}]
+#set_property -dict {LOC AU18 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[34]}]
+#set_property -dict {LOC AU20 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[35]}]
+#set_property -dict {LOC AV17 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[36]}]
+#set_property -dict {LOC AV20 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[37]}]
+#set_property -dict {LOC AU17 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[38]}]
+#set_property -dict {LOC AW20 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[39]}]
+#set_property -dict {LOC AP18 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[40]}]
+#set_property -dict {LOC AR21 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[41]}]
+#set_property -dict {LOC AR19 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[42]}]
+#set_property -dict {LOC AT21 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[43]}]
+#set_property -dict {LOC AT19 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[44]}]
+#set_property -dict {LOC AP20 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[45]}]
+#set_property -dict {LOC AR18 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[46]}]
+#set_property -dict {LOC AP19 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[47]}]
+#set_property -dict {LOC AN21 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[48]}]
+#set_property -dict {LOC AL21 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[49]}]
+#set_property -dict {LOC AL19 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[50]}]
+#set_property -dict {LOC AM18 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[51]}]
+#set_property -dict {LOC AP21 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[52]}]
+#set_property -dict {LOC AL20 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[53]}]
+#set_property -dict {LOC AM19 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[54]}]
+#set_property -dict {LOC AN18 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[55]}]
+#set_property -dict {LOC AH18 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[56]}]
+#set_property -dict {LOC AG18 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[57]}]
+#set_property -dict {LOC AK22 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[58]}]
+#set_property -dict {LOC AF20 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[59]}]
+#set_property -dict {LOC AK21 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[60]}]
+#set_property -dict {LOC AF19 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[61]}]
+#set_property -dict {LOC AJ19 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[62]}]
+#set_property -dict {LOC AJ20 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dq[63]}]
+
+#set_property -dict {LOC AT12 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_t[0]}]
+#set_property -dict {LOC AT11 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_c[0]}]
+#set_property -dict {LOC AG17 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_t[1]}]
+#set_property -dict {LOC AH17 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_c[1]}]
+#set_property -dict {LOC AV16 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_t[2]}]
+#set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_c[2]}]
+#set_property -dict {LOC AN17 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_t[3]}]
+#set_property -dict {LOC AN16 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_c[3]}]
+#set_property -dict {LOC AV21 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_t[4]}]
+#set_property -dict {LOC AW21 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_c[4]}]
+#set_property -dict {LOC AR22 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_t[5]}]
+#set_property -dict {LOC AT22 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_c[5]}]
+#set_property -dict {LOC AL22 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_t[6]}]
+#set_property -dict {LOC AM22 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_c[6]}]
+#set_property -dict {LOC AG20 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_t[7]}]
+#set_property -dict {LOC AH20 IOSTANDARD DIFF_POD12} [get_ports {ddr4_c_dqs_c[7]}]
+
+#set_property -dict {LOC AV10 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dm_dbi_n[0]}]
+#set_property -dict {LOC AL16 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dm_dbi_n[1]}]
+#set_property -dict {LOC AW14 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dm_dbi_n[2]}]
+#set_property -dict {LOC AP13 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dm_dbi_n[3]}]
+#set_property -dict {LOC AW19 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dm_dbi_n[4]}]
+#set_property -dict {LOC AR17 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dm_dbi_n[5]}]
+#set_property -dict {LOC AM20 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dm_dbi_n[6]}]
+#set_property -dict {LOC AJ18 IOSTANDARD POD12_DCI} [get_ports {ddr4_c_dm_dbi_n[7]}]
+
+#set_property -dict {LOC AP9  IOSTANDARD LVCMOS12} [get_ports {ddr4_c_odt}]
+#set_property -dict {LOC AK12 IOSTANDARD LVCMOS12} [get_ports {ddr4_c_rst_n}]
+#set_property -dict {LOC AL9  IOSTANDARD LVCMOS12} [get_ports {ddr4_c_par}]
+#set_property -dict {LOC AR12 IOSTANDARD LVCMOS12} [get_ports {ddr4_c_ten}]
+
+# PCIe Interface
+#set_property -dict {LOC J33 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_129 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC J34 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_129 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC K36 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_129 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC K37 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_129 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC L33 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_129 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC L34 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_129 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC L38 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_129 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC L39 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_129 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC N33 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_129 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC N34 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_129 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC M36 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_129 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC M37 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_129 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC P35 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_129 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC P36 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_129 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC N38 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_129 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC N39 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_129 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC R33 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC R34 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC R38 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC R39 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC T35 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC T36 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC U38 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC U39 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC V35 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC V36 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC W38 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC W39 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC Y35 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC Y36 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC AA38} [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC AA39} [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC AA33} [get_ports pcie_refclk_p] ;# MGTREFCLK0P_128
+#set_property -dict {LOC AA34} [get_ports pcie_refclk_n] ;# MGTREFCLK0N_128
+#set_property -dict {LOC AJ13 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n]
+
+#set_false_path -from [get_ports {pcie_reset_n}]
+#set_input_delay 0 [get_ports {pcie_reset_n}]
+
+# 100 MHz MGT reference clock
+#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p]
+
+# FMC+ J25
+#set_property -dict {LOC B8   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[0]}]  ;# J25.G9  LA00_P_CC
+#set_property -dict {LOC B7   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[0]}]  ;# J25.G10 LA00_N_CC
+#set_property -dict {LOC E9   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[1]}]  ;# J25.D8  LA01_P_CC
+#set_property -dict {LOC E8   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[1]}]  ;# J25.D9  LA01_N_CC
+#set_property -dict {LOC A7   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[2]}]  ;# J25.H7  LA02_P
+#set_property -dict {LOC A6   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[2]}]  ;# J25.H8  LA02_N
+#set_property -dict {LOC E7   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[3]}]  ;# J25.G12 LA03_P
+#set_property -dict {LOC E6   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[3]}]  ;# J25.G13 LA03_N
+#set_property -dict {LOC F6   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[4]}]  ;# J25.H10 LA04_P
+#set_property -dict {LOC E6   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[4]}]  ;# J25.H11 LA04_N
+#set_property -dict {LOC D9   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[5]}]  ;# J25.D11 LA05_P
+#set_property -dict {LOC D8   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[5]}]  ;# J25.D12 LA05_N
+#set_property -dict {LOC D10  IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[6]}]  ;# J25.C10 LA06_P
+#set_property -dict {LOC C10  IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[6]}]  ;# J25.C11 LA06_N
+#set_property -dict {LOC C6   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[7]}]  ;# J25.H13 LA07_P
+#set_property -dict {LOC C5   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[7]}]  ;# J25.H14 LA07_N
+#set_property -dict {LOC B5   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[8]}]  ;# J25.G12 LA08_P
+#set_property -dict {LOC A5   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[8]}]  ;# J25.G13 LA08_N
+#set_property -dict {LOC A10  IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[9]}]  ;# J25.D14 LA09_P
+#set_property -dict {LOC A9   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[9]}]  ;# J25.D15 LA09_N
+
+#set_property -dict {LOC C8   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk0_m2c_p}] ;# J25.H4 CLK0_M2C_P
+#set_property -dict {LOC C7   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk0_m2c_n}] ;# J25.H5 CLK0_M2C_N
+
+#set_property -dict {LOC B10  IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_refclk_m2c_p}] ;# J25.L24 REFCLK_M2C_P
+#set_property -dict {LOC B9   IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_refclk_m2c_n}] ;# J25.L25 REFCLK_M2C_N
+
+#set_property -dict {LOC F17  IOSTANDARD LVCMOS12} [get_ports {fmc_prsnt_m2c}]        ;# J25.H2 PRSNT_M2C_L
+#set_property -dict {LOC M18  IOSTANDARD LVCMOS12} [get_ports {fmc_hspc_prsnt_m2c_l}] ;# J25.Z1 HSPC_PRSNT_M2C_L
+
+set_property -dict {LOC E33 } [get_ports {fmc_dp_c2m_p[0]}]  ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 from J25.C2  DP0_C2M_P
+set_property -dict {LOC E34 } [get_ports {fmc_dp_c2m_n[0]}]  ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 from J25.C3  DP0_C2M_N
+set_property -dict {LOC F36 } [get_ports {fmc_dp_m2c_p[0]}]  ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 from J25.C6  DP0_M2C_P
+set_property -dict {LOC F37 } [get_ports {fmc_dp_m2c_n[0]}]  ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 from J25.C7  DP0_M2C_N
+set_property -dict {LOC H31 } [get_ports {fmc_dp_c2m_p[1]}]  ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 from J25.A22 DP1_C2M_P
+set_property -dict {LOC H32 } [get_ports {fmc_dp_c2m_n[1]}]  ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 from J25.A23 DP1_C2M_N
+set_property -dict {LOC J38 } [get_ports {fmc_dp_m2c_p[1]}]  ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 from J25.A2  DP1_M2C_P
+set_property -dict {LOC J39 } [get_ports {fmc_dp_m2c_n[1]}]  ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 from J25.A3  DP1_M2C_N
+set_property -dict {LOC G33 } [get_ports {fmc_dp_c2m_p[2]}]  ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 from J25.A26 DP2_C2M_P
+set_property -dict {LOC G34 } [get_ports {fmc_dp_c2m_n[2]}]  ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 from J25.A27 DP2_C2M_N
+set_property -dict {LOC H36 } [get_ports {fmc_dp_m2c_p[2]}]  ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 from J25.A6  DP2_M2C_P
+set_property -dict {LOC H37 } [get_ports {fmc_dp_m2c_n[2]}]  ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 from J25.A7  DP2_M2C_N
+set_property -dict {LOC F31 } [get_ports {fmc_dp_c2m_p[3]}]  ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 from J25.A30 DP3_C2M_P
+set_property -dict {LOC F32 } [get_ports {fmc_dp_c2m_n[3]}]  ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 from J25.A31 DP3_C2M_N
+set_property -dict {LOC G38 } [get_ports {fmc_dp_m2c_p[3]}]  ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 from J25.A10 DP3_M2C_P
+set_property -dict {LOC G39 } [get_ports {fmc_dp_m2c_n[3]}]  ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 from J25.A11 DP3_M2C_N
+set_property -dict {LOC U33 } [get_ports fmc_mgt_refclk_0_0_p] ;# MGTREFCLK0P_130 from U48.42 OUT5_P
+set_property -dict {LOC U34 } [get_ports fmc_mgt_refclk_0_0_n] ;# MGTREFCLK0N_130 from U48.41 OUT5_N
+#set_property -dict {LOC T31 } [get_ports fmc_mgt_refclk_0_1_p] ;# MGTREFCLK1P_130 from J25.D4 GBTCLK0_M2C_P
+#set_property -dict {LOC T32 } [get_ports fmc_mgt_refclk_0_1_n] ;# MGTREFCLK1N_130 from J25.D5 GBTCLK0_M2C_N
+
+# reference clock
+create_clock -period 6.206 -name fmc_mgt_refclk_0_0 [get_ports fmc_mgt_refclk_0_0_p]
+#create_clock -period 6.400 -name fmc_mgt_refclk_0_1 [get_ports fmc_mgt_refclk_0_1_p]
+
+set_property -dict {LOC C33 } [get_ports {fmc_dp_c2m_p[4]}]  ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 from J25.A34 DP4_C2M_P
+set_property -dict {LOC C34 } [get_ports {fmc_dp_c2m_n[4]}]  ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 from J25.A35 DP4_C2M_N
+set_property -dict {LOC D36 } [get_ports {fmc_dp_m2c_p[4]}]  ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 from J25.A14 DP4_M2C_P
+set_property -dict {LOC D37 } [get_ports {fmc_dp_m2c_n[4]}]  ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 from J25.A15 DP4_M2C_N
+set_property -dict {LOC A33 } [get_ports {fmc_dp_c2m_p[5]}]  ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 from J25.A38 DP5_C2M_P
+set_property -dict {LOC A34 } [get_ports {fmc_dp_c2m_n[5]}]  ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 from J25.A39 DP5_C2M_N
+set_property -dict {LOC B36 } [get_ports {fmc_dp_m2c_p[5]}]  ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 from J25.A18 DP5_M2C_P
+set_property -dict {LOC B37 } [get_ports {fmc_dp_m2c_n[5]}]  ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 from J25.A19 DP5_M2C_N
+set_property -dict {LOC B31 } [get_ports {fmc_dp_c2m_p[6]}]  ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 from J25.B36 DP6_C2M_P
+set_property -dict {LOC B32 } [get_ports {fmc_dp_c2m_n[6]}]  ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 from J25.B37 DP6_C2M_N
+set_property -dict {LOC C38 } [get_ports {fmc_dp_m2c_p[6]}]  ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 from J25.B16 DP6_M2C_P
+set_property -dict {LOC C39 } [get_ports {fmc_dp_m2c_n[6]}]  ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 from J25.B17 DP6_M2C_N
+set_property -dict {LOC D31 } [get_ports {fmc_dp_c2m_p[7]}]  ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 from J25.B32 DP7_C2M_P
+set_property -dict {LOC D32 } [get_ports {fmc_dp_c2m_n[7]}]  ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 from J25.B33 DP7_C2M_N
+set_property -dict {LOC E38 } [get_ports {fmc_dp_m2c_p[7]}]  ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 from J25.B12 DP7_M2C_P
+set_property -dict {LOC E39 } [get_ports {fmc_dp_m2c_n[7]}]  ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 from J25.B13 DP7_M2C_N
+set_property -dict {LOC P31 } [get_ports fmc_mgt_refclk_1_0_p] ;# MGTREFCLK0P_131 from U48.45 OUT6_P
+set_property -dict {LOC P32 } [get_ports fmc_mgt_refclk_1_0_n] ;# MGTREFCLK0N_131 from U48.44 OUT6_N
+#set_property -dict {LOC M31 } [get_ports fmc_mgt_refclk_1_1_p] ;# MGTREFCLK1P_131 from J25.B20 GBTCLK1_M2C_P
+#set_property -dict {LOC M32 } [get_ports fmc_mgt_refclk_1_1_n] ;# MGTREFCLK1N_131 from J25.B21 GBTCLK1_M2C_N
+
+# reference clock
+create_clock -period 6.206 -name fmc_mgt_refclk_1_0 [get_ports fmc_mgt_refclk_1_0_p]
+#create_clock -period 6.400 -name fmc_mgt_refclk_1_1 [get_ports fmc_mgt_refclk_1_1_p]
+
+# RFDC
+set_property -dict {LOC Y2  } [get_ports {adc_vin_p[0]}]  ;# ADC_VIN_I23_227_P from J9 via T5
+set_property -dict {LOC Y1  } [get_ports {adc_vin_n[0]}]  ;# ADC_VIN_I23_227_N from J9 via T5
+set_property -dict {LOC AB2 } [get_ports {adc_vin_p[1]}]  ;# ADC_VIN_I01_227_P from J10 via T13
+set_property -dict {LOC AB1 } [get_ports {adc_vin_n[1]}]  ;# ADC_VIN_I01_227_N from J10 via T13
+set_property -dict {LOC AD2 } [get_ports {adc_vin_p[2]}]  ;# ADC_VIN_I23_226_P from J11 via T6
+set_property -dict {LOC AD1 } [get_ports {adc_vin_n[2]}]  ;# ADC_VIN_I23_226_N from J11 via T6
+set_property -dict {LOC AF2 } [get_ports {adc_vin_p[3]}]  ;# ADC_VIN_I01_226_P from J12 via T14
+set_property -dict {LOC AF1 } [get_ports {adc_vin_n[3]}]  ;# ADC_VIN_I01_226_N from J12 via T14
+set_property -dict {LOC AH2 } [get_ports {adc_vin_p[4]}]  ;# ADC_VIN_I23_225_P from J13 via T7
+set_property -dict {LOC AH1 } [get_ports {adc_vin_n[4]}]  ;# ADC_VIN_I23_225_N from J13 via T7
+set_property -dict {LOC AK2 } [get_ports {adc_vin_p[5]}]  ;# ADC_VIN_I01_225_P from J14 via T15
+set_property -dict {LOC AK1 } [get_ports {adc_vin_n[5]}]  ;# ADC_VIN_I01_225_N from J14 via T15
+set_property -dict {LOC AM2 } [get_ports {adc_vin_p[6]}]  ;# ADC_VIN_I23_224_P from J15 via T8
+set_property -dict {LOC AM1 } [get_ports {adc_vin_n[6]}]  ;# ADC_VIN_I23_224_N from J15 via T8
+set_property -dict {LOC AP2 } [get_ports {adc_vin_p[7]}]  ;# ADC_VIN_I01_224_P from J16 via T16
+set_property -dict {LOC AP1 } [get_ports {adc_vin_n[7]}]  ;# ADC_VIN_I01_224_N from J16 via T16
+
+set_property -dict {LOC AF5 } [get_ports {adc_refclk_0_p}]  ;# ADC_224_REFCLK_P from U67.23 RFoutAP
+set_property -dict {LOC AF4 } [get_ports {adc_refclk_0_n}]  ;# ADC_224_REFCLK_N from U67.22 RFoutAN
+set_property -dict {LOC AD5 } [get_ports {adc_refclk_1_p}]  ;# ADC_225_REFCLK_P from U67.19 RFoutBP
+set_property -dict {LOC AD4 } [get_ports {adc_refclk_1_n}]  ;# ADC_225_REFCLK_N from U67.18 RFoutBN
+set_property -dict {LOC AB5 } [get_ports {adc_refclk_2_p}]  ;# ADC_226_REFCLK_P from U66.23 RFoutAP
+set_property -dict {LOC AB4 } [get_ports {adc_refclk_2_n}]  ;# ADC_226_REFCLK_N from U66.22 RFoutAN
+set_property -dict {LOC Y5  } [get_ports {adc_refclk_3_p}]  ;# ADC_227_REFCLK_P from U66.19 RFoutBP
+set_property -dict {LOC Y4  } [get_ports {adc_refclk_3_n}]  ;# ADC_227_REFCLK_N from U66.18 RFoutBN
+
+set_property -dict {LOC C2  } [get_ports {dac_vout_p[0]}]  ;# DAC_VOUT3_229_P from J1 via T1
+set_property -dict {LOC C1  } [get_ports {dac_vout_n[0]}]  ;# DAC_VOUT3_229_N from J1 via T1
+set_property -dict {LOC E2  } [get_ports {dac_vout_p[1]}]  ;# DAC_VOUT2_229_P from J2 via T9
+set_property -dict {LOC E1  } [get_ports {dac_vout_n[1]}]  ;# DAC_VOUT2_229_N from J2 via T9
+set_property -dict {LOC G2  } [get_ports {dac_vout_p[2]}]  ;# DAC_VOUT1_229_P from J3 via T2
+set_property -dict {LOC G1  } [get_ports {dac_vout_n[2]}]  ;# DAC_VOUT1_229_N from J3 via T2
+set_property -dict {LOC J2  } [get_ports {dac_vout_p[3]}]  ;# DAC_VOUT0_229_P from J4 via T10
+set_property -dict {LOC J1  } [get_ports {dac_vout_n[3]}]  ;# DAC_VOUT0_229_N from J4 via T10
+set_property -dict {LOC L2  } [get_ports {dac_vout_p[4]}]  ;# DAC_VOUT3_228_P from J5 via T3
+set_property -dict {LOC L1  } [get_ports {dac_vout_n[4]}]  ;# DAC_VOUT3_228_N from J5 via T3
+set_property -dict {LOC N2  } [get_ports {dac_vout_p[5]}]  ;# DAC_VOUT2_228_P from J6 via T11
+set_property -dict {LOC N1  } [get_ports {dac_vout_n[5]}]  ;# DAC_VOUT2_228_N from J6 via T11
+set_property -dict {LOC R2  } [get_ports {dac_vout_p[6]}]  ;# DAC_VOUT1_228_P from J7 via T4
+set_property -dict {LOC R1  } [get_ports {dac_vout_n[6]}]  ;# DAC_VOUT1_228_N from J7 via T4
+set_property -dict {LOC U2  } [get_ports {dac_vout_p[7]}]  ;# DAC_VOUT0_228_P from J8 via T12
+set_property -dict {LOC U1  } [get_ports {dac_vout_n[7]}]  ;# DAC_VOUT0_228_N from J8 via T12
+
+#set_property -dict {LOC R5  } [get_ports {dac_refclk_0_p}]  ;# DAC_228_REFCLK_P from U65.23 RFoutAP
+#set_property -dict {LOC R4  } [get_ports {dac_refclk_0_n}]  ;# DAC_228_REFCLK_N from U65.22 RFoutAN
+set_property -dict {LOC N5  } [get_ports {dac_refclk_1_p}]  ;# DAC_229_REFCLK_P from U65.19 RFoutBP
+set_property -dict {LOC N4  } [get_ports {dac_refclk_1_n}]  ;# DAC_229_REFCLK_N from U65.18 RFoutBN
+
+set_property -dict {LOC U5  } [get_ports {rfdc_sysref_p}]  ;# SYSREF_P_228 from U2.1 CLKout0_P
+set_property -dict {LOC U4  } [get_ports {rfdc_sysref_n}]  ;# SYSREF_N_228 from U2.2 CLKout0_N

src/eth/example/HTG_ZRF8/fpga/fpga_r2.xdc

@@ -0,0 +1,527 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the HiTech Global HTG-ZRF8-R2 board
+# part: xczu28dr-ffvg1517-2-e
+# part: xczu48dr-ffvg1517-2-e
+
+# General configuration
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+
+# System clocks
+# DDR4 clocks from U48 (300 MHz)
+#set_property -dict {LOC G13  IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_p] ;# U48.28 OUT1_P
+#set_property -dict {LOC G12  IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_n] ;# U48.27 OUT1_N
+#create_clock -period 3.333 -name sys_clk_ddr4 [get_ports sys_clk_ddr4_p]
+
+# User clock 1 from U48 (200 MHz)
+set_property -dict {LOC C8   IOSTANDARD LVDS_25} [get_ports clk_pl_user1_p] ;# U48.24 OUT0_P
+set_property -dict {LOC C7   IOSTANDARD LVDS_25} [get_ports clk_pl_user1_n] ;# U48.23 OUT0_N
+create_clock -period 5.000 -name clk_pl_user1 [get_ports clk_pl_user1_p]
+
+# Source pin is in an HDIO bank, so it must be routed to an MMCM via a BUFG
+set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets clk_pl_user1_bufg]
+
+# User clock 2 from U48 (200 MHz)
+#set_property -dict {LOC AM15 IOSTANDARD LVDS} [get_ports clk_pl_user2_p] ;# U48.42 OUT5_P
+#set_property -dict {LOC AN15 IOSTANDARD LVDS} [get_ports clk_pl_user2_n] ;# U48.41 OUT5_N
+#create_clock -period 5.000 -name clk_pl_user2 [get_ports clk_pl_user2_p]
+
+# PLL refclk from U78 (250 MHz)
+set_property -dict {LOC AV6  IOSTANDARD LVDS_25} [get_ports fpga_refclk_p] ;# U78.51 CLKout8_P
+set_property -dict {LOC AV5  IOSTANDARD LVDS_25} [get_ports fpga_refclk_n] ;# U78.52 CLKout8_N
+create_clock -period 4.000 -name fpga_refclk [get_ports fpga_refclk_p]
+
+# Source pin is in an HDIO bank, so it must be routed to an MMCM via a BUFG
+set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets fpga_refclk_int fpga_refclk_bufg_inst_n_0]
+
+# PLL sysref from U78
+set_property -dict {LOC AP20 IOSTANDARD LVDS} [get_ports fpga_sysref_p] ;# U78.22 CLKout5_P
+set_property -dict {LOC AP19 IOSTANDARD LVDS} [get_ports fpga_sysref_n] ;# U78.23 CLKout5_N
+create_clock -period 100.000 -name fpga_sysref [get_ports fpga_sysref_p]
+
+# PLL control
+set_property -dict {LOC AU4  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {clk_fdec}]
+set_property -dict {LOC AV2  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {clk_finc}]
+set_property -dict {LOC AU1  IOSTANDARD LVCMOS33} [get_ports {clk_intr_n}]
+set_property -dict {LOC AV3  IOSTANDARD LVCMOS33} [get_ports {clk_lol_n}]
+set_property -dict {LOC AU3  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {clk_sync_n}]
+set_property -dict {LOC AU2  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {clk_rst_n}]
+
+set_property -dict {LOC AW6  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {lmk_rst}]
+set_property -dict {LOC AW4  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {lmk_clkin_s[0]}]
+set_property -dict {LOC AW3  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {lmk_clkin_s[1]}]
+
+set_false_path -to [get_ports {clk_fdec clk_finc clk_sync_n clk_rst_n}]
+set_output_delay 0 [get_ports {clk_fdec clk_finc clk_sync_n clk_rst_n}]
+set_false_path -from [get_ports {clk_intr_n clk_lol_n}]
+set_input_delay 0 [get_ports {clk_intr_n clk_lol_n}]
+
+set_false_path -to [get_ports {lmk_rst}]
+set_output_delay 0 [get_ports {lmk_rst}]
+
+# LEDs
+set_property -dict {LOC A6   IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[0]}] ;# D10
+set_property -dict {LOC C6   IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[1]}] ;# D9
+set_property -dict {LOC D6   IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[2]}] ;# D8
+set_property -dict {LOC E6   IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[3]}] ;# D7
+
+set_false_path -to [get_ports {led[*]}]
+set_output_delay 0 [get_ports {led[*]}]
+
+# Push buttons
+set_property -dict {LOC AT5  IOSTANDARD LVCMOS33} [get_ports {btn}] ;# PB3
+
+set_false_path -from [get_ports {btn}]
+set_input_delay 0 [get_ports {btn}]
+
+# DIP switches
+set_property -dict {LOC D20  IOSTANDARD LVCMOS12} [get_ports {sw[0]}] ;# S1.1
+set_property -dict {LOC A25  IOSTANDARD LVCMOS12} [get_ports {sw[1]}] ;# S1.2
+set_property -dict {LOC B23  IOSTANDARD LVCMOS12} [get_ports {sw[2]}] ;# S1.3
+set_property -dict {LOC D19  IOSTANDARD LVCMOS12} [get_ports {sw[3]}] ;# S1.4
+
+set_false_path -from [get_ports {sw[*]}]
+set_input_delay 0 [get_ports {sw[*]}]
+
+# Trace
+#set_property -dict {LOC AR16 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[0]}]  ;# J22.38
+#set_property -dict {LOC AN17 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[1]}]  ;# J22.28
+#set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[2]}]  ;# J22.26
+#set_property -dict {LOC AF16 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[3]}]  ;# J22.24
+#set_property -dict {LOC AP14 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[4]}]  ;# J22.22
+#set_property -dict {LOC AR14 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[5]}]  ;# J22.20
+#set_property -dict {LOC AT13 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[6]}]  ;# J22.18
+#set_property -dict {LOC AT15 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[7]}]  ;# J22.16
+#set_property -dict {LOC AN16 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[8]}]  ;# J22.37
+#set_property -dict {LOC AK17 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[9]}]  ;# J22.35
+#set_property -dict {LOC AR13 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[10]}] ;# J22.33
+#set_property -dict {LOC AU13 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[11]}] ;# J22.31
+#set_property -dict {LOC AK16 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[12]}] ;# J22.29
+#set_property -dict {LOC AL15 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[13]}] ;# J22.27
+#set_property -dict {LOC AH14 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[14]}] ;# J22.25
+#set_property -dict {LOC AJ16 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_data[15]}] ;# J22.23
+#set_property -dict {LOC AL16 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_clk}]      ;# J22.6
+#set_property -dict {LOC AT16 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_tdi}]      ;# J22.19
+#set_property -dict {LOC AH16 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_tdo}]      ;# J22.11
+#set_property -dict {LOC AF17 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_tms}]      ;# J22.17
+#set_property -dict {LOC AG17 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_tck}]      ;# J22.15
+#set_property -dict {LOC AL17 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_rtck}]     ;# J22.13
+#set_property -dict {LOC AJ15 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_dbgrq}]    ;# J22.7
+#set_property -dict {LOC AU14 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_dbgack}]   ;# J22.8
+#set_property -dict {LOC AP15 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_trst_b}]   ;# J22.21
+#set_property -dict {LOC AH15 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_srst_b}]   ;# J22.9
+#set_property -dict {LOC AP16 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_ctl}]      ;# J22.36
+#set_property -dict {LOC AU15 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {trace_exttrig}]  ;# J22.10
+
+#set_false_path -to [get_ports {trace_data trace_clk trace_tdi trace_tdo trace_tms trace_tck trace_rtck trace_dbgrq trace_dbgack trace_rst_b trace_ctl trace_exttrig[*]}]
+#set_output_delay 0 [get_ports {trace_data trace_clk trace_tdi trace_tdo trace_tms trace_tck trace_rtck trace_dbgrq trace_dbgack trace_rst_b trace_ctl trace_exttrig[*]}]
+
+# UART
+set_property -dict {LOC AU8  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_rxd]
+set_property -dict {LOC AV8  IOSTANDARD LVCMOS33} [get_ports uart_txd]
+set_property -dict {LOC AV7  IOSTANDARD LVCMOS33} [get_ports uart_rts]
+set_property -dict {LOC AU7  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_cts]
+set_property -dict {LOC AT7  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_rst_n]
+set_property -dict {LOC AR7  IOSTANDARD LVCMOS33} [get_ports uart_suspend_n]
+
+set_false_path -to [get_ports {uart_rxd uart_cts uart_rst_n}]
+set_output_delay 0 [get_ports {uart_rxd uart_cts uart_rst_n}]
+set_false_path -from [get_ports {uart_txd uart_rts uart_suspend_n}]
+set_input_delay 0 [get_ports {uart_txd uart_rts uart_suspend_n}]
+
+# I2C
+set_property -dict {LOC E9   IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
+set_property -dict {LOC E8   IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
+set_property -dict {LOC D10  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c_rst_n]
+
+set_false_path -to [get_ports {i2c_sda i2c_scl i2c_rst_n}]
+set_output_delay 0 [get_ports {i2c_sda i2c_scl i2c_rst_n}]
+set_false_path -from [get_ports {i2c_sda i2c_scl}]
+set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
+
+# DDR4 SODIMM
+#set_property -dict {LOC F11  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[0]}]
+#set_property -dict {LOC C13  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[1]}]
+#set_property -dict {LOC F14  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[2]}]
+#set_property -dict {LOC F10  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[3]}]
+#set_property -dict {LOC E11  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[4]}]
+#set_property -dict {LOC E13  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[5]}]
+#set_property -dict {LOC B13  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[6]}]
+#set_property -dict {LOC E12  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[7]}]
+#set_property -dict {LOC A11  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[8]}]
+#set_property -dict {LOC C12  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[9]}]
+#set_property -dict {LOC K13  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[10]}]
+#set_property -dict {LOC C15  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[11]}]
+#set_property -dict {LOC C11  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[12]}]
+#set_property -dict {LOC K10  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[13]}]
+#set_property -dict {LOC B14  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[14]}]
+#set_property -dict {LOC H12  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[15]}]
+#set_property -dict {LOC K12  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a[16]}]
+
+#set_property -dict {LOC B15  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_act_n}]
+#set_property -dict {LOC D14  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_alert_n}]
+
+#set_property -dict {LOC H13  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_ba[0]}]
+#set_property -dict {LOC A14  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_ba[1]}]
+#set_property -dict {LOC B12  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_bg[0]}]
+#set_property -dict {LOC D11  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_bg[1]}]
+
+#set_property -dict {LOC A12  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_cke[0]}]
+#set_property -dict {LOC A15  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_cke[1]}]
+#set_property -dict {LOC J11  IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_ck_t[0]}]
+#set_property -dict {LOC J10  IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_ck_c[0]}]
+#set_property -dict {LOC J14  IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_ck_t[1]}]
+#set_property -dict {LOC J13  IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_ck_c[1]}]
+#set_property -dict {LOC H10  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_cs_n[0]}]
+#set_property -dict {LOC E14  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_cs_n[1]}]
+#set_property -dict {LOC K11  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_cs_n[2]}]
+#set_property -dict {LOC F12  IOSTANDARD SSTL12_DCI} [get_ports {ddr4_cs_n[3]}]
+
+#set_property -dict {LOC M12  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[0]}]
+#set_property -dict {LOC M13  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[1]}]
+#set_property -dict {LOC N15  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[2]}]
+#set_property -dict {LOC M17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[3]}]
+#set_property -dict {LOC L12  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[4]}]
+#set_property -dict {LOC N13  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[5]}]
+#set_property -dict {LOC M15  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[6]}]
+#set_property -dict {LOC N17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[7]}]
+#set_property -dict {LOC K17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[8]}]
+#set_property -dict {LOC L17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[9]}]
+#set_property -dict {LOC J19  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[10]}]
+#set_property -dict {LOC H16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[11]}]
+#set_property -dict {LOC J16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[12]}]
+#set_property -dict {LOC K16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[13]}]
+#set_property -dict {LOC H17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[14]}]
+#set_property -dict {LOC J18  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[15]}]
+#set_property -dict {LOC E16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[16]}]
+#set_property -dict {LOC F15  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[17]}]
+#set_property -dict {LOC E17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[18]}]
+#set_property -dict {LOC H18  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[19]}]
+#set_property -dict {LOC F16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[20]}]
+#set_property -dict {LOC G15  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[21]}]
+#set_property -dict {LOC E18  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[22]}]
+#set_property -dict {LOC G18  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[23]}]
+#set_property -dict {LOC C16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[24]}]
+#set_property -dict {LOC D15  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[25]}]
+#set_property -dict {LOC C17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[26]}]
+#set_property -dict {LOC A19  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[27]}]
+#set_property -dict {LOC A16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[28]}]
+#set_property -dict {LOC D16  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[29]}]
+#set_property -dict {LOC A17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[30]}]
+#set_property -dict {LOC B19  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[31]}]
+#set_property -dict {LOC H23  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[32]}]
+#set_property -dict {LOC J21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[33]}]
+#set_property -dict {LOC H22  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[34]}]
+#set_property -dict {LOC K24  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[35]}]
+#set_property -dict {LOC G23  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[36]}]
+#set_property -dict {LOC H21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[37]}]
+#set_property -dict {LOC G22  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[38]}]
+#set_property -dict {LOC L24  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[39]}]
+#set_property -dict {LOC E21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[40]}]
+#set_property -dict {LOC F20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[41]}]
+#set_property -dict {LOC E23  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[42]}]
+#set_property -dict {LOC F24  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[43]}]
+#set_property -dict {LOC D21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[44]}]
+#set_property -dict {LOC E22  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[45]}]
+#set_property -dict {LOC E24  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[46]}]
+#set_property -dict {LOC G20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[47]}]
+#set_property -dict {LOC C20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[48]}]
+#set_property -dict {LOC A20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[49]}]
+#set_property -dict {LOC B24  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[50]}]
+#set_property -dict {LOC C21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[51]}]
+#set_property -dict {LOC B20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[52]}]
+#set_property -dict {LOC A21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[53]}]
+#set_property -dict {LOC C22  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[54]}]
+#set_property -dict {LOC A24  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[55]}]
+#set_property -dict {LOC L19  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[56]}]
+#set_property -dict {LOC L21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[57]}]
+#set_property -dict {LOC L23  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[58]}]
+#set_property -dict {LOC N19  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[59]}]
+#set_property -dict {LOC L20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[60]}]
+#set_property -dict {LOC M19  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[61]}]
+#set_property -dict {LOC L22  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[62]}]
+#set_property -dict {LOC M20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[63]}]
+#set_property -dict {LOC F9   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[64]}]
+#set_property -dict {LOC G7   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[65]}]
+#set_property -dict {LOC H6   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[66]}]
+#set_property -dict {LOC G6   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[67]}]
+#set_property -dict {LOC G9   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[68]}]
+#set_property -dict {LOC H7   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[69]}]
+#set_property -dict {LOC K9   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[70]}]
+#set_property -dict {LOC J9   IOSTANDARD POD12_DCI} [get_ports {ddr4_dq[71]}]
+
+#set_property -dict {LOC L15  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[0]}]
+#set_property -dict {LOC L14  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[0]}]
+#set_property -dict {LOC K19  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[1]}]
+#set_property -dict {LOC K18  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[1]}]
+#set_property -dict {LOC G19  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[2]}]
+#set_property -dict {LOC F19  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[2]}]
+#set_property -dict {LOC B18  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[3]}]
+#set_property -dict {LOC B17  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[3]}]
+#set_property -dict {LOC J20  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[4]}]
+#set_property -dict {LOC H20  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[4]}]
+#set_property -dict {LOC D23  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[5]}]
+#set_property -dict {LOC D24  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[5]}]
+#set_property -dict {LOC B22  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[6]}]
+#set_property -dict {LOC A22  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[6]}]
+#set_property -dict {LOC K21  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[7]}]
+#set_property -dict {LOC K22  IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[7]}]
+#set_property -dict {LOC H8   IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_t[8]}]
+#set_property -dict {LOC G8   IOSTANDARD DIFF_POD12} [get_ports {ddr4_dqs_c[8]}]
+
+#set_property -dict {LOC N14  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[0]}]
+#set_property -dict {LOC J15  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[1]}]
+#set_property -dict {LOC G17  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[2]}]
+#set_property -dict {LOC D18  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[3]}]
+#set_property -dict {LOC J23  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[4]}]
+#set_property -dict {LOC F21  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[5]}]
+#set_property -dict {LOC C23  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[6]}]
+#set_property -dict {LOC N20  IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[7]}]
+#set_property -dict {LOC J8   IOSTANDARD POD12_DCI} [get_ports {ddr4_dm_dbi_n[8]}]
+
+#set_property -dict {LOC J7   IOSTANDARD LVCMOS12} [get_ports {ddr4_odt[0]}]
+#set_property -dict {LOC H11  IOSTANDARD LVCMOS12} [get_ports {ddr4_odt[1]}]
+#set_property -dict {LOC D13  IOSTANDARD LVCMOS12} [get_ports {ddr4_rst_n}]
+#set_property -dict {LOC G10  IOSTANDARD LVCMOS12} [get_ports {ddr4_par}]
+#set_property -dict {LOC G14  IOSTANDARD LVCMOS12} [get_ports {ddr4_event_n}]
+
+# PCIe Interface
+#set_property -dict {LOC J33 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_129 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC J34 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_129 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC K36 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_129 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC K37 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_129 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC L33 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_129 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC L34 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_129 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC L38 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_129 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC L39 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_129 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC N33 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_129 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC N34 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_129 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC M36 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_129 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC M37 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_129 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC P35 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_129 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC P36 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_129 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC N38 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_129 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC N39 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_129 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+#set_property -dict {LOC R33 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC R34 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC R38 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC R39 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC T35 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC T36 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC U38 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC U39 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC V35 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC V36 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC W38 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC W39 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC Y35 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC Y36 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC AA38} [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC AA39} [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+#set_property -dict {LOC AA33} [get_ports pcie_refclk_p] ;# MGTREFCLK0P_128
+#set_property -dict {LOC AA34} [get_ports pcie_refclk_n] ;# MGTREFCLK0N_128
+#set_property -dict {LOC AJ13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
+
+#set_false_path -from [get_ports {pcie_reset_n}]
+#set_input_delay 0 [get_ports {pcie_reset_n}]
+
+# 100 MHz MGT reference clock
+#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p]
+
+# FMC+ J25
+
+# for HTG-FMC-QSFP28-DEG90
+set_property -dict {LOC AJ12 IOSTANDARD LVCMOS18} [get_ports {fmc_qsfp_resetl}] ;# J25.G33 LA31_P
+set_property -dict {LOC AK12 IOSTANDARD LVCMOS18} [get_ports {fmc_qsfp_modsell}] ;# J25.G34 LA31_N
+set_property -dict {LOC AL7  IOSTANDARD LVCMOS18} [get_ports {fmc_qsfp_lpmode}] ;# J25.H38 LA32_N
+
+#set_property -dict {LOC AP18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[0]}]  ;# J25.G9  LA00_P_CC
+#set_property -dict {LOC AR18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[0]}]  ;# J25.G10 LA00_N_CC
+#set_property -dict {LOC AM20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[1]}]  ;# J25.D8  LA01_P_CC
+#set_property -dict {LOC AN20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[1]}]  ;# J25.D9  LA01_N_CC
+#set_property -dict {LOC AR22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[2]}]  ;# J25.H7  LA02_P
+#set_property -dict {LOC AT22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[2]}]  ;# J25.H8  LA02_N
+#set_property -dict {LOC AR21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[3]}]  ;# J25.G12 LA03_P
+#set_property -dict {LOC AT21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[3]}]  ;# J25.G13 LA03_N
+#set_property -dict {LOC AV21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[4]}]  ;# J25.H10 LA04_P
+#set_property -dict {LOC AW21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[4]}]  ;# J25.H11 LA04_N
+#set_property -dict {LOC AK22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[5]}]  ;# J25.D11 LA05_P
+#set_property -dict {LOC AK21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[5]}]  ;# J25.D12 LA05_N
+#set_property -dict {LOC AU18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[6]}]  ;# J25.C10 LA06_P
+#set_property -dict {LOC AV18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[6]}]  ;# J25.C11 LA06_N
+#set_property -dict {LOC AL21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[7]}]  ;# J25.H13 LA07_P
+#set_property -dict {LOC AL20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[7]}]  ;# J25.H14 LA07_N
+#set_property -dict {LOC AL22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[8]}]  ;# J25.G12 LA08_P
+#set_property -dict {LOC AM22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[8]}]  ;# J25.G13 LA08_N
+#set_property -dict {LOC AR19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[9]}]  ;# J25.D14 LA09_P
+#set_property -dict {LOC AT19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[9]}]  ;# J25.D15 LA09_N
+#set_property -dict {LOC AU17 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[10]}] ;# J25.C14 LA10_P
+#set_property -dict {LOC AV17 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[10]}] ;# J25.C15 LA10_N
+#set_property -dict {LOC AL19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[11]}] ;# J25.H16 LA11_P
+#set_property -dict {LOC AM19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[11]}] ;# J25.H17 LA11_N
+#set_property -dict {LOC AG20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[12]}] ;# J25.G15 LA12_P
+#set_property -dict {LOC AH20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[12]}] ;# J25.G16 LA12_N
+#set_property -dict {LOC AJ20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[13]}] ;# J25.D17 LA13_P
+#set_property -dict {LOC AJ19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[13]}] ;# J25.D18 LA13_N
+#set_property -dict {LOC AJ18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[14]}] ;# J25.C18 LA14_P
+#set_property -dict {LOC AK18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[14]}] ;# J25.C19 LA14_N
+#set_property -dict {LOC AR17 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[15]}] ;# J25.H19 LA15_P
+#set_property -dict {LOC AT17 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[15]}] ;# J25.H20 LA15_N
+#set_property -dict {LOC AG18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[16]}] ;# J25.G18 LA16_P
+#set_property -dict {LOC AH18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[16]}] ;# J25.G19 LA16_N
+#set_property -dict {LOC AP8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[17]}] ;# J25.D20 LA17_P_CC
+#set_property -dict {LOC AR8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[17]}] ;# J25.D21 LA17_N_CC
+#set_property -dict {LOC AP9  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[18]}] ;# J25.C22 LA18_P_CC
+#set_property -dict {LOC AR9  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[18]}] ;# J25.C23 LA18_N_CC
+#set_property -dict {LOC AU12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[19]}] ;# J25.H22 LA19_P
+#set_property -dict {LOC AV12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[19]}] ;# J25.H23 LA19_N
+#set_property -dict {LOC AW9  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[20]}] ;# J25.G21 LA20_P
+#set_property -dict {LOC AW8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[20]}] ;# J25.G22 LA20_N
+#set_property -dict {LOC AM13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[21]}] ;# J25.H25 LA21_P
+#set_property -dict {LOC AN13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[21]}] ;# J25.H26 LA21_N
+#set_property -dict {LOC AT10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[22]}] ;# J25.G24 LA22_P
+#set_property -dict {LOC AU10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[22]}] ;# J25.G25 LA22_N
+#set_property -dict {LOC AV11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[23]}] ;# J25.D23 LA23_P
+#set_property -dict {LOC AW11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[23]}] ;# J25.D24 LA23_N
+#set_property -dict {LOC AN8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[24]}] ;# J25.H28 LA24_P
+#set_property -dict {LOC AN7  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[24]}] ;# J25.H29 LA24_N
+#set_property -dict {LOC AL14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[25]}] ;# J25.G27 LA25_P
+#set_property -dict {LOC AM14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[25]}] ;# J25.G28 LA25_N
+#set_property -dict {LOC AM12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[26]}] ;# J25.D26 LA26_P
+#set_property -dict {LOC AN12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[26]}] ;# J25.D27 LA26_N
+#set_property -dict {LOC AR12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[27]}] ;# J25.C26 LA27_P
+#set_property -dict {LOC AR11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[27]}] ;# J25.C27 LA27_N
+#set_property -dict {LOC AL10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[28]}] ;# J25.H31 LA28_P
+#set_property -dict {LOC AM10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[28]}] ;# J25.H32 LA28_N
+#set_property -dict {LOC AJ14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[29]}] ;# J25.G30 LA29_P
+#set_property -dict {LOC AK14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[29]}] ;# J25.G31 LA29_N
+#set_property -dict {LOC AG12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[30]}] ;# J25.H34 LA30_P
+#set_property -dict {LOC AH12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[30]}] ;# J25.H35 LA30_N
+#set_property -dict {LOC AJ12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[31]}] ;# J25.G33 LA31_P
+#set_property -dict {LOC AK12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[31]}] ;# J25.G34 LA31_N
+#set_property -dict {LOC AL8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[32]}] ;# J25.H37 LA32_P
+#set_property -dict {LOC AL7  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[32]}] ;# J25.H38 LA32_N
+#set_property -dict {LOC AL9  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[33]}] ;# J25.G36 LA33_P
+#set_property -dict {LOC AM9  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[33]}] ;# J25.G37 LA33_N
+
+#set_property -dict {LOC AN21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_clk0_m2c_p}] ;# J25.H4 CLK0_M2C_P
+#set_property -dict {LOC AP21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_clk0_m2c_n}] ;# J25.H5 CLK0_M2C_N
+
+#set_property -dict {LOC AN11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_refclk_m2c_p}] ;# J25.L24 REFCLK_M2C_P
+#set_property -dict {LOC AP11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_refclk_m2c_n}] ;# J25.L25 REFCLK_M2C_N
+#set_property -dict {LOC AV10 IOSTANDARD LVDS                       } [get_ports {fmc_sync_c2m_p}]   ;# J25.L16 SYNC_C2M_P
+#set_property -dict {LOC AW10 IOSTANDARD LVDS                       } [get_ports {fmc_sync_c2m_n}]   ;# J25.L17 SYNC_C2M_N
+#set_property -dict {LOC AN10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_sync_m2c_p}]   ;# J25.L28 SYNC_M2C_P
+#set_property -dict {LOC AP10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_sync_m2c_n}]   ;# J25.L29 SYNC_M2C_N
+
+#set_property -dict {LOC A10  IOSTANDARD LVCMOS18} [get_ports {fmc_pg_m2c}]           ;# J25.F1 PG_M2C
+#set_property -dict {LOC C10  IOSTANDARD LVCMOS12} [get_ports {fmc_prsnt_m2c_l}]      ;# J25.H2 PRSNT_M2C_L
+#set_property -dict {LOC B10  IOSTANDARD LVCMOS12} [get_ports {fmc_hspc_prsnt_m2c_l}] ;# J25.Z1 HSPC_PRSNT_M2C_L
+
+set_property -dict {LOC E33 } [get_ports {fmc_dp_c2m_p[0]}]  ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 from J25.C2  DP0_C2M_P
+set_property -dict {LOC E34 } [get_ports {fmc_dp_c2m_n[0]}]  ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 from J25.C3  DP0_C2M_N
+set_property -dict {LOC F36 } [get_ports {fmc_dp_m2c_p[0]}]  ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 from J25.C6  DP0_M2C_P
+set_property -dict {LOC F37 } [get_ports {fmc_dp_m2c_n[0]}]  ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 from J25.C7  DP0_M2C_N
+set_property -dict {LOC H31 } [get_ports {fmc_dp_c2m_p[1]}]  ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 from J25.A22 DP1_C2M_P
+set_property -dict {LOC H32 } [get_ports {fmc_dp_c2m_n[1]}]  ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 from J25.A23 DP1_C2M_N
+set_property -dict {LOC J38 } [get_ports {fmc_dp_m2c_p[1]}]  ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 from J25.A2  DP1_M2C_P
+set_property -dict {LOC J39 } [get_ports {fmc_dp_m2c_n[1]}]  ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 from J25.A3  DP1_M2C_N
+set_property -dict {LOC G33 } [get_ports {fmc_dp_c2m_p[2]}]  ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 from J25.A26 DP2_C2M_P
+set_property -dict {LOC G34 } [get_ports {fmc_dp_c2m_n[2]}]  ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 from J25.A27 DP2_C2M_N
+set_property -dict {LOC H36 } [get_ports {fmc_dp_m2c_p[2]}]  ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 from J25.A6  DP2_M2C_P
+set_property -dict {LOC H37 } [get_ports {fmc_dp_m2c_n[2]}]  ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 from J25.A7  DP2_M2C_N
+set_property -dict {LOC F31 } [get_ports {fmc_dp_c2m_p[3]}]  ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 from J25.A30 DP3_C2M_P
+set_property -dict {LOC F32 } [get_ports {fmc_dp_c2m_n[3]}]  ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 from J25.A31 DP3_C2M_N
+set_property -dict {LOC G38 } [get_ports {fmc_dp_m2c_p[3]}]  ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 from J25.A10 DP3_M2C_P
+set_property -dict {LOC G39 } [get_ports {fmc_dp_m2c_n[3]}]  ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 from J25.A11 DP3_M2C_N
+set_property -dict {LOC U33 } [get_ports fmc_mgt_refclk_0_0_p] ;# MGTREFCLK0P_130 from U48.38 OUT4_P
+set_property -dict {LOC U34 } [get_ports fmc_mgt_refclk_0_0_n] ;# MGTREFCLK0N_130 from U48.37 OUT4_N
+#set_property -dict {LOC T31 } [get_ports fmc_mgt_refclk_0_1_p] ;# MGTREFCLK1P_130 from J25.D4 GBTCLK0_M2C_P
+#set_property -dict {LOC T32 } [get_ports fmc_mgt_refclk_0_1_n] ;# MGTREFCLK1N_130 from J25.D5 GBTCLK0_M2C_N
+
+# reference clock
+create_clock -period 6.206 -name fmc_mgt_refclk_0_0 [get_ports fmc_mgt_refclk_0_0_p]
+#create_clock -period 6.400 -name fmc_mgt_refclk_0_1 [get_ports fmc_mgt_refclk_0_1_p]
+
+set_property -dict {LOC C33 } [get_ports {fmc_dp_c2m_p[4]}]  ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 from J25.A34 DP4_C2M_P
+set_property -dict {LOC C34 } [get_ports {fmc_dp_c2m_n[4]}]  ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 from J25.A35 DP4_C2M_N
+set_property -dict {LOC D36 } [get_ports {fmc_dp_m2c_p[4]}]  ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 from J25.A14 DP4_M2C_P
+set_property -dict {LOC D37 } [get_ports {fmc_dp_m2c_n[4]}]  ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 from J25.A15 DP4_M2C_N
+set_property -dict {LOC A33 } [get_ports {fmc_dp_c2m_p[5]}]  ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 from J25.A38 DP5_C2M_P
+set_property -dict {LOC A34 } [get_ports {fmc_dp_c2m_n[5]}]  ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 from J25.A39 DP5_C2M_N
+set_property -dict {LOC B36 } [get_ports {fmc_dp_m2c_p[5]}]  ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 from J25.A18 DP5_M2C_P
+set_property -dict {LOC B37 } [get_ports {fmc_dp_m2c_n[5]}]  ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 from J25.A19 DP5_M2C_N
+set_property -dict {LOC B31 } [get_ports {fmc_dp_c2m_p[6]}]  ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 from J25.B36 DP6_C2M_P
+set_property -dict {LOC B32 } [get_ports {fmc_dp_c2m_n[6]}]  ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 from J25.B37 DP6_C2M_N
+set_property -dict {LOC C38 } [get_ports {fmc_dp_m2c_p[6]}]  ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 from J25.B16 DP6_M2C_P
+set_property -dict {LOC C39 } [get_ports {fmc_dp_m2c_n[6]}]  ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 from J25.B17 DP6_M2C_N
+set_property -dict {LOC D31 } [get_ports {fmc_dp_c2m_p[7]}]  ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 from J25.B32 DP7_C2M_P
+set_property -dict {LOC D32 } [get_ports {fmc_dp_c2m_n[7]}]  ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 from J25.B33 DP7_C2M_N
+set_property -dict {LOC E38 } [get_ports {fmc_dp_m2c_p[7]}]  ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 from J25.B12 DP7_M2C_P
+set_property -dict {LOC E39 } [get_ports {fmc_dp_m2c_n[7]}]  ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 from J25.B13 DP7_M2C_N
+set_property -dict {LOC P31 } [get_ports fmc_mgt_refclk_1_0_p] ;# MGTREFCLK0P_131 from U48.35 OUT3_P
+set_property -dict {LOC P32 } [get_ports fmc_mgt_refclk_1_0_n] ;# MGTREFCLK0N_131 from U48.34 OUT3_N
+#set_property -dict {LOC M31 } [get_ports fmc_mgt_refclk_1_1_p] ;# MGTREFCLK1P_131 from J25.B20 GBTCLK1_M2C_P
+#set_property -dict {LOC M32 } [get_ports fmc_mgt_refclk_1_1_n] ;# MGTREFCLK1N_131 from J25.B21 GBTCLK1_M2C_N
+
+# reference clock
+create_clock -period 6.206 -name fmc_mgt_refclk_1_0 [get_ports fmc_mgt_refclk_1_0_p]
+#create_clock -period 6.400 -name fmc_mgt_refclk_1_1 [get_ports fmc_mgt_refclk_1_1_p]
+
+# RFDC
+set_property -dict {LOC Y2  } [get_ports {adc_vin_p[0]}]  ;# ADC_VIN_I23_227_P from J7 (RA) via T5
+set_property -dict {LOC Y1  } [get_ports {adc_vin_n[0]}]  ;# ADC_VIN_I23_227_N from J7 (RA) via T5
+set_property -dict {LOC AB2 } [get_ports {adc_vin_p[1]}]  ;# ADC_VIN_I01_227_P from J17 (V) via T13
+set_property -dict {LOC AB1 } [get_ports {adc_vin_n[1]}]  ;# ADC_VIN_I01_227_N from J17 (V) via T13
+set_property -dict {LOC AD2 } [get_ports {adc_vin_p[2]}]  ;# ADC_VIN_I23_226_P from J8 (RA) via T6
+set_property -dict {LOC AD1 } [get_ports {adc_vin_n[2]}]  ;# ADC_VIN_I23_226_N from J8 (RA) via T6
+set_property -dict {LOC AF2 } [get_ports {adc_vin_p[3]}]  ;# ADC_VIN_I01_226_P from J18 (V) via T14
+set_property -dict {LOC AF1 } [get_ports {adc_vin_n[3]}]  ;# ADC_VIN_I01_226_N from J18 (V) via T14
+set_property -dict {LOC AH2 } [get_ports {adc_vin_p[4]}]  ;# ADC_VIN_I23_225_P from J9 (RA) via T7
+set_property -dict {LOC AH1 } [get_ports {adc_vin_n[4]}]  ;# ADC_VIN_I23_225_N from J9 (RA) via T7
+set_property -dict {LOC AK2 } [get_ports {adc_vin_p[5]}]  ;# ADC_VIN_I01_225_P from J19 (V) via T15
+set_property -dict {LOC AK1 } [get_ports {adc_vin_n[5]}]  ;# ADC_VIN_I01_225_N from J19 (V) via T15
+set_property -dict {LOC AM2 } [get_ports {adc_vin_p[6]}]  ;# ADC_VIN_I23_224_P from J10 (RA) via T8
+set_property -dict {LOC AM1 } [get_ports {adc_vin_n[6]}]  ;# ADC_VIN_I23_224_N from J10 (RA) via T8
+set_property -dict {LOC AP2 } [get_ports {adc_vin_p[7]}]  ;# ADC_VIN_I01_224_P from J20 (V) via T16
+set_property -dict {LOC AP1 } [get_ports {adc_vin_n[7]}]  ;# ADC_VIN_I01_224_N from J20 (V) via T16
+
+set_property -dict {LOC AF5 } [get_ports {adc_refclk_0_p}]  ;# ADC_224_REFCLK_P from U83.23 RFoutAP
+set_property -dict {LOC AF4 } [get_ports {adc_refclk_0_n}]  ;# ADC_224_REFCLK_N from U83.22 RFoutAN
+set_property -dict {LOC AD5 } [get_ports {adc_refclk_1_p}]  ;# ADC_225_REFCLK_P from U83.19 RFoutBP
+set_property -dict {LOC AD4 } [get_ports {adc_refclk_1_n}]  ;# ADC_225_REFCLK_N from U83.18 RFoutBN
+set_property -dict {LOC AB5 } [get_ports {adc_refclk_2_p}]  ;# ADC_226_REFCLK_P from U82.23 RFoutAP
+set_property -dict {LOC AB4 } [get_ports {adc_refclk_2_n}]  ;# ADC_226_REFCLK_N from U82.22 RFoutAN
+set_property -dict {LOC Y5  } [get_ports {adc_refclk_3_p}]  ;# ADC_227_REFCLK_P from U82.19 RFoutBP
+set_property -dict {LOC Y4  } [get_ports {adc_refclk_3_n}]  ;# ADC_227_REFCLK_N from U82.18 RFoutBN
+
+set_property -dict {LOC C2  } [get_ports {dac_vout_p[0]}]  ;# DAC_VOUT3_229_P from J3 (RA) via T1
+set_property -dict {LOC C1  } [get_ports {dac_vout_n[0]}]  ;# DAC_VOUT3_229_N from J3 (RA) via T1
+set_property -dict {LOC E2  } [get_ports {dac_vout_p[1]}]  ;# DAC_VOUT2_229_P from J13 (V) via T9
+set_property -dict {LOC E1  } [get_ports {dac_vout_n[1]}]  ;# DAC_VOUT2_229_N from J13 (V) via T9
+set_property -dict {LOC G2  } [get_ports {dac_vout_p[2]}]  ;# DAC_VOUT1_229_P from J4 (RA) via T2
+set_property -dict {LOC G1  } [get_ports {dac_vout_n[2]}]  ;# DAC_VOUT1_229_N from J4 (RA) via T2
+set_property -dict {LOC J2  } [get_ports {dac_vout_p[3]}]  ;# DAC_VOUT0_229_P from J14 (V) via T10
+set_property -dict {LOC J1  } [get_ports {dac_vout_n[3]}]  ;# DAC_VOUT0_229_N from J14 (V) via T10
+set_property -dict {LOC L2  } [get_ports {dac_vout_p[4]}]  ;# DAC_VOUT3_228_P from J5 (RA) via T3
+set_property -dict {LOC L1  } [get_ports {dac_vout_n[4]}]  ;# DAC_VOUT3_228_N from J5 (RA) via T3
+set_property -dict {LOC N2  } [get_ports {dac_vout_p[5]}]  ;# DAC_VOUT2_228_P from J15 (V) via T11
+set_property -dict {LOC N1  } [get_ports {dac_vout_n[5]}]  ;# DAC_VOUT2_228_N from J15 (V) via T11
+set_property -dict {LOC R2  } [get_ports {dac_vout_p[6]}]  ;# DAC_VOUT1_228_P from J6 (RA) via T4
+set_property -dict {LOC R1  } [get_ports {dac_vout_n[6]}]  ;# DAC_VOUT1_228_N from J6 (RA) via T4
+set_property -dict {LOC U2  } [get_ports {dac_vout_p[7]}]  ;# DAC_VOUT0_228_P from J16 (V) via T12
+set_property -dict {LOC U1  } [get_ports {dac_vout_n[7]}]  ;# DAC_VOUT0_228_N from J16 (V) via T12
+
+#set_property -dict {LOC R5  } [get_ports {dac_refclk_0_p}]  ;# DAC_228_REFCLK_P from U81.23 RFoutAP
+#set_property -dict {LOC R4  } [get_ports {dac_refclk_0_n}]  ;# DAC_228_REFCLK_N from U81.22 RFoutAN
+set_property -dict {LOC N5  } [get_ports {dac_refclk_1_p}]  ;# DAC_229_REFCLK_P from U81.19 RFoutBP
+set_property -dict {LOC N4  } [get_ports {dac_refclk_1_n}]  ;# DAC_229_REFCLK_N from U81.18 RFoutBN
+
+set_property -dict {LOC U5  } [get_ports {rfdc_sysref_p}]  ;# SYSREF_P_228 from U2.1 CLKout0_P
+set_property -dict {LOC U4  } [get_ports {rfdc_sysref_n}]  ;# SYSREF_N_228 from U2.2 CLKout0_N

src/eth/example/HTG_ZRF8/fpga/ip/usp_rfdc_1ghz_1gsps.tcl

@@ -0,0 +1,182 @@
+
+create_ip -name usp_rf_data_converter -vendor xilinx.com -library ip -module_name usp_rfdc_0
+
+set ADC_RATE {1.0}
+set ADC_REFCLK_FREQ {1000.000}
+set ADC_OUTCLK_FREQ {62.500}
+set ADC_FABRIC_FREQ {250.000}
+set ADC_DATA_WIDTH {4}
+
+set DAC_RATE $ADC_RATE
+set DAC_REFCLK_FREQ $ADC_REFCLK_FREQ
+set DAC_OUTCLK_FREQ $ADC_OUTCLK_FREQ
+set DAC_FABRIC_FREQ $ADC_FABRIC_FREQ
+set DAC_DATA_WIDTH $ADC_DATA_WIDTH
+set DAC_VOP {40.5}
+
+set_property -dict [list \
+    CONFIG.Axiclk_Freq {125} \
+    CONFIG.DAC_VOP_RTS {true} \
+    CONFIG.ADC0_Sampling_Rate $ADC_RATE \
+    CONFIG.ADC0_Refclk_Freq $ADC_REFCLK_FREQ \
+    CONFIG.ADC0_Outclk_Freq $ADC_OUTCLK_FREQ \
+    CONFIG.ADC0_Fabric_Freq $ADC_FABRIC_FREQ \
+    CONFIG.ADC_Data_Width00 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Data_Width01 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Slice02_Enable {true} \
+    CONFIG.ADC_Decimation_Mode02 {1} \
+    CONFIG.ADC_Mixer_Type02 {1} \
+    CONFIG.ADC_Data_Width02 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Coarse_Mixer_Freq02 {3} \
+    CONFIG.ADC_Slice03_Enable {true} \
+    CONFIG.ADC_Decimation_Mode03 {1} \
+    CONFIG.ADC_Mixer_Type03 {1} \
+    CONFIG.ADC_Data_Width03 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Coarse_Mixer_Freq03 {3} \
+    CONFIG.ADC1_Enable {1} \
+    CONFIG.ADC1_Sampling_Rate $ADC_RATE \
+    CONFIG.ADC1_Refclk_Freq $ADC_REFCLK_FREQ \
+    CONFIG.ADC1_Outclk_Freq $ADC_OUTCLK_FREQ \
+    CONFIG.ADC1_Fabric_Freq $ADC_FABRIC_FREQ \
+    CONFIG.ADC_Slice10_Enable {true} \
+    CONFIG.ADC_Decimation_Mode10 {1} \
+    CONFIG.ADC_Mixer_Type10 {1} \
+    CONFIG.ADC_Data_Width10 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Coarse_Mixer_Freq10 {3} \
+    CONFIG.ADC_Slice11_Enable {true} \
+    CONFIG.ADC_Decimation_Mode11 {1} \
+    CONFIG.ADC_Mixer_Type11 {1} \
+    CONFIG.ADC_Data_Width11 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Coarse_Mixer_Freq11 {3} \
+    CONFIG.ADC_Slice12_Enable {true} \
+    CONFIG.ADC_Decimation_Mode12 {1} \
+    CONFIG.ADC_Mixer_Type12 {1} \
+    CONFIG.ADC_Data_Width12 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Coarse_Mixer_Freq12 {3} \
+    CONFIG.ADC_OBS12 {0} \
+    CONFIG.ADC_Slice13_Enable {true} \
+    CONFIG.ADC_Decimation_Mode13 {1} \
+    CONFIG.ADC_Mixer_Type13 {1} \
+    CONFIG.ADC_Data_Width13 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Coarse_Mixer_Freq13 {3} \
+    CONFIG.ADC2_Enable {1} \
+    CONFIG.ADC2_Sampling_Rate $ADC_RATE \
+    CONFIG.ADC2_Refclk_Freq $ADC_REFCLK_FREQ \
+    CONFIG.ADC2_Outclk_Freq $ADC_OUTCLK_FREQ \
+    CONFIG.ADC2_Fabric_Freq $ADC_FABRIC_FREQ \
+    CONFIG.ADC_Slice20_Enable {true} \
+    CONFIG.ADC_Decimation_Mode20 {1} \
+    CONFIG.ADC_Mixer_Type20 {1} \
+    CONFIG.ADC_Data_Width20 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Coarse_Mixer_Freq20 {3} \
+    CONFIG.ADC_Slice21_Enable {true} \
+    CONFIG.ADC_Decimation_Mode21 {1} \
+    CONFIG.ADC_Mixer_Type21 {1} \
+    CONFIG.ADC_Data_Width21 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Coarse_Mixer_Freq21 {3} \
+    CONFIG.ADC_Slice22_Enable {true} \
+    CONFIG.ADC_Decimation_Mode22 {1} \
+    CONFIG.ADC_Mixer_Type22 {1} \
+    CONFIG.ADC_Data_Width22 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Coarse_Mixer_Freq22 {3} \
+    CONFIG.ADC_OBS22 {0} \
+    CONFIG.ADC_Slice23_Enable {true} \
+    CONFIG.ADC_Decimation_Mode23 {1} \
+    CONFIG.ADC_Mixer_Type23 {1} \
+    CONFIG.ADC_Data_Width23 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Coarse_Mixer_Freq23 {3} \
+    CONFIG.ADC3_Enable {1} \
+    CONFIG.ADC3_Sampling_Rate $ADC_RATE \
+    CONFIG.ADC3_Refclk_Freq $ADC_REFCLK_FREQ \
+    CONFIG.ADC3_Outclk_Freq $ADC_OUTCLK_FREQ \
+    CONFIG.ADC3_Fabric_Freq $ADC_FABRIC_FREQ \
+    CONFIG.ADC_Slice30_Enable {true} \
+    CONFIG.ADC_Decimation_Mode30 {1} \
+    CONFIG.ADC_Mixer_Type30 {1} \
+    CONFIG.ADC_Data_Width30 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Coarse_Mixer_Freq30 {3} \
+    CONFIG.ADC_Slice31_Enable {true} \
+    CONFIG.ADC_Decimation_Mode31 {1} \
+    CONFIG.ADC_Mixer_Type31 {1} \
+    CONFIG.ADC_Data_Width31 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Coarse_Mixer_Freq31 {3} \
+    CONFIG.ADC_Slice32_Enable {true} \
+    CONFIG.ADC_Decimation_Mode32 {1} \
+    CONFIG.ADC_Mixer_Type32 {1} \
+    CONFIG.ADC_Data_Width32 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Coarse_Mixer_Freq32 {3} \
+    CONFIG.ADC_OBS32 {0} \
+    CONFIG.ADC_Slice33_Enable {true} \
+    CONFIG.ADC_Decimation_Mode33 {1} \
+    CONFIG.ADC_Mixer_Type33 {1} \
+    CONFIG.ADC_Data_Width33 $ADC_DATA_WIDTH \
+    CONFIG.ADC_Coarse_Mixer_Freq33 {3} \
+    CONFIG.ADC_DSA_RTS {true} \
+    CONFIG.DAC0_Enable {1} \
+    CONFIG.DAC0_Sampling_Rate $DAC_RATE \
+    CONFIG.DAC0_Refclk_Freq $DAC_REFCLK_FREQ \
+    CONFIG.DAC0_Outclk_Freq $DAC_OUTCLK_FREQ \
+    CONFIG.DAC0_Fabric_Freq $DAC_FABRIC_FREQ \
+    CONFIG.DAC0_Clock_Source {6} \
+    CONFIG.DAC0_VOP $DAC_VOP \
+    CONFIG.DAC_Slice00_Enable {true} \
+    CONFIG.DAC_Data_Width00 $DAC_DATA_WIDTH \
+    CONFIG.DAC_Interpolation_Mode00 {1} \
+    CONFIG.DAC_Mixer_Type00 {1} \
+    CONFIG.DAC_Coarse_Mixer_Freq00 {3} \
+    CONFIG.DAC_Slice02_Enable {true} \
+    CONFIG.DAC_Data_Width02 $DAC_DATA_WIDTH \
+    CONFIG.DAC_Interpolation_Mode02 {1} \
+    CONFIG.DAC_Mixer_Type02 {1} \
+    CONFIG.DAC_Coarse_Mixer_Freq02 {3} \
+    CONFIG.DAC1_Enable {1} \
+    CONFIG.DAC1_Sampling_Rate $DAC_RATE \
+    CONFIG.DAC1_Refclk_Freq $DAC_REFCLK_FREQ \
+    CONFIG.DAC1_Outclk_Freq $DAC_OUTCLK_FREQ \
+    CONFIG.DAC1_Fabric_Freq $DAC_FABRIC_FREQ \
+    CONFIG.DAC1_VOP $DAC_VOP \
+    CONFIG.DAC_Slice10_Enable {true} \
+    CONFIG.DAC_Data_Width10 $DAC_DATA_WIDTH \
+    CONFIG.DAC_Interpolation_Mode10 {1} \
+    CONFIG.DAC_Mixer_Type10 {1} \
+    CONFIG.DAC_Coarse_Mixer_Freq10 {3} \
+    CONFIG.DAC_Slice12_Enable {true} \
+    CONFIG.DAC_Data_Width12 $DAC_DATA_WIDTH \
+    CONFIG.DAC_Interpolation_Mode12 {1} \
+    CONFIG.DAC_Mixer_Type12 {1} \
+    CONFIG.DAC_Coarse_Mixer_Freq12 {3} \
+    CONFIG.DAC2_Enable {1} \
+    CONFIG.DAC2_Sampling_Rate $DAC_RATE \
+    CONFIG.DAC2_Refclk_Freq $DAC_REFCLK_FREQ \
+    CONFIG.DAC2_Outclk_Freq $DAC_OUTCLK_FREQ \
+    CONFIG.DAC2_Fabric_Freq $DAC_FABRIC_FREQ \
+    CONFIG.DAC2_Clock_Dist {1} \
+    CONFIG.DAC2_VOP $DAC_VOP \
+    CONFIG.DAC_Slice20_Enable {true} \
+    CONFIG.DAC_Data_Width20 $DAC_DATA_WIDTH \
+    CONFIG.DAC_Interpolation_Mode20 {1} \
+    CONFIG.DAC_Mixer_Type20 {1} \
+    CONFIG.DAC_Coarse_Mixer_Freq20 {3} \
+    CONFIG.DAC_Slice22_Enable {true} \
+    CONFIG.DAC_Data_Width22 $DAC_DATA_WIDTH \
+    CONFIG.DAC_Interpolation_Mode22 {1} \
+    CONFIG.DAC_Mixer_Type22 {1} \
+    CONFIG.DAC_Coarse_Mixer_Freq22 {3} \
+    CONFIG.DAC3_Enable {1} \
+    CONFIG.DAC3_Sampling_Rate $DAC_RATE \
+    CONFIG.DAC3_Refclk_Freq $DAC_REFCLK_FREQ \
+    CONFIG.DAC3_Outclk_Freq $DAC_OUTCLK_FREQ \
+    CONFIG.DAC3_Fabric_Freq $DAC_FABRIC_FREQ \
+    CONFIG.DAC3_Clock_Source {6} \
+    CONFIG.DAC3_VOP $DAC_VOP \
+    CONFIG.DAC_Slice30_Enable {true} \
+    CONFIG.DAC_Data_Width30 $DAC_DATA_WIDTH \
+    CONFIG.DAC_Interpolation_Mode30 {1} \
+    CONFIG.DAC_Mixer_Type30 {1} \
+    CONFIG.DAC_Coarse_Mixer_Freq30 {3} \
+    CONFIG.DAC_Slice32_Enable {true} \
+    CONFIG.DAC_Data_Width32 $DAC_DATA_WIDTH \
+    CONFIG.DAC_Interpolation_Mode32 {1} \
+    CONFIG.DAC_Mixer_Type32 {1} \
+    CONFIG.DAC_Coarse_Mixer_Freq32 {3} \
+] [get_ips usp_rfdc_0]

src/eth/example/HTG_ZRF8/fpga/lib/taxi

@@ -0,0 +1 @@
+../../../../../../

src/eth/example/HTG_ZRF8/fpga/pll/HTG-ZRF8-EM-161-ZRF8EM01-Registers.txt

@@ -0,0 +1,412 @@
+# Si534x/7x/8x/9x Registers Script
+# 
+# Part: Si5341
+# Project File: X:\Projects\taxi\src\eth\example\HTG_ZRF8\fpga\pll\HTG-ZRF8-EM-161-ZRF8EM01.slabtimeproj
+# Design ID: ZRF8EM01
+# Includes Pre/Post Download Control Register Writes: Yes
+# Die Revision: B1
+# Creator: ClockBuilder Pro v4.1 [2021-09-22]
+# Created On: 2025-09-02 08:11:56 GMT-07:00
+Address,Data
+# 
+# Start configuration preamble
+0x0B24,0xC0
+0x0B25,0x00
+# Rev D stuck divider fix
+0x0502,0x01
+0x0505,0x03
+0x0957,0x17
+0x0B4E,0x1A
+# End configuration preamble
+# 
+# Delay 300 msec
+#    Delay is worst case time for device to complete any calibration
+#    that is running due to device state change previous to this script
+#    being processed.
+# 
+# Start configuration registers
+0x0006,0x00
+0x0007,0x00
+0x0008,0x00
+0x000B,0x74
+0x0017,0xD0
+0x0018,0xFF
+0x0021,0x0F
+0x0022,0x00
+0x002B,0x02
+0x002C,0x20
+0x002D,0x00
+0x002E,0x00
+0x002F,0x00
+0x0030,0x00
+0x0031,0x00
+0x0032,0x00
+0x0033,0x00
+0x0034,0x00
+0x0035,0x00
+0x0036,0x00
+0x0037,0x00
+0x0038,0x00
+0x0039,0x00
+0x003A,0x00
+0x003B,0x00
+0x003C,0x00
+0x003D,0x00
+0x0041,0x00
+0x0042,0x00
+0x0043,0x00
+0x0044,0x00
+0x009E,0x00
+0x0102,0x01
+0x0108,0x02
+0x0109,0x09
+0x010A,0x33
+0x010B,0x08
+0x010D,0x02
+0x010E,0x09
+0x010F,0x33
+0x0110,0x0A
+0x0112,0x02
+0x0113,0x09
+0x0114,0x33
+0x0115,0x0B
+0x0117,0x06
+0x0118,0x09
+0x0119,0x33
+0x011A,0x09
+0x011C,0x02
+0x011D,0x09
+0x011E,0x33
+0x011F,0x0B
+0x0121,0x02
+0x0122,0x09
+0x0123,0x33
+0x0124,0x08
+0x0126,0x02
+0x0127,0x09
+0x0128,0x33
+0x0129,0x08
+0x012B,0x02
+0x012C,0x09
+0x012D,0x33
+0x012E,0x0A
+0x0130,0x02
+0x0131,0x09
+0x0132,0x33
+0x0133,0x0A
+0x013A,0x02
+0x013B,0x09
+0x013C,0x33
+0x013D,0x0A
+0x013F,0x00
+0x0140,0x00
+0x0141,0x40
+0x0206,0x00
+0x0208,0x00
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
+0x020C,0x00
+0x020D,0x00
+0x020E,0x00
+0x020F,0x00
+0x0210,0x00
+0x0211,0x00
+0x0212,0x00
+0x0213,0x00
+0x0214,0x00
+0x0215,0x00
+0x0216,0x00
+0x0217,0x00
+0x0218,0x00
+0x0219,0x00
+0x021A,0x00
+0x021B,0x00
+0x021C,0x00
+0x021D,0x00
+0x021E,0x00
+0x021F,0x00
+0x0220,0x00
+0x0221,0x00
+0x0222,0x00
+0x0223,0x00
+0x0224,0x00
+0x0225,0x00
+0x0226,0x00
+0x0227,0x00
+0x0228,0x00
+0x0229,0x00
+0x022A,0x00
+0x022B,0x00
+0x022C,0x00
+0x022D,0x00
+0x022E,0x00
+0x022F,0x00
+0x0235,0x00
+0x0236,0x00
+0x0237,0x00
+0x0238,0x00
+0x0239,0x96
+0x023A,0x00
+0x023B,0x00
+0x023C,0x00
+0x023D,0x00
+0x023E,0x80
+0x024A,0x02
+0x024B,0x00
+0x024C,0x00
+0x024D,0x3B
+0x024E,0x00
+0x024F,0x00
+0x0250,0x1A
+0x0251,0x00
+0x0252,0x00
+0x0253,0x00
+0x0254,0x00
+0x0255,0x00
+0x0256,0x19
+0x0257,0x00
+0x0258,0x00
+0x0259,0x02
+0x025A,0x00
+0x025B,0x00
+0x025C,0x02
+0x025D,0x00
+0x025E,0x00
+0x025F,0x01
+0x0260,0x00
+0x0261,0x00
+0x0262,0x02
+0x0263,0x00
+0x0264,0x00
+0x0268,0x01
+0x0269,0x00
+0x026A,0x00
+0x026B,0x5A
+0x026C,0x52
+0x026D,0x46
+0x026E,0x38
+0x026F,0x45
+0x0270,0x4D
+0x0271,0x30
+0x0272,0x31
+0x0302,0x00
+0x0303,0x00
+0x0304,0x00
+0x0305,0x00
+0x0306,0x08
+0x0307,0x00
+0x0308,0x00
+0x0309,0x00
+0x030A,0x80
+0x030B,0x89
+0x030C,0x00
+0x030D,0x00
+0x030E,0x00
+0x030F,0x00
+0x0310,0x00
+0x0311,0x24
+0x0312,0x00
+0x0313,0x00
+0x0314,0x00
+0x0315,0x00
+0x0316,0xA0
+0x0317,0x00
+0x0318,0x00
+0x0319,0x00
+0x031A,0x00
+0x031B,0x00
+0x031C,0x06
+0x031D,0x00
+0x031E,0x00
+0x031F,0x00
+0x0320,0x00
+0x0321,0x80
+0x0322,0x00
+0x0323,0x00
+0x0324,0x00
+0x0325,0x00
+0x0326,0x40
+0x0327,0x06
+0x0328,0x00
+0x0329,0x00
+0x032A,0x00
+0x032B,0x00
+0x032C,0x9C
+0x032D,0x00
+0x032E,0x00
+0x032F,0x00
+0x0330,0x00
+0x0331,0x00
+0x0332,0x00
+0x0333,0x00
+0x0334,0x00
+0x0335,0x00
+0x0336,0x00
+0x0337,0x00
+0x0338,0x00
+0x0339,0x1F
+0x033B,0x00
+0x033C,0x00
+0x033D,0x00
+0x033E,0x00
+0x033F,0x00
+0x0340,0x00
+0x0341,0x00
+0x0342,0x00
+0x0343,0x00
+0x0344,0x00
+0x0345,0x00
+0x0346,0x00
+0x0347,0x00
+0x0348,0x00
+0x0349,0x00
+0x034A,0x00
+0x034B,0x00
+0x034C,0x00
+0x034D,0x00
+0x034E,0x00
+0x034F,0x00
+0x0350,0x00
+0x0351,0x00
+0x0352,0x00
+0x0353,0x00
+0x0354,0x00
+0x0355,0x00
+0x0356,0x00
+0x0357,0x00
+0x0358,0x00
+0x0359,0x00
+0x035A,0x00
+0x035B,0x00
+0x035C,0x00
+0x035D,0x00
+0x035E,0x00
+0x035F,0x00
+0x0360,0x00
+0x0361,0x00
+0x0362,0x00
+0x0802,0x00
+0x0803,0x00
+0x0804,0x00
+0x0805,0x00
+0x0806,0x00
+0x0807,0x00
+0x0808,0x00
+0x0809,0x00
+0x080A,0x00
+0x080B,0x00
+0x080C,0x00
+0x080D,0x00
+0x080E,0x00
+0x080F,0x00
+0x0810,0x00
+0x0811,0x00
+0x0812,0x00
+0x0813,0x00
+0x0814,0x00
+0x0815,0x00
+0x0816,0x00
+0x0817,0x00
+0x0818,0x00
+0x0819,0x00
+0x081A,0x00
+0x081B,0x00
+0x081C,0x00
+0x081D,0x00
+0x081E,0x00
+0x081F,0x00
+0x0820,0x00
+0x0821,0x00
+0x0822,0x00
+0x0823,0x00
+0x0824,0x00
+0x0825,0x00
+0x0826,0x00
+0x0827,0x00
+0x0828,0x00
+0x0829,0x00
+0x082A,0x00
+0x082B,0x00
+0x082C,0x00
+0x082D,0x00
+0x082E,0x00
+0x082F,0x00
+0x0830,0x00
+0x0831,0x00
+0x0832,0x00
+0x0833,0x00
+0x0834,0x00
+0x0835,0x00
+0x0836,0x00
+0x0837,0x00
+0x0838,0x00
+0x0839,0x00
+0x083A,0x00
+0x083B,0x00
+0x083C,0x00
+0x083D,0x00
+0x083E,0x00
+0x083F,0x00
+0x0840,0x00
+0x0841,0x00
+0x0842,0x00
+0x0843,0x00
+0x0844,0x00
+0x0845,0x00
+0x0846,0x00
+0x0847,0x00
+0x0848,0x00
+0x0849,0x00
+0x084A,0x00
+0x084B,0x00
+0x084C,0x00
+0x084D,0x00
+0x084E,0x00
+0x084F,0x00
+0x0850,0x00
+0x0851,0x00
+0x0852,0x00
+0x0853,0x00
+0x0854,0x00
+0x0855,0x00
+0x0856,0x00
+0x0857,0x00
+0x0858,0x00
+0x0859,0x00
+0x085A,0x00
+0x085B,0x00
+0x085C,0x00
+0x085D,0x00
+0x085E,0x00
+0x085F,0x00
+0x0860,0x00
+0x0861,0x00
+0x090E,0x02
+0x091C,0x04
+0x0943,0x01
+0x0949,0x00
+0x094A,0x00
+0x094E,0x49
+0x094F,0x02
+0x095E,0x00
+0x0A02,0x00
+0x0A03,0x0F
+0x0A04,0x04
+0x0A05,0x0F
+0x0A14,0x00
+0x0A1A,0x00
+0x0A20,0x00
+0x0A26,0x00
+0x0A2C,0x00
+0x0B44,0x0F
+0x0B4A,0x10
+0x0B57,0x0E
+0x0B58,0x01
+# End configuration registers
+# 
+# Start configuration postamble
+0x001C,0x01
+0x0B24,0xC3
+0x0B25,0x02
+# End configuration postamble

src/eth/example/HTG_ZRF8/fpga/pll/HTG-ZRF8-R2-161-ZRF8R201-Registers.txt

@@ -0,0 +1,412 @@
+# Si534x/7x/8x/9x Registers Script
+# 
+# Part: Si5341
+# Project File: X:\Projects\taxi\src\eth\example\HTG_ZRF8\fpga\pll\HTG-ZRF8-R2-161-ZRF8R201.slabtimeproj
+# Design ID: ZRF8R201
+# Includes Pre/Post Download Control Register Writes: Yes
+# Die Revision: B1
+# Creator: ClockBuilder Pro v4.1 [2021-09-22]
+# Created On: 2025-09-02 08:30:10 GMT-07:00
+Address,Data
+# 
+# Start configuration preamble
+0x0B24,0xC0
+0x0B25,0x00
+# Rev D stuck divider fix
+0x0502,0x01
+0x0505,0x03
+0x0957,0x17
+0x0B4E,0x1A
+# End configuration preamble
+# 
+# Delay 300 msec
+#    Delay is worst case time for device to complete any calibration
+#    that is running due to device state change previous to this script
+#    being processed.
+# 
+# Start configuration registers
+0x0006,0x00
+0x0007,0x00
+0x0008,0x00
+0x000B,0x74
+0x0017,0xD0
+0x0018,0xFF
+0x0021,0x0F
+0x0022,0x00
+0x002B,0x02
+0x002C,0x20
+0x002D,0x00
+0x002E,0x00
+0x002F,0x00
+0x0030,0x00
+0x0031,0x00
+0x0032,0x00
+0x0033,0x00
+0x0034,0x00
+0x0035,0x00
+0x0036,0x00
+0x0037,0x00
+0x0038,0x00
+0x0039,0x00
+0x003A,0x00
+0x003B,0x00
+0x003C,0x00
+0x003D,0x00
+0x0041,0x00
+0x0042,0x00
+0x0043,0x00
+0x0044,0x00
+0x009E,0x00
+0x0102,0x01
+0x0108,0x02
+0x0109,0x09
+0x010A,0x33
+0x010B,0x0A
+0x010D,0x02
+0x010E,0x09
+0x010F,0x33
+0x0110,0x0A
+0x0112,0x02
+0x0113,0x09
+0x0114,0x33
+0x0115,0x08
+0x0117,0x02
+0x0118,0x09
+0x0119,0x33
+0x011A,0x08
+0x011C,0x02
+0x011D,0x09
+0x011E,0x33
+0x011F,0x08
+0x0121,0x02
+0x0122,0x09
+0x0123,0x33
+0x0124,0x0A
+0x0126,0x02
+0x0127,0x09
+0x0128,0x33
+0x0129,0x0B
+0x012B,0x02
+0x012C,0x09
+0x012D,0x33
+0x012E,0x0A
+0x0130,0x02
+0x0131,0x09
+0x0132,0x33
+0x0133,0x0B
+0x013A,0x06
+0x013B,0x09
+0x013C,0x33
+0x013D,0x09
+0x013F,0x00
+0x0140,0x00
+0x0141,0x40
+0x0206,0x00
+0x0208,0x00
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
+0x020C,0x00
+0x020D,0x00
+0x020E,0x00
+0x020F,0x00
+0x0210,0x00
+0x0211,0x00
+0x0212,0x00
+0x0213,0x00
+0x0214,0x00
+0x0215,0x00
+0x0216,0x00
+0x0217,0x00
+0x0218,0x00
+0x0219,0x00
+0x021A,0x00
+0x021B,0x00
+0x021C,0x00
+0x021D,0x00
+0x021E,0x00
+0x021F,0x00
+0x0220,0x00
+0x0221,0x00
+0x0222,0x00
+0x0223,0x00
+0x0224,0x00
+0x0225,0x00
+0x0226,0x00
+0x0227,0x00
+0x0228,0x00
+0x0229,0x00
+0x022A,0x00
+0x022B,0x00
+0x022C,0x00
+0x022D,0x00
+0x022E,0x00
+0x022F,0x00
+0x0235,0x00
+0x0236,0x00
+0x0237,0x00
+0x0238,0x00
+0x0239,0x96
+0x023A,0x00
+0x023B,0x00
+0x023C,0x00
+0x023D,0x00
+0x023E,0x80
+0x024A,0x02
+0x024B,0x00
+0x024C,0x00
+0x024D,0x01
+0x024E,0x00
+0x024F,0x00
+0x0250,0x02
+0x0251,0x00
+0x0252,0x00
+0x0253,0x02
+0x0254,0x00
+0x0255,0x00
+0x0256,0x02
+0x0257,0x00
+0x0258,0x00
+0x0259,0x02
+0x025A,0x00
+0x025B,0x00
+0x025C,0x19
+0x025D,0x00
+0x025E,0x00
+0x025F,0x3B
+0x0260,0x00
+0x0261,0x00
+0x0262,0x1A
+0x0263,0x00
+0x0264,0x00
+0x0268,0x00
+0x0269,0x00
+0x026A,0x00
+0x026B,0x5A
+0x026C,0x52
+0x026D,0x46
+0x026E,0x38
+0x026F,0x52
+0x0270,0x32
+0x0271,0x30
+0x0272,0x31
+0x0302,0x00
+0x0303,0x00
+0x0304,0x00
+0x0305,0x00
+0x0306,0x08
+0x0307,0x00
+0x0308,0x00
+0x0309,0x00
+0x030A,0x80
+0x030B,0x89
+0x030C,0x00
+0x030D,0x00
+0x030E,0x00
+0x030F,0x00
+0x0310,0x00
+0x0311,0x24
+0x0312,0x00
+0x0313,0x00
+0x0314,0x00
+0x0315,0x00
+0x0316,0xA0
+0x0317,0x00
+0x0318,0x00
+0x0319,0x00
+0x031A,0x00
+0x031B,0x00
+0x031C,0x06
+0x031D,0x00
+0x031E,0x00
+0x031F,0x00
+0x0320,0x00
+0x0321,0x80
+0x0322,0x00
+0x0323,0x00
+0x0324,0x00
+0x0325,0x00
+0x0326,0x40
+0x0327,0x06
+0x0328,0x00
+0x0329,0x00
+0x032A,0x00
+0x032B,0x00
+0x032C,0x9C
+0x032D,0x00
+0x032E,0x00
+0x032F,0x00
+0x0330,0x00
+0x0331,0x00
+0x0332,0x00
+0x0333,0x00
+0x0334,0x00
+0x0335,0x00
+0x0336,0x00
+0x0337,0x00
+0x0338,0x00
+0x0339,0x1F
+0x033B,0x00
+0x033C,0x00
+0x033D,0x00
+0x033E,0x00
+0x033F,0x00
+0x0340,0x00
+0x0341,0x00
+0x0342,0x00
+0x0343,0x00
+0x0344,0x00
+0x0345,0x00
+0x0346,0x00
+0x0347,0x00
+0x0348,0x00
+0x0349,0x00
+0x034A,0x00
+0x034B,0x00
+0x034C,0x00
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+0x034E,0x00
+0x034F,0x00
+0x0350,0x00
+0x0351,0x00
+0x0352,0x00
+0x0353,0x00
+0x0354,0x00
+0x0355,0x00
+0x0356,0x00
+0x0357,0x00
+0x0358,0x00
+0x0359,0x00
+0x035A,0x00
+0x035B,0x00
+0x035C,0x00
+0x035D,0x00
+0x035E,0x00
+0x035F,0x00
+0x0360,0x00
+0x0361,0x00
+0x0362,0x00
+0x0802,0x00
+0x0803,0x00
+0x0804,0x00
+0x0805,0x00
+0x0806,0x00
+0x0807,0x00
+0x0808,0x00
+0x0809,0x00
+0x080A,0x00
+0x080B,0x00
+0x080C,0x00
+0x080D,0x00
+0x080E,0x00
+0x080F,0x00
+0x0810,0x00
+0x0811,0x00
+0x0812,0x00
+0x0813,0x00
+0x0814,0x00
+0x0815,0x00
+0x0816,0x00
+0x0817,0x00
+0x0818,0x00
+0x0819,0x00
+0x081A,0x00
+0x081B,0x00
+0x081C,0x00
+0x081D,0x00
+0x081E,0x00
+0x081F,0x00
+0x0820,0x00
+0x0821,0x00
+0x0822,0x00
+0x0823,0x00
+0x0824,0x00
+0x0825,0x00
+0x0826,0x00
+0x0827,0x00
+0x0828,0x00
+0x0829,0x00
+0x082A,0x00
+0x082B,0x00
+0x082C,0x00
+0x082D,0x00
+0x082E,0x00
+0x082F,0x00
+0x0830,0x00
+0x0831,0x00
+0x0832,0x00
+0x0833,0x00
+0x0834,0x00
+0x0835,0x00
+0x0836,0x00
+0x0837,0x00
+0x0838,0x00
+0x0839,0x00
+0x083A,0x00
+0x083B,0x00
+0x083C,0x00
+0x083D,0x00
+0x083E,0x00
+0x083F,0x00
+0x0840,0x00
+0x0841,0x00
+0x0842,0x00
+0x0843,0x00
+0x0844,0x00
+0x0845,0x00
+0x0846,0x00
+0x0847,0x00
+0x0848,0x00
+0x0849,0x00
+0x084A,0x00
+0x084B,0x00
+0x084C,0x00
+0x084D,0x00
+0x084E,0x00
+0x084F,0x00
+0x0850,0x00
+0x0851,0x00
+0x0852,0x00
+0x0853,0x00
+0x0854,0x00
+0x0855,0x00
+0x0856,0x00
+0x0857,0x00
+0x0858,0x00
+0x0859,0x00
+0x085A,0x00
+0x085B,0x00
+0x085C,0x00
+0x085D,0x00
+0x085E,0x00
+0x085F,0x00
+0x0860,0x00
+0x0861,0x00
+0x090E,0x02
+0x091C,0x04
+0x0943,0x01
+0x0949,0x00
+0x094A,0x00
+0x094E,0x49
+0x094F,0x02
+0x095E,0x00
+0x0A02,0x00
+0x0A03,0x0F
+0x0A04,0x04
+0x0A05,0x0F
+0x0A14,0x00
+0x0A1A,0x00
+0x0A20,0x00
+0x0A26,0x00
+0x0A2C,0x00
+0x0B44,0x0F
+0x0B4A,0x10
+0x0B57,0x0E
+0x0B58,0x01
+# End configuration registers
+# 
+# Start configuration postamble
+0x001C,0x01
+0x0B24,0xC3
+0x0B25,0x02
+# End configuration postamble

src/eth/example/HTG_ZRF8/fpga/pll/LMK04832_EM_250.txt

@@ -0,0 +1,270 @@
+# Configuration for LMK04832 PLL on HTG-ZRF8-EM
+
+# PLL1
+# CLKin0 = 12.2880 MHz TCXO
+# CLKin1 = 10 MHz
+# CLKin0 R = 768
+# CLKin1 R = 625
+# PFD = in0 / R0 = in1 / R1 = 16 kHz
+# N1 = 7680
+# VCO = PFD * N1 = 122.88 MHz
+# Ext VCO is 122.88 MHz
+
+# PLL2
+# 122.88 MHz from ext VCO
+# VCO0 range 2440 - 2580 MHz
+# VCO1 range 2945 - 3255 MHz
+# R2 = 1536
+# P = 2
+# N2 = 15625
+# PFD = 122.88 / R2 = 0.08
+# VCO = PFD * P * N2 = 2500
+# VCO/10 = 250 MHz
+# VCO/250 = 10 MHz
+# VCO/1280 = 1.953125 MHz
+
+# CLKout0: DAC 228 SYSREF
+# CLKout1: SYNC_IN_PLL1/SYNC_IN_PLL2
+# CLKout2: RF_CLKOUT to Si5341
+# CLKout3: SYNC_IN_PLL3
+# CLKout4: CLK_IN_PLL3
+# CLKout5: NC
+# CLKout6: CLK_IN_PLL2
+# CLKout7: NC
+# CLKout8: LMK_CLK_OUT SMPM
+# CLKout9: NC
+# CLKout10: CLK_IN_PLL1
+# CLKout11: NC
+# CLKout12: SYSREF_FPGA
+# CLKout13: REFCLK_FPGA
+
+Address,Data
+
+# Reset
+0x000,0x80
+
+# Configure outputs
+
+# DCLK0_1_DIV: 10 (2500/10 = 250)
+0x100,0x0a
+# DCLK0_1_DDLY: 10
+0x101,0x0a
+# CLKout0_1_PD
+0x102,0x00
+# CLKout0_SRC_MUX: 1 (sysref)
+0x103,0x60
+# CLKout1_SRC_MUX: 1 (sysref)
+0x104,0x20
+# SCLK0_1_ADLY: 0
+0x105,0x00
+# SCLK0_1_DDLY: 0
+0x106,0x00
+# CLKout0_FMT: 1 (LVDS)
+# CLKout1_FMT: 15 (CMOS norm/norm)
+0x107,0xf1
+# DCLK2_3_DIV: 10 (2500/10 = 250)
+0x108,0x0a
+# DCLK2_3_DDLY: 10
+0x109,0x0a
+# CLKout2_3_PD
+0x10a,0x00
+# CLKout2_SRC_MUX: 0 (device clock)
+0x10b,0x40
+# CLKout3_SRC_MUX: 1 (sysref)
+0x10c,0x20
+# SCLK2_3_ADLY: 0
+0x10d,0x00
+# SCLK2_3_DDLY: 0
+0x10e,0x00
+# CLKout2_FMT: 1 (LVDS)
+# CLKout3_FMT: 12 (CMOS norm/norm)
+0x10f,0xc1
+# DCLK4_5_DIV: 10 (2500/10 = 250)
+0x110,0x0a
+# DCLK4_5_DDLY: 10
+0x111,0x0a
+# CLKout4_5_PD
+0x112,0x00
+# CLKout4_SRC_MUX: 0 (device clock)
+0x113,0x40
+# CLKout5_SRC_MUX: 1 (sysref)
+0x114,0x20
+# SCLK4_5_ADLY: 0
+0x115,0x00
+# SCLK4_5_DDLY: 0
+0x116,0x00
+# CLKout4_FMT: 1 (LVDS)
+# CLKout5_FMT: 0 (PD)
+0x117,0x01
+# DCLK6_7_DIV: 10 (2500/10 = 250)
+0x118,0x0a
+# DCLK6_7_DDLY: 10
+0x119,0x0a
+# CLKout6_7_PD
+0x11a,0x00
+# CLKout6_SRC_MUX: 0 (device clock)
+0x11b,0x40
+# CLKout7_SRC_MUX: 1 (sysref)
+0x11c,0x20
+# SCLK6_7_ADLY: 0
+0x11d,0x00
+# SCLK6_7_DDLY: 0
+0x11e,0x00
+# CLKout6_FMT: 1 (LVDS)
+# CLKout7_FMT: 0 (PD)
+0x11f,0x01
+# DCLK8_9_DIV: 250 (2500/250 = 10)
+0x120,0xfa
+# DCLK8_9_DDLY: 10
+0x121,0x0a
+# CLKout8_9_PD
+0x122,0x00
+# CLKout8_SRC_MUX: 0 (device clock)
+0x123,0x40
+# CLKout9_SRC_MUX: 1 (sysref)
+0x124,0x20
+# SCLK8_9_ADLY: 0
+0x125,0x00
+# SCLK8_9_DDLY: 0
+0x126,0x00
+# CLKout8_FMT: 5 (LVPECL 2000 mV)
+# CLKout9_FMT: 0 (PD)
+0x127,0x05
+# DCLK10_11_DIV: 10 (2500/10 = 250)
+0x128,0x0a
+# DCLK10_11_DDLY: 10
+0x129,0x0a
+# CLKout10_11_PD
+0x12a,0x00
+# CLKout10_SRC_MUX: 0 (device clock)
+0x12b,0x40
+# CLKout11_SRC_MUX: 1 (sysref)
+0x12c,0x20
+# SCLK10_11_ADLY: 0
+0x12d,0x00
+# SCLK10_11_DDLY: 0
+0x12e,0x00
+# CLKout10_FMT: 1 (LVDS)
+# CLKout11_FMT: 0 (PD)
+0x12f,0x01
+# DCLK12_13_DIV: 10 (2500/10 = 250)
+0x130,0x0a
+# DCLK12_13_DDLY: 10
+0x131,0x0a
+# CLKout12_13_PD
+0x132,0x00
+# CLKout12_SRC_MUX: 1 (sysref)
+0x133,0x60
+# CLKout13_SRC_MUX: 0 (device clock)
+0x134,0x00
+# SCLK12_13_ADLY: 0
+0x135,0x00
+# SCLK12_13_DDLY: 0
+0x136,0x00
+# CLKout12_FMT: 1 (LVDS)
+# CLKout13_FMT: 1 (LVDS)
+0x137,0x11
+
+# configure PLL1
+
+# VCO_MUX: VCO0
+# OSCout_FMT: power down
+0x138,0x00
+# PLL2_RCLK_MUX: 0 (OSCin)
+# PLL2_NCLK_MUX: 0 (prescaler)
+# PLL1_NCLK_MUX: 0 (OSCin)
+# FB_MUX: 0
+# FB_MUX_EN: 0
+0x13f,0x00
+# release power down
+0x140,0x00
+# 0x141,0x00
+# 0x142,0x00
+# 0x143,0x00
+# 0x144,0x00
+# 0x145,0x00
+# enable CLKin0 and CLKin1 with bipolar buffers
+0x146,0x18
+# route CLKin0 and CLKin1 to PLL1, enable auto revert
+0x147,0x8a
+# CLKin_SEL0: input
+0x148,0x00
+# CLKin_SEL1: input
+0x149,0x00
+# reset mux/type: input
+0x14a,0x00
+# auto DAC
+0x14b,0x10
+# MAN_DAC
+0x14c,0x00
+# DAC trip low: 0
+0x14d,0x00
+# DAC trip high: 63
+# DAC_CLK_MULT: 3 (16384)
+0x14e,0xff
+# DAC_CLK_CNTR
+0x14f,0x7f
+# no holdover
+0x150,0x00
+# holdover DLD count
+#0x151,0x00
+#0x152,0x00
+# CLKin0 R = 768 (0x300)
+0x153,0x03
+0x154,0x00
+# CLKin1 R = 625 (0x271)
+0x155,0x02
+0x156,0x71
+# CLKin2 R
+#0x157,0x00
+#0x158,0x00
+# PLL1 N = 7680 (0x1e00)
+0x159,0x1e
+0x15a,0x00
+# PLL1_WND_SIZE: 3
+# PLL1_CP_TRI: 0
+# PLL1_CP_POL: 1
+# PLL1_CP_GAIN: 4
+0x15b,0xd4
+# PLL1_DLD_CNT: 32, 0
+0x15c,0x20
+0x15d,0x00
+# HOLDOVER_EXIT_NADJ: 30
+0x15e,0x1e
+# PLL1 LD pin: SPI readback
+0x15f,0x3b
+
+# configure PLL2
+
+# release PLL2 PD
+0x173,0x10
+
+# PLL2 R: 1536 (0x600)
+0x160,0x06
+0x161,0x00
+# PLL2 P: 2 (2)
+# OSCin_FREQ: 1 (63-127)
+# 2X: off
+0x162,0x44
+# PLL2_N_CAL: 15625 (0x3d09)
+0x163,0x00
+0x164,0x3d
+0x165,0x09
+# PLL2_N_CAL: 15625 (0x3d09)
+0x166,0x00
+0x167,0x3d
+0x168,0x09
+# PLL2_WND_SIZE: 2 (1.8 ns)
+# PLL2_CP_GAIN: 3
+# PLL2_CP_POL: 0
+# PLL2_CP_TRI: 0
+# PLL2_DLD_EN: 1
+0x169,0x59
+# PLL2_DLD_CNT: 32, 0
+0x16a,0x20
+0x16b,0x00
+# PLL2 LD pin: PLL1+PLL2 DLD
+0x16e,0x1b
+
+# release PLL1 R reset
+0x177,0x00

src/eth/example/HTG_ZRF8/fpga/pll/LMK04832_R2_250.txt

@@ -0,0 +1,270 @@
+# Configuration for LMK04832 PLL on HTG-ZRF8-R2
+
+# PLL1
+# CLKin0 = 12.2880 MHz TCXO
+# CLKin1 = 10 MHz
+# CLKin0 R = 768
+# CLKin1 R = 625
+# PFD = in0 / R0 = in1 / R1 = 16 kHz
+# N1 = 7680
+# VCO = PFD * N1 = 122.88 MHz
+# Ext VCO is 122.88 MHz
+
+# PLL2
+# 122.88 MHz from ext VCO
+# VCO0 range 2440 - 2580 MHz
+# VCO1 range 2945 - 3255 MHz
+# R2 = 1536
+# P = 2
+# N2 = 15625
+# PFD = 122.88 / R2 = 0.08
+# VCO = PFD * P * N2 = 2500
+# VCO/10 = 250 MHz
+# VCO/250 = 10 MHz
+# VCO/1280 = 1.953125 MHz
+
+# CLKout0: LMK_CLK_OUT SMPM
+# CLKout1: RF_CLKOUT to Si5341
+# CLKout2: CLK_IN_PLL3 (refclk)
+# CLKout3: DAC 228 SYSREF (sysref)
+# CLKout4: CLK_IN_PLL2 (refclk)
+# CLKout5: SYSREF_FPGA (sysref)
+# CLKout6: CLK_IN_PLL1 (refclk)
+# CLKout7: NC
+# CLKout8: REFCLK_FPGA (refclk)
+# CLKout9: NC
+# CLKout10: NC
+# CLKout11: SYNC_IN_PLL1/SYNC_IN_PLL2 (sysref)
+# CLKout12: NC
+# CLKout13: SYNC_IN_PLL3 (sysref)
+
+Address,Data
+
+# Reset
+0x000,0x80
+
+# Configure outputs
+
+# DCLK0_1_DIV: 10 (2500/10 = 250)
+0x100,0x0a
+# DCLK0_1_DDLY: 10
+0x101,0x0a
+# CLKout0_1_PD
+0x102,0x00
+# CLKout0_SRC_MUX: 0 (device clock)
+0x103,0x40
+# CLKout1_SRC_MUX: 0 (device clock)
+0x104,0x00
+# SCLK0_1_ADLY: 0
+0x105,0x00
+# SCLK0_1_DDLY: 0
+0x106,0x00
+# CLKout0_FMT: 5 (LVPECL 2000 mV)
+# CLKout1_FMT: 1 (LVDS)
+0x107,0x15
+# DCLK2_3_DIV: 10 (2500/10 = 250)
+0x108,0x0a
+# DCLK2_3_DDLY: 10
+0x109,0x0a
+# CLKout2_3_PD
+0x10a,0x00
+# CLKout2_SRC_MUX: 0 (device clock)
+0x10b,0x40
+# CLKout3_SRC_MUX: 1 (sysref)
+0x10c,0x20
+# SCLK2_3_ADLY: 0
+0x10d,0x00
+# SCLK2_3_DDLY: 0
+0x10e,0x00
+# CLKout2_FMT: 1 (LVDS)
+# CLKout3_FMT: 1 (LVDS)
+0x10f,0x11
+# DCLK4_5_DIV: 10 (2500/10 = 250)
+0x110,0x0a
+# DCLK4_5_DDLY: 10
+0x111,0x0a
+# CLKout4_5_PD
+0x112,0x00
+# CLKout4_SRC_MUX: 0 (device clock)
+0x113,0x40
+# CLKout5_SRC_MUX: 1 (sysref)
+0x114,0x20
+# SCLK4_5_ADLY: 0
+0x115,0x00
+# SCLK4_5_DDLY: 0
+0x116,0x00
+# CLKout4_FMT: 1 (LVDS)
+# CLKout5_FMT: 1 (LVDS)
+0x117,0x11
+# DCLK6_7_DIV: 10 (2500/10 = 250)
+0x118,0x0a
+# DCLK6_7_DDLY: 10
+0x119,0x0a
+# CLKout6_7_PD
+0x11a,0x00
+# CLKout6_SRC_MUX: 0 (device clock)
+0x11b,0x40
+# CLKout7_SRC_MUX: 1 (sysref)
+0x11c,0x20
+# SCLK6_7_ADLY: 0
+0x11d,0x00
+# SCLK6_7_DDLY: 0
+0x11e,0x00
+# CLKout6_FMT: 1 (LVDS)
+# CLKout7_FMT: 0 (PD)
+0x11f,0x01
+# DCLK8_9_DIV: 10 (2500/10 = 250)
+0x120,0x0a
+# DCLK8_9_DDLY: 10
+0x121,0x0a
+# CLKout8_9_PD
+0x122,0x00
+# CLKout8_SRC_MUX: 0 (device clock)
+0x123,0x40
+# CLKout9_SRC_MUX: 1 (sysref)
+0x124,0x20
+# SCLK8_9_ADLY: 0
+0x125,0x00
+# SCLK8_9_DDLY: 0
+0x126,0x00
+# CLKout8_FMT: 1 (LVDS)
+# CLKout9_FMT: 0 (PD)
+0x127,0x01
+# DCLK10_11_DIV: 10 (2500/10 = 250)
+0x128,0x0a
+# DCLK10_11_DDLY: 10
+0x129,0x0a
+# CLKout10_11_PD
+0x12a,0x00
+# CLKout10_SRC_MUX: 0 (device clock)
+0x12b,0x40
+# CLKout11_SRC_MUX: 1 (sysref)
+0x12c,0x20
+# SCLK10_11_ADLY: 0
+0x12d,0x00
+# SCLK10_11_DDLY: 0
+0x12e,0x00
+# CLKout10_FMT: 0 (PD)
+# CLKout11_FMT: 15 (CMOS norm/norm)
+0x12f,0xf0
+# DCLK12_13_DIV: 10 (2500/10 = 250)
+0x130,0x0a
+# DCLK12_13_DDLY: 10
+0x131,0x0a
+# CLKout12_13_PD
+0x132,0x00
+# CLKout12_SRC_MUX: 1 (sysref)
+0x133,0x60
+# CLKout13_SRC_MUX: 1 (sysref)
+0x134,0x20
+# SCLK12_13_ADLY: 0
+0x135,0x00
+# SCLK12_13_DDLY: 0
+0x136,0x00
+# CLKout12_FMT: 0 (PD)
+# CLKout13_FMT: 12 (CMOS norm/norm)
+0x137,0xc0
+
+# configure PLL1
+
+# VCO_MUX: VCO0
+# OSCout_FMT: power down
+0x138,0x00
+# PLL2_RCLK_MUX: 0 (OSCin)
+# PLL2_NCLK_MUX: 0 (prescaler)
+# PLL1_NCLK_MUX: 0 (OSCin)
+# FB_MUX: 0
+# FB_MUX_EN: 0
+0x13f,0x00
+# release power down
+0x140,0x00
+# 0x141,0x00
+# 0x142,0x00
+# 0x143,0x00
+# 0x144,0x00
+# 0x145,0x00
+# enable CLKin0 and CLKin1 with bipolar buffers
+0x146,0x18
+# route CLKin0 and CLKin1 to PLL1, enable auto revert
+0x147,0x8a
+# CLKin_SEL0: input
+0x148,0x00
+# CLKin_SEL1: input
+0x149,0x00
+# reset mux/type: input
+0x14a,0x00
+# auto DAC
+0x14b,0x10
+# MAN_DAC
+0x14c,0x00
+# DAC trip low: 0
+0x14d,0x00
+# DAC trip high: 63
+# DAC_CLK_MULT: 3 (16384)
+0x14e,0xff
+# DAC_CLK_CNTR
+0x14f,0x7f
+# no holdover
+0x150,0x00
+# holdover DLD count
+#0x151,0x00
+#0x152,0x00
+# CLKin0 R = 768 (0x300)
+0x153,0x03
+0x154,0x00
+# CLKin1 R = 625 (0x271)
+0x155,0x02
+0x156,0x71
+# CLKin2 R
+#0x157,0x00
+#0x158,0x00
+# PLL1 N = 7680 (0x1e00)
+0x159,0x1e
+0x15a,0x00
+# PLL1_WND_SIZE: 3
+# PLL1_CP_TRI: 0
+# PLL1_CP_POL: 1
+# PLL1_CP_GAIN: 4
+0x15b,0xd4
+# PLL1_DLD_CNT: 32, 0
+0x15c,0x20
+0x15d,0x00
+# HOLDOVER_EXIT_NADJ: 30
+0x15e,0x1e
+# PLL1 LD pin: SPI readback
+0x15f,0x3b
+
+# configure PLL2
+
+# release PLL2 PD
+0x173,0x10
+
+# PLL2 R: 1536 (0x600)
+0x160,0x06
+0x161,0x00
+# PLL2 P: 2 (2)
+# OSCin_FREQ: 1 (63-127)
+# 2X: off
+0x162,0x44
+# PLL2_N_CAL: 15625 (0x3d09)
+0x163,0x00
+0x164,0x3d
+0x165,0x09
+# PLL2_N_CAL: 15625 (0x3d09)
+0x166,0x00
+0x167,0x3d
+0x168,0x09
+# PLL2_WND_SIZE: 2 (1.8 ns)
+# PLL2_CP_GAIN: 3
+# PLL2_CP_POL: 0
+# PLL2_CP_TRI: 0
+# PLL2_DLD_EN: 1
+0x169,0x59
+# PLL2_DLD_CNT: 32, 0
+0x16a,0x20
+0x16b,0x00
+# PLL2 LD pin: PLL1+PLL2 DLD
+0x16e,0x1b
+
+# release PLL1 R reset
+0x177,0x00

src/eth/example/HTG_ZRF8/fpga/pll/LMX2594_250_1000.txt

@@ -0,0 +1,152 @@
+# Configuration for LMX2594 PLL
+
+# OSCin = 250 MHz
+# VCO range 7.5 - 15 GHz
+# R_PRE = 1
+# R = 1
+# PFD = OSCin / (R_PRE * R) = 250 MHz
+# N = 32
+# VCO = PFD * N = 8 GHz
+# VCO / 8 = 1 GHz
+
+# Reset
+0,0x2412
+0,0x2410
+
+# QUICK_RECAL_EN: 0
+# VCO_CAPCTRL_STRT: 0
+78,0x0001
+# 77,0x0000
+# 76,0x0000
+# CHDIV: 3 (8)
+75,0x08c0
+# 74,0x0000
+# 73,0x0000
+# 72,0x0000
+# 71,0x0000
+# MASH_RST_COUNT: 50000 (0xc350)
+70,0xc350
+# MASH_RST_COUNT: 50000 (0xc350)
+69,0x0000
+# 68,0x0000
+# 67,0x0000
+# 66,0x0000
+# 65,0x0000
+# 64,0x0000
+# 63,0x0000
+# 62,0x0000
+# 61,0x0000
+# LD_DELAY: 1000 (0x3e8)
+60,0x03e8
+# LD_TYPE: 1
+59,0x0001
+# INPIN_IGNORE: 1
+# INPIN_HYST: 0
+# INPIN_LVL: 0
+# INPIN_FMT: 0
+58,0x8001
+# 57,0x0000
+# 56,0x0000
+# 55,0x0000
+# 54,0x0000
+# 53,0x0000
+# 52,0x0000
+# 51,0x0000
+# 50,0x0000
+# 49,0x0000
+# 48,0x0000
+# 47,0x0000
+# OUTB_MUX: 0 (ch div)
+46,0x07fc
+# OUTA_MUX: 0 (ch div)
+# OUT_ISET: 0 (max)
+# OUTB_PWR: 31 (0x1f)
+45,0xc0df
+# OUTA_PWR: 31 (0x1f)
+# OUTB_PD: 0
+# OUTA_PD: 0
+# MASH_RESET_N: 0
+# MASH_ORDER: 0
+44,0x1f00
+# PLL_NUM: 0
+43,0x0000
+# PLL_NUM: 0
+42,0x0000
+# MASH_SEED: 0
+41,0x0000
+# MASH_SEED: 0
+40,0x0000
+# PLL_DEN: '1
+39,0xffff
+# PLL_DEN: '1
+38,0xffff
+# MASH_SEED_EN: 0
+# PFD_DLY_SEL: 2
+37,0x0204
+# PLL_N: 32 (0x20)
+36,0x0020
+# 35,0x0000
+# PLL_N: 32 (0x20)
+34,0x0000
+# 33,0x0000
+# 32,0x0000
+# CHDIV_DIV2: 1
+31,0x43ec
+# 30,0x0000
+# 29,0x0000
+# 28,0x0000
+# 27,0x0000
+# 26,0x0000
+# 25,0x0000
+# 24,0x0000
+# 23,0x0000
+# 22,0x0000
+# 21,0x0000
+# VCO_SEL: 7 (VCO7)
+# VCO_SEL_FORCE: 0
+20,0xf848
+# VCO_CAPCTRL: 183 (0xb7)
+19,0x27b7
+# 18,0x0000
+# VCO_DACISET_STRT: 250 (0xfa)
+17,0x00fa
+# VCO_DACISET: 128 (0x80)
+16,0x0080
+# 15,0x0000
+# CPG: 7
+14,0x1e70
+# PLL_R_PRE: 1
+12,0x5001
+# PLL_R: 1
+11,0x0018
+# MULT: 1 (bypass)
+10,0x10d8
+# OSC_2X: 0
+9,0x0604
+# VCO_DACISET_FORCE: 0
+# VCO_CAPCTRL_FORCE: 0
+8,0x2000
+# OUT_FORCE: 0
+7,0x00b2
+# ACAL_CMP_DLY: 10
+4,0x0a43
+# CAL_CLK_DIV: 3 (div 8)
+1,0x080b
+
+# FCAL_HPFD_ADJ: 3 (PFD > 200 MHz)
+# FCAL_LPFD_ADJ: 0 (PFD > 10 MHz)
+# FCAL_EN: 0
+# MUXOUT_LD_SEL: 0 (readback)
+# RESET: 0
+# POWERDOWN: 0
+0,0x2590
+
+# Delay 10 msec
+
+# FCAL_HPFD_ADJ: 3 (PFD > 200 MHz)
+# FCAL_LPFD_ADJ: 0 (PFD > 10 MHz)
+# FCAL_EN: 1
+# MUXOUT_LD_SEL: 0 (readback)
+# RESET: 0
+# POWERDOWN: 0
+0,0x2598

src/eth/example/HTG_ZRF8/fpga/pll/pll_i2c_init.py

@@ -0,0 +1,779 @@
+#!/usr/bin/env python
+"""
+Generates an I2C init module for multiple chips
+"""
+
+from jinja2 import Template
+
+
+def si5341_cmds(regs, dev_addr=0x74):
+    cur_page = None
+    cur_addr = None
+
+    cmds = []
+
+    print(f"Reading register list file '{regs}'...")
+
+    with open(regs, "r") as f:
+        for line in f:
+            line = line.strip()
+            if not line or line == "Address,Data":
+                continue
+            if line[0] == '#':
+                cmds.append(f"// {line[1:].strip()}")
+
+                if line.startswith("# Delay"):
+                    cmds.append("cmd_delay(10); // delay 300 ms")
+                    cur_addr = None
+
+                continue
+
+            d = line.split(",")
+            addr = int(d[0], 0)
+            page = (addr >> 8) & 0xff
+            data = int(d[1], 0)
+
+            if page != cur_page:
+                cmds.append(f"cmd_start(7'h{dev_addr:02x});")
+                cmds.append("cmd_wr(8'h01);")
+                cmds.append(f"cmd_wr(8'h{page:02x}); // set page {page:#04x}")
+                cur_page = page
+                cur_addr = None
+
+            if addr != cur_addr:
+                cmds.append(f"cmd_start(7'h{dev_addr:02x});")
+                cmds.append(f"cmd_wr(8'h{addr & 0xff:02x});")
+                cur_addr = addr
+
+            cmds.append(f"cmd_wr(8'h{data:02x}); // write {data:#04x} to {addr:#06x}")
+            cur_addr += 1
+
+    return cmds
+
+
+def lmk04832_cmds(regs, dev_addr=0x2a, mask=0x01):
+    cmds = []
+
+    print(f"Reading register list file '{regs}'...")
+
+    with open(regs, "r") as f:
+        for line in f:
+            line = line.strip()
+            if not line or line == "Address,Data":
+                continue
+            if line[0] == '#':
+                cmds.append(f"// {line[1:].strip()}")
+
+                if line.startswith("# Delay"):
+                    cmds.append("cmd_delay(10); // delay 300 ms")
+
+                continue
+
+            d = line.split(",")
+            addr = int(d[0], 0)
+            addr_msb = (addr >> 8) & 0xff
+            addr_lsb = addr & 0xff
+            data = int(d[1], 0)
+
+            cmds.append(f"cmd_start(7'h{dev_addr:02x});")
+            cmds.append(f"cmd_wr(8'h{mask:02x}); // SPI transfer, CS mask {mask:#03x}")
+            cmds.append(f"cmd_wr(8'h{addr_msb:02x}); // address {addr:#06x}")
+            cmds.append(f"cmd_wr(8'h{addr_lsb:02x});")
+            cmds.append(f"cmd_wr(8'h{data:02x}); // write {data:#04x}")
+
+    return cmds
+
+
+def lmx2594_cmds(regs, dev_addr=0x2a, mask=0x01):
+    cmds = []
+
+    print(f"Reading register list file '{regs}'...")
+
+    with open(regs, "r") as f:
+        for line in f:
+            line = line.strip()
+            if not line or line == "Address,Data":
+                continue
+            if line[0] == '#':
+                cmds.append(f"// {line[1:].strip()}")
+
+                if line.startswith("# Delay"):
+                    cmds.append("cmd_delay(10); // delay 300 ms")
+
+                continue
+
+            d = line.split(",")
+            addr = int(d[0], 0)
+            data = int(d[1], 0)
+            data_msb = (data >> 8) & 0xff
+            data_lsb = data & 0xff
+
+            cmds.append(f"cmd_start(7'h{dev_addr:02x});")
+            cmds.append(f"cmd_wr(8'h{mask:02x}); // SPI transfer, CS mask {mask:#03x}")
+            cmds.append(f"cmd_wr(8'h{addr:02x}); // address {addr:#04x}")
+            cmds.append(f"cmd_wr(8'h{data_msb:02x}); // write {data:#06x}")
+            cmds.append(f"cmd_wr(8'h{data_lsb:02x});")
+
+    return cmds
+
+
+def mux_cmds(val, dev_addr):
+    cmds = []
+    cmds.append(f"cmd_start(7'h{dev_addr:02x});")
+    cmds.append(f"cmd_wr(8'h{val:02x});")
+    cmds.append("cmd_stop(); // I2C stop")
+    return cmds
+
+
+def main():
+    cmds = []
+
+    cmds.append("// Initial delay")
+    cmds.append("cmd_delay(6); // delay 30 ms")
+
+    # Si5341 on HTG-ZRF8-EM
+    cmds.append("// Set mux to select U48 Si5341 on HTG-ZRF8-EM")
+    cmds.extend(mux_cmds(0x10, 0x71))
+
+    cmds.extend(si5341_cmds("HTG-ZRF8-EM-161-ZRF8EM01-Registers.txt", 0x74))
+
+    # PLLs for RF data converters
+    cmds.append("// Set mux to select I2C-SPI bridge on HTG-ZRF8-EM")
+    cmds.extend(mux_cmds(0x0a, 0x71))
+
+    cmds.append("// Configure I2C-SPI bridge")
+    cmds.append("cmd_start(7'h2a);")
+    cmds.append("cmd_wr(8'hf0);")
+    cmds.append("cmd_wr(8'h00);")
+    cmds.append("cmd_start(7'h2a);")
+    cmds.append("cmd_wr(8'hf6);")
+    cmds.append("cmd_wr(8'h00);")
+
+    cmds.extend(lmk04832_cmds("LMK04832_EM_250.txt", 0x2a, 0x08))
+    cmds.extend(lmx2594_cmds("LMX2594_250_1000.txt", 0x2a, 0x07))
+
+    cmds.append("// Clear I2C-SPI bridge interrupt")
+    cmds.append("cmd_start(7'h2a);")
+    cmds.append("cmd_wr(8'hf1);")
+
+    # cmds.append("// Delay for PLL to lock")
+    # cmds.append("cmd_delay(10); // delay 300 ms")
+
+    generate(cmds, "pll_i2c_init_em")
+
+    cmds = []
+
+    cmds.append("// Initial delay")
+    cmds.append("cmd_delay(6); // delay 30 ms")
+
+    # Si5341 on HTG-ZRF8-R2
+    cmds.append("// Set mux to select U19 Si5341 on HTG-ZRF8-R2")
+    cmds.extend(mux_cmds(0x10, 0x71))
+
+    cmds.extend(si5341_cmds("HTG-ZRF8-R2-161-ZRF8R201-Registers.txt", 0x74))
+
+    # PLLs for RF data converters
+    cmds.append("// Set mux to select I2C-SPI bridge on HTG-ZRF8-R2")
+    cmds.extend(mux_cmds(0x0b, 0x71))
+
+    cmds.append("// Configure I2C-SPI bridge for LMK04832")
+    cmds.append("cmd_start(7'h2e);")
+    cmds.append("cmd_wr(8'hf0);")
+    cmds.append("cmd_wr(8'h00);")
+    cmds.append("cmd_start(7'h2e);")
+    cmds.append("cmd_wr(8'hf6);")
+    cmds.append("cmd_wr(8'h00);")
+
+    cmds.append("// Configure I2C-SPI bridge for LMX2594")
+    cmds.append("cmd_start(7'h2a);")
+    cmds.append("cmd_wr(8'hf0);")
+    cmds.append("cmd_wr(8'h00);")
+    cmds.append("cmd_start(7'h2a);")
+    cmds.append("cmd_wr(8'hf6);")
+    cmds.append("cmd_wr(8'h00);")
+
+    cmds.extend(lmk04832_cmds("LMK04832_R2_250.txt", 0x2e, 0x01))
+    cmds.extend(lmx2594_cmds("LMX2594_250_1000.txt", 0x2a, 0x07))
+
+    cmds.append("// Clear I2C-SPI bridge interrupt for LMK04832")
+    cmds.append("cmd_start(7'h2e);")
+    cmds.append("cmd_wr(8'hf1);")
+    cmds.append("// Clear I2C-SPI bridge interrupt for LMX2594")
+    cmds.append("cmd_start(7'h2a);")
+    cmds.append("cmd_wr(8'hf1);")
+
+    # cmds.append("// Delay for PLL to lock")
+    # cmds.append("cmd_delay(10); // delay 300 ms")
+
+    generate(cmds, "pll_i2c_init_r2")
+
+
+def generate(cmds=None, name=None, output=None):
+    if cmds is None:
+        raise Exception("Command list is required")
+
+    if name is None:
+        name = "pll_i2c_init"
+
+    if output is None:
+        output = name + ".sv"
+
+    print(f"Generating PLL I2C init module {name}...")
+
+    cmds = cmds.copy()
+    cmds.append("cmd_halt(); // end")
+
+    cmd_str = ""
+    cmd_count = 0
+
+    for cmd in cmds:
+        if cmd.startswith('//'):
+            cmd_str += f"    {cmd}\n"
+        else:
+            cmd_str += f"    init_data[{cmd_count}] = {cmd}\n"
+            cmd_count += 1
+
+    t = Template(u"""// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2015-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * {{name}}
+ */
+module {{name}} #
+(
+    parameter logic SIM_SPEEDUP = 1'b0
+)
+(
+    input  wire logic  clk,
+    input  wire logic  rst,
+
+    /*
+     * I2C master interface
+     */
+    taxi_axis_if.src   m_axis_cmd,
+    taxi_axis_if.src   m_axis_tx,
+
+    /*
+     * Status
+     */
+    output wire logic  busy,
+
+    /*
+     * Configuration
+     */
+    input  wire logic  start
+);
+
+/*
+
+Generic module for I2C bus initialization.  Good for use when multiple devices
+on an I2C bus must be initialized on system start without intervention of a
+general-purpose processor.
+
+Copy this file and change init_data and INIT_DATA_LEN as needed.
+
+This module can be used in two modes: simple device initialization, or multiple
+device initialization.  In multiple device mode, the same initialization sequence
+can be performed on multiple different device addresses.
+
+To use single device mode, only use the start write to address and write data commands.
+The module will generate the I2C commands in sequential order.  Terminate the list
+with a 0 entry.
+
+To use the multiple device mode, use the start data and start address block commands
+to set up lists of initialization data and device addresses.  The module enters
+multiple device mode upon seeing a start data block command.  The module stores the
+offset of the start of the data block and then skips ahead until it reaches a start
+address block command.  The module will store the offset to the address block and
+read the first address in the block.  Then it will jump back to the data block
+and execute it, substituting the stored address for each current address write
+command.  Upon reaching the start address block command, the module will read out the
+next address and start again at the top of the data block.  If the module encounters
+a start data block command while looking for an address, then it will store a new data
+offset and then look for a start address block command.  Terminate the list with a 0
+entry.  Normal address commands will operate normally inside a data block.
+
+Commands:
+
+00 0000000 : stop
+00 0000001 : exit multiple device mode
+00 0000011 : start write to current address
+00 0001000 : start address block
+00 0001001 : start data block
+00 001dddd : delay 2**(16+d) cycles
+00 1000001 : send I2C stop
+01 aaaaaaa : start write to address
+1 dddddddd : write 8-bit data
+
+Examples
+
+write 0x11223344 to register 0x0004 on device at 0x50
+
+01 1010000  start write to 0x50
+1 00000000  write address 0x0004
+1 00000100
+1 00010001  write data 0x11223344
+1 00100010
+1 00110011
+1 01000100
+0 00000000  stop
+
+write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53
+
+00 0001001  start data block
+00 0000011  start write to current address
+1 00000000  write address 0x0004
+1 00000100
+1 00010001  write data 0x11223344
+1 00100010
+1 00110011
+1 01000100
+00 0001000  start address block
+01 1010000  address 0x50
+01 1010001  address 0x51
+01 1010010  address 0x52
+01 1010011  address 0x53
+00 0000001  exit multi-dev mode
+00 0000000  stop
+
+*/
+
+// check configuration
+if (m_axis_cmd.DATA_W < 12)
+    $fatal(0, "Command interface width must be at least 12 bits (instance %m)");
+
+if (m_axis_tx.DATA_W != 8)
+    $fatal(0, "Data interface width must be 8 bits (instance %m)");
+
+function [8:0] cmd_start(input [6:0] addr);
+    cmd_start = {2'b01, addr};
+endfunction
+
+function [8:0] cmd_wr(input [7:0] data);
+    cmd_wr = {1'b1, data};
+endfunction
+
+function [8:0] cmd_stop();
+    cmd_stop = {2'b00, 7'b1000001};
+endfunction
+
+function [8:0] cmd_delay(input [3:0] d);
+    cmd_delay = {2'b00, 3'b001, d};
+endfunction
+
+function [8:0] cmd_halt();
+    cmd_halt = 9'd0;
+endfunction
+
+function [8:0] blk_start_data();
+    blk_start_data = {2'b00, 7'b0001001};
+endfunction
+
+function [8:0] blk_start_addr();
+    blk_start_addr = {2'b00, 7'b0001000};
+endfunction
+
+function [8:0] cmd_start_cur();
+    cmd_start_cur = {2'b00, 7'b0000011};
+endfunction
+
+function [8:0] cmd_exit();
+    cmd_exit = {2'b00, 7'b0000001};
+endfunction
+
+// init_data ROM
+localparam INIT_DATA_LEN = {{cmd_count}};
+
+reg [8:0] init_data [INIT_DATA_LEN-1:0];
+
+initial begin
+{{cmd_str-}}
+end
+
+localparam [2:0]
+    STATE_IDLE = 3'd0,
+    STATE_RUN = 3'd1,
+    STATE_TABLE_1 = 3'd2,
+    STATE_TABLE_2 = 3'd3,
+    STATE_TABLE_3 = 3'd4;
+
+logic [2:0] state_reg = STATE_IDLE, state_next;
+
+localparam AW = $clog2(INIT_DATA_LEN);
+
+logic [8:0] init_data_reg = '0;
+
+logic [AW-1:0] address_reg = '0, address_next;
+logic [AW-1:0] address_ptr_reg = '0, address_ptr_next;
+logic [AW-1:0] data_ptr_reg = '0, data_ptr_next;
+
+logic [6:0] cur_address_reg = '0, cur_address_next;
+
+logic [31:0] delay_counter_reg = '0, delay_counter_next;
+
+logic [6:0] m_axis_cmd_address_reg = '0, m_axis_cmd_address_next;
+logic m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next;
+logic m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next;
+logic m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next;
+logic m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next;
+
+logic [7:0] m_axis_tx_tdata_reg = '0, m_axis_tx_tdata_next;
+logic m_axis_tx_tvalid_reg = 1'b0, m_axis_tx_tvalid_next;
+
+logic start_flag_reg = 1'b0, start_flag_next;
+
+logic busy_reg = 1'b0;
+
+assign m_axis_cmd.tdata[6:0] = m_axis_cmd_address_reg;
+assign m_axis_cmd.tdata[7]   = m_axis_cmd_start_reg;
+assign m_axis_cmd.tdata[8]   = 1'b0; // read
+assign m_axis_cmd.tdata[9]   = m_axis_cmd_write_reg;
+assign m_axis_cmd.tdata[10]  = 1'b0; // write multi
+assign m_axis_cmd.tdata[11]  = m_axis_cmd_stop_reg;
+assign m_axis_cmd.tvalid = m_axis_cmd_valid_reg;
+assign m_axis_cmd.tlast = 1'b1;
+assign m_axis_cmd.tid = '0;
+assign m_axis_cmd.tdest = '0;
+assign m_axis_cmd.tuser = '0;
+
+assign m_axis_tx.tdata = m_axis_tx_tdata_reg;
+assign m_axis_tx.tvalid = m_axis_tx_tvalid_reg;
+assign m_axis_tx.tlast = 1'b1;
+assign m_axis_tx.tid = '0;
+assign m_axis_tx.tdest = '0;
+assign m_axis_tx.tuser = '0;
+
+assign busy = busy_reg;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    address_next = address_reg;
+    address_ptr_next = address_ptr_reg;
+    data_ptr_next = data_ptr_reg;
+
+    cur_address_next = cur_address_reg;
+
+    delay_counter_next = delay_counter_reg;
+
+    m_axis_cmd_address_next = m_axis_cmd_address_reg;
+    m_axis_cmd_start_next = m_axis_cmd_start_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
+    m_axis_cmd_write_next = m_axis_cmd_write_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
+    m_axis_cmd_stop_next = m_axis_cmd_stop_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready);
+    m_axis_cmd_valid_next = m_axis_cmd_valid_reg && !m_axis_cmd.tready;
+
+    m_axis_tx_tdata_next = m_axis_tx_tdata_reg;
+    m_axis_tx_tvalid_next = m_axis_tx_tvalid_reg && !m_axis_tx.tready;
+
+    start_flag_next = start_flag_reg;
+
+    if (m_axis_cmd.tvalid || m_axis_tx.tvalid) begin
+        // wait for output registers to clear
+        state_next = state_reg;
+    end else if (delay_counter_reg != 0) begin
+        // delay
+        delay_counter_next = delay_counter_reg - 1;
+        state_next = state_reg;
+    end else begin
+        case (state_reg)
+            STATE_IDLE: begin
+                // wait for start signal
+                if (!start_flag_reg && start) begin
+                    address_next = '0;
+                    start_flag_next = 1'b1;
+                    state_next = STATE_RUN;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end
+            STATE_RUN: begin
+                // process commands
+                if (init_data_reg[8] == 1'b1) begin
+                    // write data
+                    m_axis_cmd_write_next = 1'b1;
+                    m_axis_cmd_stop_next = 1'b0;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    m_axis_tx_tdata_next = init_data_reg[7:0];
+                    m_axis_tx_tvalid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg[8:7] == 2'b01) begin
+                    // write address
+                    m_axis_cmd_address_next = init_data_reg[6:0];
+                    m_axis_cmd_start_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg[8:4] == 5'b00001) begin
+                    // delay
+                    if (SIM_SPEEDUP) begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]);
+                    end else begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]+16);
+                    end
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'b001000001) begin
+                    // send stop
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end
+            end
+            STATE_TABLE_1: begin
+                // find address table start
+                if (init_data_reg == 9'b000001000) begin
+                    // address table start
+                    address_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_2;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 1) begin
+                    // exit mode
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end
+            end
+            STATE_TABLE_2: begin
+                // find next address
+                if (init_data_reg[8:7] == 2'b01) begin
+                    // write address command
+                    // store address and move to data table
+                    cur_address_next = init_data_reg[6:0];
+                    address_ptr_next = address_reg + 1;
+                    address_next = data_ptr_reg;
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 9'd1) begin
+                    // exit mode
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_2;
+                end
+            end
+            STATE_TABLE_3: begin
+                // process data table with selected address
+                if (init_data_reg[8] == 1'b1) begin
+                    // write data
+                    m_axis_cmd_write_next = 1'b1;
+                    m_axis_cmd_stop_next = 1'b0;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    m_axis_tx_tdata_next = init_data_reg[7:0];
+                    m_axis_tx_tvalid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg[8:7] == 2'b01) begin
+                    // write address
+                    m_axis_cmd_address_next = init_data_reg[6:0];
+                    m_axis_cmd_start_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b000000011) begin
+                    // write current address
+                    m_axis_cmd_address_next = cur_address_reg;
+                    m_axis_cmd_start_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg[8:4] == 5'b00001) begin
+                    // delay
+                    if (SIM_SPEEDUP) begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]);
+                    end else begin
+                        delay_counter_next = 32'd1 << (init_data_reg[3:0]+16);
+                    end
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b001000001) begin
+                    // send stop
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    address_next = address_reg + 1;
+
+                    state_next = STATE_TABLE_3;
+                end else if (init_data_reg == 9'b000001001) begin
+                    // data table start
+                    data_ptr_next = address_reg + 1;
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_1;
+                end else if (init_data_reg == 9'b000001000) begin
+                    // address table start
+                    address_next = address_ptr_reg;
+                    state_next = STATE_TABLE_2;
+                end else if (init_data_reg == 9'd1) begin
+                    // exit mode
+                    address_next = address_reg + 1;
+                    state_next = STATE_RUN;
+                end else if (init_data_reg == 9'd0) begin
+                    // stop
+                    m_axis_cmd_start_next = 1'b0;
+                    m_axis_cmd_write_next = 1'b0;
+                    m_axis_cmd_stop_next = 1'b1;
+                    m_axis_cmd_valid_next = 1'b1;
+
+                    state_next = STATE_IDLE;
+                end else begin
+                    // invalid command, skip
+                    address_next = address_reg + 1;
+                    state_next = STATE_TABLE_3;
+                end
+            end
+            default: begin
+                // invalid state
+                state_next = STATE_IDLE;
+            end
+        endcase
+    end
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    // read init_data ROM
+    init_data_reg <= init_data[address_next];
+
+    address_reg <= address_next;
+    address_ptr_reg <= address_ptr_next;
+    data_ptr_reg <= data_ptr_next;
+
+    cur_address_reg <= cur_address_next;
+
+    delay_counter_reg <= delay_counter_next;
+
+    m_axis_cmd_address_reg <= m_axis_cmd_address_next;
+    m_axis_cmd_start_reg <= m_axis_cmd_start_next;
+    m_axis_cmd_write_reg <= m_axis_cmd_write_next;
+    m_axis_cmd_stop_reg <= m_axis_cmd_stop_next;
+    m_axis_cmd_valid_reg <= m_axis_cmd_valid_next;
+
+    m_axis_tx_tdata_reg <= m_axis_tx_tdata_next;
+    m_axis_tx_tvalid_reg <= m_axis_tx_tvalid_next;
+
+    start_flag_reg <= start && start_flag_next;
+
+    busy_reg <= (state_reg != STATE_IDLE);
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        init_data_reg <= '0;
+
+        address_reg <= '0;
+        address_ptr_reg <= '0;
+        data_ptr_reg <= '0;
+
+        cur_address_reg <= '0;
+
+        delay_counter_reg <= '0;
+
+        m_axis_cmd_valid_reg <= 1'b0;
+
+        m_axis_tx_tvalid_reg <= 1'b0;
+
+        start_flag_reg <= 1'b0;
+
+        busy_reg <= 1'b0;
+    end
+end
+
+endmodule
+
+`resetall
+""")
+
+    print(f"Writing file '{output}'...")
+
+    with open(output, 'w') as f:
+        f.write(t.render(
+            cmd_str=cmd_str,
+            cmd_count=cmd_count,
+            name=name
+        ))
+        f.flush()
+
+    print("Done")
+
+
+if __name__ == "__main__":
+    main()

src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv

@@ -0,0 +1,610 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA core logic
+ */
+module fpga_core #
+(
+    parameter logic SIM = 1'b0,
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "zynquplusRFSOC",
+    parameter PORT_CNT = 2,
+    parameter GTY_QUAD_CNT = PORT_CNT,
+    parameter GTY_CNT = GTY_QUAD_CNT*4,
+    parameter GTY_CLK_CNT = GTY_QUAD_CNT,
+    parameter ADC_CNT = 8,
+    parameter DAC_CNT = ADC_CNT
+)
+(
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    input  wire logic                    clk_125mhz,
+    input  wire logic                    rst_125mhz,
+    input  wire logic                    fpga_refclk,
+    input  wire logic                    fpga_sysref,
+
+    /*
+     * GPIO
+     */
+    input  wire logic [3:0]              sw,
+    output wire logic [3:0]              led,
+    output wire logic [7:0]              gpio,
+
+    /*
+     * I2C for board management
+     */
+    input  wire logic                    i2c_scl_i,
+    output wire logic                    i2c_scl_o,
+    input  wire logic                    i2c_sda_i,
+    output wire logic                    i2c_sda_o,
+
+    /*
+     * UART: 921600 bps, 8N1
+     */
+    output wire logic                    uart_rxd,
+    input  wire logic                    uart_txd,
+    input  wire logic                    uart_rts,
+    output wire logic                    uart_cts,
+    output wire logic                    uart_rst_n,
+    input  wire logic                    uart_suspend_n,
+
+    /*
+     * Ethernet: QSFP28
+     */
+    output wire logic [GTY_CNT-1:0]      eth_gty_tx_p,
+    output wire logic [GTY_CNT-1:0]      eth_gty_tx_n,
+    input  wire logic [GTY_CNT-1:0]      eth_gty_rx_p,
+    input  wire logic [GTY_CNT-1:0]      eth_gty_rx_n,
+    input  wire logic [GTY_CLK_CNT-1:0]  eth_gty_mgt_refclk_p,
+    input  wire logic [GTY_CLK_CNT-1:0]  eth_gty_mgt_refclk_n,
+    output wire logic [GTY_CLK_CNT-1:0]  eth_gty_mgt_refclk_out,
+
+    output wire logic [PORT_CNT-1:0]     eth_port_resetl,
+    input  wire logic [PORT_CNT-1:0]     eth_port_modprsl,
+    input  wire logic [PORT_CNT-1:0]     eth_port_intl,
+
+    /*
+     * RFDC
+     */
+    input  wire logic                    axil_rfdc_clk,
+    input  wire logic                    axil_rfdc_rst,
+    taxi_axil_if.wr_mst                  m_axil_rfdc_wr,
+    taxi_axil_if.rd_mst                  m_axil_rfdc_rd,
+
+    input  wire logic                    axis_rfdc_clk,
+    input  wire logic                    axis_rfdc_rst,
+    taxi_axis_if.snk                     s_axis_adc[ADC_CNT],
+    taxi_axis_if.src                     m_axis_dac[DAC_CNT]
+);
+
+// XFCP
+taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
+
+assign uart_cts = 1'b1;
+assign uart_rst_n = 1'b1;
+
+taxi_xfcp_if_uart #(
+    .TX_FIFO_DEPTH(512),
+    .RX_FIFO_DEPTH(512)
+)
+xfcp_if_uart_inst (
+    .clk(clk_125mhz),
+    .rst(rst_125mhz),
+
+    /*
+     * UART interface
+     */
+    .uart_rxd(uart_txd),
+    .uart_txd(uart_rxd),
+
+    /*
+     * XFCP downstream interface
+     */
+    .xfcp_dsp_ds(xfcp_ds),
+    .xfcp_dsp_us(xfcp_us),
+
+    /*
+     * Configuration
+     */
+    .prescale(16'(125000000/921600))
+);
+
+taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[3](), xfcp_sw_us[3]();
+
+taxi_xfcp_switch #(
+    .XFCP_ID_STR("HTG-ZRF8"),
+    .XFCP_EXT_ID(0),
+    .XFCP_EXT_ID_STR("Taxi example"),
+    .PORTS($size(xfcp_sw_us))
+)
+xfcp_sw_inst (
+    .clk(clk_125mhz),
+    .rst(rst_125mhz),
+
+    /*
+     * XFCP upstream port
+     */
+    .xfcp_usp_ds(xfcp_ds),
+    .xfcp_usp_us(xfcp_us),
+
+    /*
+     * XFCP downstream ports
+     */
+    .xfcp_dsp_ds(xfcp_sw_ds),
+    .xfcp_dsp_us(xfcp_sw_us)
+);
+
+// Statistics
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat();
+
+taxi_xfcp_mod_stats #(
+    .XFCP_ID_STR("Statistics"),
+    .XFCP_EXT_ID(0),
+    .XFCP_EXT_ID_STR(""),
+    .STAT_COUNT_W(64),
+    .STAT_PIPELINE(2)
+)
+xfcp_stats_inst (
+    .clk(clk_125mhz),
+    .rst(rst_125mhz),
+
+    /*
+     * XFCP upstream port
+     */
+    .xfcp_usp_ds(xfcp_sw_ds[0]),
+    .xfcp_usp_us(xfcp_sw_us[0]),
+
+    /*
+     * Statistics increment input
+     */
+    .s_axis_stat(axis_stat)
+);
+
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(axis_stat.ID_W)) axis_eth_stat[GTY_QUAD_CNT]();
+
+taxi_axis_arb_mux #(
+    .S_COUNT($size(axis_eth_stat)),
+    .UPDATE_TID(1'b0),
+    .ARB_ROUND_ROBIN(1'b1),
+    .ARB_LSB_HIGH_PRIO(1'b0)
+)
+stat_mux_inst (
+    .clk(clk_125mhz),
+    .rst(rst_125mhz),
+
+    /*
+     * AXI4-Stream inputs (sink)
+     */
+    .s_axis(axis_eth_stat),
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    .m_axis(axis_stat)
+);
+
+// I2C
+taxi_xfcp_mod_i2c_master #(
+    .DEFAULT_PRESCALE(16'(125000000/400000/4))
+)
+xfcp_mod_i2c_inst (
+    .clk(clk_125mhz),
+    .rst(rst_125mhz),
+
+    /*
+     * XFCP upstream port
+     */
+    .xfcp_usp_ds(xfcp_sw_ds[1]),
+    .xfcp_usp_us(xfcp_sw_us[1]),
+
+    /*
+     * I2C interface
+     */
+    .i2c_scl_i(i2c_scl_i),
+    .i2c_scl_o(i2c_scl_o),
+    .i2c_sda_i(i2c_sda_i),
+    .i2c_sda_o(i2c_sda_o)
+);
+
+// RFDC control
+taxi_xfcp_mod_axil #(
+    .XFCP_ID_STR("RFDC"),
+    .COUNT_SIZE(16)
+)
+xfcp_mod_axil_inst (
+    .clk(clk_125mhz),
+    .rst(rst_125mhz),
+
+    /*
+     * XFCP upstream port
+     */
+    .xfcp_usp_ds(xfcp_sw_ds[2]),
+    .xfcp_usp_us(xfcp_sw_us[2]),
+
+    /*
+     * AXI lite master interface
+     */
+    .m_axil_wr(m_axil_rfdc_wr),
+    .m_axil_rd(m_axil_rfdc_rd)
+);
+
+// Ethernet
+wire eth_reset = SIM ? 1'b0 : rst_125mhz;
+assign eth_port_resetl = {PORT_CNT{~eth_reset}};
+
+wire [GTY_CNT-1:0] eth_gty_tx_clk;
+wire [GTY_CNT-1:0] eth_gty_tx_rst;
+taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
+
+wire [GTY_CNT-1:0] eth_gty_rx_clk;
+wire [GTY_CNT-1:0] eth_gty_rx_rst;
+taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
+
+wire [GTY_CNT-1:0] eth_gty_rx_status;
+
+wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
+
+wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk;
+wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_bufg;
+
+wire [GTY_CLK_CNT-1:0] eth_gty_rst;
+
+for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
+
+    wire eth_gty_mgt_refclk_int;
+
+    if (SIM) begin
+
+        assign eth_gty_mgt_refclk[n] = eth_gty_mgt_refclk_p[n];
+        assign eth_gty_mgt_refclk_int = eth_gty_mgt_refclk_p[n];
+        assign eth_gty_mgt_refclk_bufg[n] = eth_gty_mgt_refclk_int;
+
+    end else begin
+
+        IBUFDS_GTE4 ibufds_gte4_eth_gty_mgt_refclk_inst (
+            .I     (eth_gty_mgt_refclk_p[n]),
+            .IB    (eth_gty_mgt_refclk_n[n]),
+            .CEB   (1'b0),
+            .O     (eth_gty_mgt_refclk[n]),
+            .ODIV2 (eth_gty_mgt_refclk_int)
+        );
+
+        BUFG_GT bufg_gt_eth_gty_mgt_refclk_inst (
+            .CE      (&eth_gty_gtpowergood),
+            .CEMASK  (1'b1),
+            .CLR     (1'b0),
+            .CLRMASK (1'b1),
+            .DIV     (3'd0),
+            .I       (eth_gty_mgt_refclk_int),
+            .O       (eth_gty_mgt_refclk_bufg[n])
+        );
+
+    end
+
+    assign eth_gty_mgt_refclk_out[n] = eth_gty_mgt_refclk_bufg[n];
+
+    taxi_sync_reset #(
+        .N(4)
+    )
+    qsfp_sync_reset_inst (
+        .clk(eth_gty_mgt_refclk_bufg[n]),
+        .rst(rst_125mhz || eth_reset),
+        .out(eth_gty_rst[n])
+    );
+
+end
+
+localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3",  "QSFP1.4"};
+localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3",  "QSFP2.4"};
+
+for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
+
+    localparam CLK = n;
+    localparam CNT = 4;
+
+    taxi_eth_mac_25g_us #(
+        .SIM(SIM),
+        .VENDOR(VENDOR),
+        .FAMILY(FAMILY),
+
+        .CNT(CNT),
+
+        // GT config
+        .CFG_LOW_LATENCY(1),
+
+        // GT type
+        .GT_TYPE("GTY"),
+
+        // PHY parameters
+        .PADDING_EN(1'b1),
+        .DIC_EN(1'b1),
+        .MIN_FRAME_LEN(64),
+        .PTP_TS_EN(1'b0),
+        .PTP_TS_FMT_TOD(1'b1),
+        .PTP_TS_W(96),
+        .PRBS31_EN(1'b0),
+        .TX_SERDES_PIPELINE(1),
+        .RX_SERDES_PIPELINE(1),
+        .COUNT_125US(125000/6.4),
+        .STAT_EN(1),
+        .STAT_TX_LEVEL(1),
+        .STAT_RX_LEVEL(1),
+        .STAT_ID_BASE(n*CNT*(16+16)),
+        .STAT_UPDATE_PERIOD(1024),
+        .STAT_STR_EN(1),
+        .STAT_PREFIX_STR(
+            n == 0 ? STAT_PREFIX_STR_QSFP1 :
+            STAT_PREFIX_STR_QSFP2
+        )
+    )
+    mac_inst (
+        .xcvr_ctrl_clk(clk_125mhz),
+        .xcvr_ctrl_rst(eth_gty_rst[CLK]),
+
+        /*
+         * Common
+         */
+        .xcvr_gtpowergood_out(eth_gty_gtpowergood[n]),
+        .xcvr_gtrefclk00_in(eth_gty_mgt_refclk[CLK]),
+        .xcvr_qpll0pd_in(1'b0),
+        .xcvr_qpll0reset_in(1'b0),
+        .xcvr_qpll0pcierate_in(3'd0),
+        .xcvr_qpll0lock_out(),
+        .xcvr_qpll0clk_out(),
+        .xcvr_qpll0refclk_out(),
+        .xcvr_gtrefclk01_in(eth_gty_mgt_refclk[CLK]),
+        .xcvr_qpll1pd_in(1'b0),
+        .xcvr_qpll1reset_in(1'b0),
+        .xcvr_qpll1pcierate_in(3'd0),
+        .xcvr_qpll1lock_out(),
+        .xcvr_qpll1clk_out(),
+        .xcvr_qpll1refclk_out(),
+
+        /*
+         * Serial data
+         */
+        .xcvr_txp(eth_gty_tx_p[n*CNT +: CNT]),
+        .xcvr_txn(eth_gty_tx_n[n*CNT +: CNT]),
+        .xcvr_rxp(eth_gty_rx_p[n*CNT +: CNT]),
+        .xcvr_rxn(eth_gty_rx_n[n*CNT +: CNT]),
+
+        /*
+         * MAC clocks
+         */
+        .rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
+        .rx_rst_in('0),
+        .rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
+        .tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
+        .tx_rst_in('0),
+        .tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
+        .ptp_sample_clk('0),
+
+        /*
+         * Transmit interface (AXI stream)
+         */
+        .s_axis_tx(eth_gty_axis_tx[n*CNT +: CNT]),
+        .m_axis_tx_cpl(eth_gty_axis_tx_cpl[n*CNT +: CNT]),
+
+        /*
+         * Receive interface (AXI stream)
+         */
+        .m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]),
+
+        /*
+         * PTP clock
+         */
+        .tx_ptp_ts('{CNT{'0}}),
+        .tx_ptp_ts_step('0),
+        .rx_ptp_ts('{CNT{'0}}),
+        .rx_ptp_ts_step('0),
+
+        /*
+         * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
+         */
+        .tx_lfc_req('0),
+        .tx_lfc_resend('0),
+        .rx_lfc_en('0),
+        .rx_lfc_req(),
+        .rx_lfc_ack('0),
+
+        /*
+         * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
+         */
+        .tx_pfc_req('{CNT{'0}}),
+        .tx_pfc_resend('0),
+        .rx_pfc_en('{CNT{'0}}),
+        .rx_pfc_req(),
+        .rx_pfc_ack('{CNT{'0}}),
+
+        /*
+         * Pause interface
+         */
+        .tx_lfc_pause_en('0),
+        .tx_pause_req('0),
+        .tx_pause_ack(),
+
+        /*
+         * Statistics
+         */
+        .stat_clk(clk_125mhz),
+        .stat_rst(rst_125mhz),
+        .m_axis_stat(axis_eth_stat[n]),
+
+        /*
+         * Status
+         */
+        .tx_start_packet(),
+        .stat_tx_byte(),
+        .stat_tx_pkt_len(),
+        .stat_tx_pkt_ucast(),
+        .stat_tx_pkt_mcast(),
+        .stat_tx_pkt_bcast(),
+        .stat_tx_pkt_vlan(),
+        .stat_tx_pkt_good(),
+        .stat_tx_pkt_bad(),
+        .stat_tx_err_oversize(),
+        .stat_tx_err_user(),
+        .stat_tx_err_underflow(),
+        .rx_start_packet(),
+        .rx_error_count(),
+        .rx_block_lock(),
+        .rx_high_ber(),
+        .rx_status(eth_gty_rx_status[n*CNT +: CNT]),
+        .stat_rx_byte(),
+        .stat_rx_pkt_len(),
+        .stat_rx_pkt_fragment(),
+        .stat_rx_pkt_jabber(),
+        .stat_rx_pkt_ucast(),
+        .stat_rx_pkt_mcast(),
+        .stat_rx_pkt_bcast(),
+        .stat_rx_pkt_vlan(),
+        .stat_rx_pkt_good(),
+        .stat_rx_pkt_bad(),
+        .stat_rx_err_oversize(),
+        .stat_rx_err_bad_fcs(),
+        .stat_rx_err_bad_block(),
+        .stat_rx_err_framing(),
+        .stat_rx_err_preamble(),
+        .stat_rx_fifo_drop('0),
+        .stat_tx_mcf(),
+        .stat_rx_mcf(),
+        .stat_tx_lfc_pkt(),
+        .stat_tx_lfc_xon(),
+        .stat_tx_lfc_xoff(),
+        .stat_tx_lfc_paused(),
+        .stat_tx_pfc_pkt(),
+        .stat_tx_pfc_xon(),
+        .stat_tx_pfc_xoff(),
+        .stat_tx_pfc_paused(),
+        .stat_rx_lfc_pkt(),
+        .stat_rx_lfc_xon(),
+        .stat_rx_lfc_xoff(),
+        .stat_rx_lfc_paused(),
+        .stat_rx_pfc_pkt(),
+        .stat_rx_pfc_xon(),
+        .stat_rx_pfc_xoff(),
+        .stat_rx_pfc_paused(),
+
+        /*
+         * Configuration
+         */
+        .cfg_tx_max_pkt_len('{CNT{16'd9218}}),
+        .cfg_tx_ifg('{CNT{8'd12}}),
+        .cfg_tx_enable('1),
+        .cfg_rx_max_pkt_len('{CNT{16'd9218}}),
+        .cfg_rx_enable('1),
+        .cfg_tx_prbs31_enable('0),
+        .cfg_rx_prbs31_enable('0),
+        .cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
+        .cfg_mcf_rx_check_eth_dst_mcast('1),
+        .cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
+        .cfg_mcf_rx_check_eth_dst_ucast('0),
+        .cfg_mcf_rx_eth_src('{CNT{48'd0}}),
+        .cfg_mcf_rx_check_eth_src('0),
+        .cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
+        .cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
+        .cfg_mcf_rx_check_opcode_lfc('1),
+        .cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
+        .cfg_mcf_rx_check_opcode_pfc('1),
+        .cfg_mcf_rx_forward('0),
+        .cfg_mcf_rx_enable('0),
+        .cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
+        .cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
+        .cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
+        .cfg_tx_lfc_opcode('{CNT{16'h0001}}),
+        .cfg_tx_lfc_en('0),
+        .cfg_tx_lfc_quanta('{CNT{16'hffff}}),
+        .cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
+        .cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
+        .cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
+        .cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
+        .cfg_tx_pfc_opcode('{CNT{16'h0101}}),
+        .cfg_tx_pfc_en('0),
+        .cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
+        .cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
+        .cfg_rx_lfc_opcode('{CNT{16'h0001}}),
+        .cfg_rx_lfc_en('0),
+        .cfg_rx_pfc_opcode('{CNT{16'h0101}}),
+        .cfg_rx_pfc_en('0)
+    );
+
+end
+
+for (genvar n = 0; n < GTY_CNT; n = n + 1) begin : gty_ch
+
+    taxi_axis_async_fifo #(
+        .DEPTH(16384),
+        .RAM_PIPELINE(2),
+        .FRAME_FIFO(1),
+        .USER_BAD_FRAME_VALUE(1'b1),
+        .USER_BAD_FRAME_MASK(1'b1),
+        .DROP_OVERSIZE_FRAME(1),
+        .DROP_BAD_FRAME(1),
+        .DROP_WHEN_FULL(1)
+    )
+    ch_fifo (
+        /*
+         * AXI4-Stream input (sink)
+         */
+        .s_clk(eth_gty_rx_clk[n]),
+        .s_rst(eth_gty_rx_rst[n]),
+        .s_axis(eth_gty_axis_rx[n]),
+
+        /*
+         * AXI4-Stream output (source)
+         */
+        .m_clk(eth_gty_tx_clk[n]),
+        .m_rst(eth_gty_tx_rst[n]),
+        .m_axis(eth_gty_axis_tx[n]),
+
+        /*
+         * Pause
+         */
+        .s_pause_req(1'b0),
+        .s_pause_ack(),
+        .m_pause_req(1'b0),
+        .m_pause_ack(),
+
+        /*
+         * Status
+         */
+        .s_status_depth(),
+        .s_status_depth_commit(),
+        .s_status_overflow(),
+        .s_status_bad_frame(),
+        .s_status_good_frame(),
+        .m_status_depth(),
+        .m_status_depth_commit(),
+        .m_status_overflow(),
+        .m_status_bad_frame(),
+        .m_status_good_frame()
+    );
+
+end
+
+for (genvar n = 0; n < ADC_CNT; n = n + 1) begin : rfdc_lpbk
+
+    assign m_axis_dac[n].tdata = s_axis_adc[n].tdata;
+    assign m_axis_dac[n].tvalid = s_axis_adc[n].tvalid;
+    assign s_axis_adc[n].tready = m_axis_dac[n].tready;
+
+end
+
+endmodule
+
+`resetall

src/eth/example/HTG_ZRF8/fpga/rtl/fpga_em.sv

@@ -0,0 +1,897 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA top-level module for HTG-ZRF8-EM
+ */
+module fpga #
+(
+    parameter logic SIM = 1'b0,
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "zynquplusRFSOC"
+)
+(
+    /*
+     * Clock: 200 MHz LVDS
+     */
+    input  wire logic       clk_pl_user_p,
+    input  wire logic       clk_pl_user_n,
+    input  wire logic       fpga_refclk_p,
+    input  wire logic       fpga_refclk_n,
+    input  wire logic       fpga_sysref_p,
+    input  wire logic       fpga_sysref_n,
+
+    /*
+     * GPIO
+     */
+    input  wire logic       btn,
+    input  wire logic [3:0] sw,
+    output wire logic [3:0] led,
+    output wire logic [7:0] gpio,
+
+    /*
+     * I2C for board management
+     */
+    inout  wire logic       i2c_scl,
+    inout  wire logic       i2c_sda,
+    output wire logic       i2c_rst_n,
+
+    /*
+     * UART: 921600 bps, 8N1
+     */
+    output wire logic       uart_rxd,
+    input  wire logic       uart_txd,
+    input  wire logic       uart_rts,
+    output wire logic       uart_cts,
+    output wire logic       uart_rst_n,
+    input  wire logic       uart_suspend_n,
+
+    /*
+     * FMC+
+     */
+    // output wire logic [9:0] fmc_la_p,
+    // output wire logic [9:0] fmc_la_n,
+
+    output wire logic [7:0] fmc_dp_c2m_p,
+    output wire logic [7:0] fmc_dp_c2m_n,
+    input  wire logic [7:0] fmc_dp_m2c_p,
+    input  wire logic [7:0] fmc_dp_m2c_n,
+    input  wire logic       fmc_mgt_refclk_0_0_p,
+    input  wire logic       fmc_mgt_refclk_0_0_n,
+    input  wire logic       fmc_mgt_refclk_1_0_p,
+    input  wire logic       fmc_mgt_refclk_1_0_n,
+
+    /*
+     * RFDC
+     */
+    input  wire logic [7:0] adc_vin_p,
+    input  wire logic [7:0] adc_vin_n,
+
+    input  wire logic       adc_refclk_0_p,
+    input  wire logic       adc_refclk_0_n,
+    input  wire logic       adc_refclk_1_p,
+    input  wire logic       adc_refclk_1_n,
+    input  wire logic       adc_refclk_2_p,
+    input  wire logic       adc_refclk_2_n,
+    input  wire logic       adc_refclk_3_p,
+    input  wire logic       adc_refclk_3_n,
+
+    output wire logic [7:0] dac_vout_p,
+    output wire logic [7:0] dac_vout_n,
+
+    // input  wire logic       dac_refclk_0_p,
+    // input  wire logic       dac_refclk_0_n,
+    input  wire logic       dac_refclk_1_p,
+    input  wire logic       dac_refclk_1_n,
+
+    input  wire logic       rfdc_sysref_p,
+    input  wire logic       rfdc_sysref_n
+);
+
+// PLL
+wire pll_i2c_busy;
+
+// Clock and reset
+
+wire clk_pl_user_ibufg;
+wire clk_pl_user_bufg;
+
+// Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
+wire clk_125mhz_int;
+wire rst_125mhz_int;
+
+wire mmcm_rst = pll_i2c_busy;
+wire mmcm_locked;
+wire mmcm_clkfb;
+
+IBUFGDS #(
+   .DIFF_TERM("FALSE"),
+   .IBUF_LOW_PWR("FALSE")   
+)
+clk_pl_user_ibufg_inst (
+   .I (clk_pl_user_p),
+   .IB(clk_pl_user_n),
+   .O (clk_pl_user_ibufg)
+);
+
+BUFG
+clk_pl_user_bufg_inst (
+    .I(clk_pl_user_ibufg),
+    .O(clk_pl_user_bufg)
+);
+
+// MMCM instance
+MMCME4_BASE #(
+    // 200 MHz input
+    .CLKIN1_PERIOD(5.0),
+    .REF_JITTER1(0.010),
+    // 200 MHz input / 1 = 200 MHz PFD (range 10 MHz to 500 MHz)
+    .DIVCLK_DIVIDE(1),
+    // 200 MHz PFD * 5 = 1000 MHz VCO (range 800 MHz to 1600 MHz)
+    .CLKFBOUT_MULT_F(5),
+    .CLKFBOUT_PHASE(0),
+    // 1000 MHz / 8 = 125 MHz, 0 degrees
+    .CLKOUT0_DIVIDE_F(8),
+    .CLKOUT0_DUTY_CYCLE(0.5),
+    .CLKOUT0_PHASE(0),
+    // Not used
+    .CLKOUT1_DIVIDE(1),
+    .CLKOUT1_DUTY_CYCLE(0.5),
+    .CLKOUT1_PHASE(0),
+    // Not used
+    .CLKOUT2_DIVIDE(1),
+    .CLKOUT2_DUTY_CYCLE(0.5),
+    .CLKOUT2_PHASE(0),
+    // Not used
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.5),
+    .CLKOUT3_PHASE(0),
+    // Not used
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.5),
+    .CLKOUT4_PHASE(0),
+    .CLKOUT4_CASCADE("FALSE"),
+    // Not used
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.5),
+    .CLKOUT5_PHASE(0),
+    // Not used
+    .CLKOUT6_DIVIDE(1),
+    .CLKOUT6_DUTY_CYCLE(0.5),
+    .CLKOUT6_PHASE(0),
+
+    // optimized bandwidth
+    .BANDWIDTH("OPTIMIZED"),
+    // don't wait for lock during startup
+    .STARTUP_WAIT("FALSE")
+)
+clk_mmcm_inst (
+    // 200 MHz input
+    .CLKIN1(clk_pl_user_bufg),
+    // direct clkfb feeback
+    .CLKFBIN(mmcm_clkfb),
+    .CLKFBOUT(mmcm_clkfb),
+    .CLKFBOUTB(),
+    // 125 MHz, 0 degrees
+    .CLKOUT0(clk_125mhz_mmcm_out),
+    .CLKOUT0B(),
+    // Not used
+    .CLKOUT1(),
+    .CLKOUT1B(),
+    // Not used
+    .CLKOUT2(),
+    .CLKOUT2B(),
+    // Not used
+    .CLKOUT3(),
+    .CLKOUT3B(),
+    // Not used
+    .CLKOUT4(),
+    // Not used
+    .CLKOUT5(),
+    // Not used
+    .CLKOUT6(),
+    // reset input
+    .RST(mmcm_rst),
+    // don't power down
+    .PWRDWN(1'b0),
+    // locked output
+    .LOCKED(mmcm_locked)
+);
+
+BUFG
+clk_125mhz_bufg_inst (
+    .I(clk_125mhz_mmcm_out),
+    .O(clk_125mhz_int)
+);
+
+taxi_sync_reset #(
+    .N(4)
+)
+sync_reset_125mhz_inst (
+    .clk(clk_125mhz_int),
+    .rst(~mmcm_locked),
+    .out(rst_125mhz_int)
+);
+
+wire fpga_refclk_ibufg;
+wire fpga_refclk_int;
+wire fpga_sysref_ibufg;
+wire fpga_sysref_int;
+
+IBUFGDS #(
+   .DIFF_TERM("FALSE"),
+   .IBUF_LOW_PWR("FALSE")   
+)
+fpga_refclk_ibufg_inst (
+   .O   (fpga_refclk_ibufg),
+   .I   (fpga_refclk_p),
+   .IB  (fpga_refclk_n) 
+);
+
+BUFG
+fpga_refclk_bufg_inst (
+    .I(fpga_refclk_ibufg),
+    .O(fpga_refclk_int)
+);
+
+IBUFGDS #(
+   .DIFF_TERM("FALSE"),
+   .IBUF_LOW_PWR("FALSE")   
+)
+fpga_sysref_ibufg_inst (
+   .O   (fpga_sysref_ibufg),
+   .I   (fpga_sysref_p),
+   .IB  (fpga_sysref_n) 
+);
+
+BUFG
+fpga_sysref_bufg_inst (
+    .I(fpga_sysref_ibufg),
+    .O(fpga_sysref_int)
+);
+
+// STARTUP instance for cfgmclk
+wire cfgmclk;
+
+STARTUPE3
+startupe3_inst (
+    .CFGCLK(),
+    .CFGMCLK(cfgmclk),
+    .DI(),
+    .DO(4'd0),
+    .DTS(1'b1),
+    .EOS(),
+    .FCSBO(1'b1),
+    .FCSBTS(1'b1),
+    .GSR(1'b0),
+    .GTS(1'b0),
+    .KEYCLEARB(1'b1),
+    .PACK(1'b0),
+    .PREQ(),
+    .USRCCLKO(1'b0),
+    .USRCCLKTS(1'b1),
+    .USRDONEO(1'b0),
+    .USRDONETS(1'b1)
+);
+
+wire cfgmclk_int;
+
+BUFG
+cfgmclk_bufg_inst (
+    .I(cfgmclk),
+    .O(cfgmclk_int)
+);
+
+wire cfgmclk_rst_int;
+
+taxi_sync_reset #(
+    .N(4)
+)
+sync_reset_cfgmclk_inst (
+    .clk(cfgmclk_int),
+    .rst(~btn),
+    .out(cfgmclk_rst_int)
+);
+
+// GPIO
+wire [3:0] sw_int;
+
+taxi_debounce_switch #(
+    .WIDTH(4),
+    .N(4),
+    .RATE(125000)
+)
+debounce_switch_inst (
+    .clk(clk_125mhz_int),
+    .rst(rst_125mhz_int),
+    .in({sw}),
+    .out({sw_int})
+);
+
+wire uart_txd_int;
+wire uart_rts_int;
+
+taxi_sync_signal #(
+    .WIDTH(2),
+    .N(2)
+)
+sync_signal_inst (
+    .clk(clk_125mhz_int),
+    .in({uart_txd, uart_rts}),
+    .out({uart_txd_int, uart_rts_int})
+);
+
+wire i2c_scl_i;
+wire i2c_scl_o;
+wire i2c_sda_i;
+wire i2c_sda_o;
+
+assign i2c_scl_i = i2c_scl;
+assign i2c_scl = i2c_scl_o ? 1'bz : 1'b0;
+assign i2c_sda_i = i2c_sda;
+assign i2c_sda = i2c_sda_o ? 1'bz : 1'b0;
+assign i2c_rst_n = 1'b1;
+
+wire i2c_init_scl_i = i2c_scl_i;
+wire i2c_init_scl_o;
+wire i2c_init_sda_i = i2c_sda_i;
+wire i2c_init_sda_o;
+
+wire i2c_int_scl_i = i2c_scl_i;
+wire i2c_int_scl_o;
+wire i2c_int_sda_i = i2c_sda_i;
+wire i2c_int_sda_o;
+
+assign i2c_scl_o = i2c_init_scl_o & i2c_int_scl_o;
+assign i2c_sda_o = i2c_init_sda_o & i2c_int_sda_o;
+
+// PLL init
+taxi_axis_if #(.DATA_W(12)) pll_i2c_cmd();
+taxi_axis_if #(.DATA_W(8)) pll_i2c_tx();
+taxi_axis_if #(.DATA_W(8)) pll_i2c_rx();
+
+assign pll_i2c_rx.tready = 1'b1;
+
+taxi_i2c_master
+pll_i2c_master_inst (
+    .clk(cfgmclk_int),
+    .rst(cfgmclk_rst_int),
+
+    /*
+     * Host interface
+     */
+    .s_axis_cmd(pll_i2c_cmd),
+    .s_axis_tx(pll_i2c_tx),
+    .m_axis_rx(pll_i2c_rx),
+
+    /*
+     * I2C interface
+     */
+    .scl_i(i2c_init_scl_i),
+    .scl_o(i2c_init_scl_o),
+    .sda_i(i2c_init_sda_i),
+    .sda_o(i2c_init_sda_o),
+
+    /*
+     * Status
+     */
+    .busy(),
+    .bus_control(),
+    .bus_active(),
+    .missed_ack(),
+
+    /*
+     * Configuration
+     */
+    .prescale(SIM ? 15 : 150),
+    .stop_on_idle(1)
+);
+
+pll_i2c_init_em #(
+    .SIM_SPEEDUP(SIM)
+)
+pll_i2c_init_inst (
+    .clk(cfgmclk_int),
+    .rst(cfgmclk_rst_int),
+
+    /*
+     * I2C master interface
+     */
+    .m_axis_cmd(pll_i2c_cmd),
+    .m_axis_tx(pll_i2c_tx),
+
+    /*
+     * Status
+     */
+    .busy(pll_i2c_busy),
+
+    /*
+     * Configuration
+     */
+    .start(1'b1)
+);
+
+localparam PORT_CNT = 2;
+localparam GTY_QUAD_CNT = PORT_CNT;
+localparam GTY_CNT = GTY_QUAD_CNT*4;
+localparam GTY_CLK_CNT = GTY_QUAD_CNT;
+
+// RF data converters
+localparam ADC_CNT = 8;
+localparam ADC_SAMPLE_W = 16;
+localparam ADC_SAMPLE_CNT = 4;
+localparam ADC_DATA_W = ADC_SAMPLE_W*ADC_SAMPLE_CNT;
+
+localparam DAC_CNT = ADC_CNT;
+localparam DAC_SAMPLE_W = ADC_SAMPLE_W;
+localparam DAC_SAMPLE_CNT = ADC_SAMPLE_CNT;
+localparam DAC_DATA_W = DAC_SAMPLE_W*DAC_SAMPLE_CNT;
+
+wire axil_rfdc_clk = clk_125mhz_int;
+wire axil_rfdc_rst = rst_125mhz_int;
+
+taxi_axil_if #(
+    .DATA_W(32),
+    .ADDR_W(18)
+) axil_rfdc();
+
+wire axis_rfdc_clk;
+wire axis_rfdc_rst;
+
+wire [3:0] adc_clk_out;
+wire [3:0] dac_clk_out;
+
+taxi_axis_if #(
+    .DATA_W(ADC_DATA_W),
+    .KEEP_EN(1),
+    .KEEP_W(ADC_SAMPLE_CNT),
+    .LAST_EN(0),
+    .USER_EN(0),
+    .ID_EN(0),
+    .DEST_EN(0)
+) axis_adc[ADC_CNT]();
+
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_0 = axis_adc[0].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_1 = axis_adc[1].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_2 = axis_adc[2].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_3 = axis_adc[3].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_4 = axis_adc[4].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_5 = axis_adc[5].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_6 = axis_adc[6].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_7 = axis_adc[7].tdata;
+
+taxi_axis_if #(
+    .DATA_W(DAC_DATA_W),
+    .KEEP_EN(1),
+    .KEEP_W(DAC_SAMPLE_CNT),
+    .LAST_EN(0),
+    .USER_EN(0),
+    .ID_EN(0),
+    .DEST_EN(0)
+) axis_dac[DAC_CNT]();
+
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_0 = axis_dac[0].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_1 = axis_dac[1].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_2 = axis_dac[2].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_3 = axis_dac[3].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_4 = axis_dac[4].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_5 = axis_dac[5].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_6 = axis_dac[6].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_7 = axis_dac[7].tdata;
+
+wire rfdc_mmcm_in = dac_clk_out[0];
+wire rfdc_mmcm_rst = rst_125mhz_int;
+wire rfdc_mmcm_clkfb;
+wire rfdc_mmcm_locked;
+wire rfdc_mmcm_out;
+
+// MMCM instance
+MMCME4_BASE #(
+    // 62.5 MHz input
+    .CLKIN1_PERIOD(16.0),
+    .REF_JITTER1(0.010),
+    // 62.5 MHz input / 1 = 62.5 MHz PFD (range 10 MHz to 500 MHz)
+    .DIVCLK_DIVIDE(1),
+    // 62.5 MHz PFD * 20 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
+    .CLKFBOUT_MULT_F(20),
+    .CLKFBOUT_PHASE(0),
+    // 1250 MHz / 5 = 250 MHz, 0 degrees
+    .CLKOUT0_DIVIDE_F(5),
+    .CLKOUT0_DUTY_CYCLE(0.5),
+    .CLKOUT0_PHASE(0),
+    // Not used
+    .CLKOUT1_DIVIDE(1),
+    .CLKOUT1_DUTY_CYCLE(0.5),
+    .CLKOUT1_PHASE(0),
+    // Not used
+    .CLKOUT2_DIVIDE(1),
+    .CLKOUT2_DUTY_CYCLE(0.5),
+    .CLKOUT2_PHASE(0),
+    // Not used
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.5),
+    .CLKOUT3_PHASE(0),
+    // Not used
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.5),
+    .CLKOUT4_PHASE(0),
+    .CLKOUT4_CASCADE("FALSE"),
+    // Not used
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.5),
+    .CLKOUT5_PHASE(0),
+    // Not used
+    .CLKOUT6_DIVIDE(1),
+    .CLKOUT6_DUTY_CYCLE(0.5),
+    .CLKOUT6_PHASE(0),
+
+    // optimized bandwidth
+    .BANDWIDTH("OPTIMIZED"),
+    // don't wait for lock during startup
+    .STARTUP_WAIT("FALSE")
+)
+rfdc_mmcm_inst (
+    // 62.5 MHz input
+    .CLKIN1(rfdc_mmcm_in),
+    // direct clkfb feeback
+    .CLKFBIN(rfdc_mmcm_clkfb),
+    .CLKFBOUT(rfdc_mmcm_clkfb),
+    .CLKFBOUTB(),
+    // 250 MHz, 0 degrees
+    .CLKOUT0(rfdc_mmcm_out),
+    .CLKOUT0B(),
+    // Not used
+    .CLKOUT1(),
+    .CLKOUT1B(),
+    // Not used
+    .CLKOUT2(),
+    .CLKOUT2B(),
+    // Not used
+    .CLKOUT3(),
+    .CLKOUT3B(),
+    // Not used
+    .CLKOUT4(),
+    // Not used
+    .CLKOUT5(),
+    // Not used
+    .CLKOUT6(),
+    // reset input
+    .RST(rfdc_mmcm_rst),
+    // don't power down
+    .PWRDWN(1'b0),
+    // locked output
+    .LOCKED(rfdc_mmcm_locked)
+);
+
+BUFG
+axis_rfdc_bufg_inst (
+    .I(rfdc_mmcm_out),
+    .O(axis_rfdc_clk)
+);
+
+taxi_sync_reset #(
+    .N(4)
+)
+axis_rfdc_sync_reset_inst (
+    .clk(axis_rfdc_clk),
+    .rst(!rfdc_mmcm_locked || rfdc_mmcm_rst),
+    .out(axis_rfdc_rst)
+);
+
+usp_rfdc_0 rfdc_inst (
+    // Common
+    .sysref_in_p(rfdc_sysref_p),
+    .sysref_in_n(rfdc_sysref_n),
+
+    .s_axi_aclk(axil_rfdc_clk),
+    .s_axi_aresetn(!axil_rfdc_rst),
+    .s_axi_awaddr(axil_rfdc.awaddr),
+    .s_axi_awvalid(axil_rfdc.awvalid),
+    .s_axi_awready(axil_rfdc.awready),
+    .s_axi_wdata(axil_rfdc.wdata),
+    .s_axi_wstrb(axil_rfdc.wstrb),
+    .s_axi_wvalid(axil_rfdc.wvalid),
+    .s_axi_wready(axil_rfdc.wready),
+    .s_axi_bresp(axil_rfdc.bresp),
+    .s_axi_bvalid(axil_rfdc.bvalid),
+    .s_axi_bready(axil_rfdc.bready),
+    .s_axi_araddr(axil_rfdc.araddr),
+    .s_axi_arvalid(axil_rfdc.arvalid),
+    .s_axi_arready(axil_rfdc.arready),
+    .s_axi_rdata(axil_rfdc.rdata),
+    .s_axi_rresp(axil_rfdc.rresp),
+    .s_axi_rvalid(axil_rfdc.rvalid),
+    .s_axi_rready(axil_rfdc.rready),
+
+    .irq(),
+
+    // ADC
+    .adc0_clk_p(adc_refclk_0_p),
+    .adc0_clk_n(adc_refclk_0_n),
+    .clk_adc0(adc_clk_out[0]),
+
+    .adc1_clk_p(adc_refclk_1_p),
+    .adc1_clk_n(adc_refclk_1_n),
+    .clk_adc1(adc_clk_out[1]),
+
+    .adc2_clk_p(adc_refclk_2_p),
+    .adc2_clk_n(adc_refclk_2_n),
+    .clk_adc2(adc_clk_out[2]),
+
+    .adc3_clk_p(adc_refclk_3_p),
+    .adc3_clk_n(adc_refclk_3_n),
+    .clk_adc3(adc_clk_out[3]),
+
+    .vin0_01_p(adc_vin_p[7]),
+    .vin0_01_n(adc_vin_n[7]),
+    .vin0_23_p(adc_vin_p[6]),
+    .vin0_23_n(adc_vin_n[6]),
+
+    .vin1_01_p(adc_vin_p[5]),
+    .vin1_01_n(adc_vin_n[5]),
+    .vin1_23_p(adc_vin_p[4]),
+    .vin1_23_n(adc_vin_n[4]),
+
+    .vin2_01_p(adc_vin_p[3]),
+    .vin2_01_n(adc_vin_n[3]),
+    .vin2_23_p(adc_vin_p[2]),
+    .vin2_23_n(adc_vin_n[2]),
+
+    .vin3_01_p(adc_vin_p[1]),
+    .vin3_01_n(adc_vin_n[1]),
+    .vin3_23_p(adc_vin_p[0]),
+    .vin3_23_n(adc_vin_n[0]),
+
+    .m0_axis_aresetn(!axis_rfdc_rst),
+    .m0_axis_aclk(axis_rfdc_clk),
+    .m00_axis_tdata(axis_adc[7].tdata),
+    .m00_axis_tvalid(axis_adc[7].tvalid),
+    .m00_axis_tready(axis_adc[7].tready),
+    .m02_axis_tdata(axis_adc[6].tdata),
+    .m02_axis_tvalid(axis_adc[6].tvalid),
+    .m02_axis_tready(axis_adc[6].tready),
+
+    .m1_axis_aresetn(!axis_rfdc_rst),
+    .m1_axis_aclk(axis_rfdc_clk),
+    .m10_axis_tdata(axis_adc[5].tdata),
+    .m10_axis_tvalid(axis_adc[5].tvalid),
+    .m10_axis_tready(axis_adc[5].tready),
+    .m12_axis_tdata(axis_adc[4].tdata),
+    .m12_axis_tvalid(axis_adc[4].tvalid),
+    .m12_axis_tready(axis_adc[4].tready),
+
+    .m2_axis_aresetn(!axis_rfdc_rst),
+    .m2_axis_aclk(axis_rfdc_clk),
+    .m20_axis_tdata(axis_adc[3].tdata),
+    .m20_axis_tvalid(axis_adc[3].tvalid),
+    .m20_axis_tready(axis_adc[3].tready),
+    .m22_axis_tdata(axis_adc[2].tdata),
+    .m22_axis_tvalid(axis_adc[2].tvalid),
+    .m22_axis_tready(axis_adc[2].tready),
+
+    .m3_axis_aresetn(!axis_rfdc_rst),
+    .m3_axis_aclk(axis_rfdc_clk),
+    .m30_axis_tdata(axis_adc[1].tdata),
+    .m30_axis_tvalid(axis_adc[1].tvalid),
+    .m30_axis_tready(axis_adc[1].tready),
+    .m32_axis_tdata(axis_adc[0].tdata),
+    .m32_axis_tvalid(axis_adc[0].tvalid),
+    .m32_axis_tready(axis_adc[0].tready),
+
+    .adc0_01_dsa_code(5'd27),
+    .adc0_23_dsa_code(5'd27),
+    .adc0_dsa_update(1'b0),
+    .adc1_01_dsa_code(5'd27),
+    .adc1_23_dsa_code(5'd27),
+    .adc1_dsa_update(1'b0),
+    .adc2_01_dsa_code(5'd27),
+    .adc2_23_dsa_code(5'd27),
+    .adc2_dsa_update(1'b0),
+    .adc3_01_dsa_code(5'd27),
+    .adc3_23_dsa_code(5'd27),
+    .adc3_dsa_update(1'b0),
+
+    // DAC
+    .dac2_clk_p(dac_refclk_1_p),
+    .dac2_clk_n(dac_refclk_1_n),
+
+    .clk_dac0(dac_clk_out[0]),
+    .clk_dac1(dac_clk_out[1]),
+    .clk_dac2(dac_clk_out[2]),
+    .clk_dac3(dac_clk_out[3]),
+
+    .vout00_p(dac_vout_p[7]),
+    .vout00_n(dac_vout_n[7]),
+    .vout02_p(dac_vout_p[6]),
+    .vout02_n(dac_vout_n[6]),
+
+    .vout10_p(dac_vout_p[5]),
+    .vout10_n(dac_vout_n[5]),
+    .vout12_p(dac_vout_p[4]),
+    .vout12_n(dac_vout_n[4]),
+
+    .vout20_p(dac_vout_p[3]),
+    .vout20_n(dac_vout_n[3]),
+    .vout22_p(dac_vout_p[2]),
+    .vout22_n(dac_vout_n[2]),
+
+    .vout30_p(dac_vout_p[1]),
+    .vout30_n(dac_vout_n[1]),
+    .vout32_p(dac_vout_p[0]),
+    .vout32_n(dac_vout_n[0]),
+
+    .s0_axis_aresetn(!axis_rfdc_rst),
+    .s0_axis_aclk(axis_rfdc_clk),
+    .s00_axis_tdata(axis_dac[7].tdata),
+    .s00_axis_tvalid(axis_dac[7].tvalid),
+    .s00_axis_tready(axis_dac[7].tready),
+    .s02_axis_tdata(axis_dac[6].tdata),
+    .s02_axis_tvalid(axis_dac[6].tvalid),
+    .s02_axis_tready(axis_dac[6].tready),
+
+    .s1_axis_aresetn(!axis_rfdc_rst),
+    .s1_axis_aclk(axis_rfdc_clk),
+    .s10_axis_tdata(axis_dac[5].tdata),
+    .s10_axis_tvalid(axis_dac[5].tvalid),
+    .s10_axis_tready(axis_dac[5].tready),
+    .s12_axis_tdata(axis_dac[4].tdata),
+    .s12_axis_tvalid(axis_dac[4].tvalid),
+    .s12_axis_tready(axis_dac[4].tready),
+
+    .s2_axis_aresetn(!axis_rfdc_rst),
+    .s2_axis_aclk(axis_rfdc_clk),
+    .s20_axis_tdata(axis_dac[3].tdata),
+    .s20_axis_tvalid(axis_dac[3].tvalid),
+    .s20_axis_tready(axis_dac[3].tready),
+    .s22_axis_tdata(axis_dac[2].tdata),
+    .s22_axis_tvalid(axis_dac[2].tvalid),
+    .s22_axis_tready(axis_dac[2].tready),
+
+    .s3_axis_aresetn(!axis_rfdc_rst),
+    .s3_axis_aclk(axis_rfdc_clk),
+    .s30_axis_tdata(axis_dac[1].tdata),
+    .s30_axis_tvalid(axis_dac[1].tvalid),
+    .s30_axis_tready(axis_dac[1].tready),
+    .s32_axis_tdata(axis_dac[0].tdata),
+    .s32_axis_tvalid(axis_dac[0].tvalid),
+    .s32_axis_tready(axis_dac[0].tready),
+
+    .dac00_vop_code(10'd895),
+    .dac02_vop_code(10'd895),
+    .dac00_update_vop(1'b0),
+    .dac02_update_vop(1'b0),
+    .dac00_vop_done(),
+    .dac02_vop_done(),
+    .dac0_vop_busy(),
+
+    .dac10_vop_code(10'd895),
+    .dac12_vop_code(10'd895),
+    .dac10_update_vop(1'b0),
+    .dac12_update_vop(1'b0),
+    .dac10_vop_done(),
+    .dac12_vop_done(),
+    .dac1_vop_busy(),
+
+    .dac20_vop_code(10'd895),
+    .dac22_vop_code(10'd895),
+    .dac20_update_vop(1'b0),
+    .dac22_update_vop(1'b0),
+    .dac20_vop_done(),
+    .dac22_vop_done(),
+    .dac2_vop_busy(),
+
+    .dac30_vop_code(10'd895),
+    .dac32_vop_code(10'd895),
+    .dac30_update_vop(1'b0),
+    .dac32_update_vop(1'b0),
+    .dac30_vop_done(),
+    .dac32_vop_done(),
+    .dac3_vop_busy()
+);
+
+fpga_core #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .PORT_CNT(PORT_CNT),
+    .GTY_QUAD_CNT(GTY_QUAD_CNT),
+    .GTY_CNT(GTY_CNT),
+    .GTY_CLK_CNT(GTY_CLK_CNT),
+    .ADC_CNT(ADC_CNT),
+    .DAC_CNT(DAC_CNT)
+)
+core_inst (
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    .clk_125mhz(clk_125mhz_int),
+    .rst_125mhz(rst_125mhz_int),
+    .fpga_refclk(fpga_refclk_int),
+    .fpga_sysref(fpga_sysref_int),
+
+    /*
+     * GPIO
+     */
+    .sw(sw_int),
+    .led(led),
+    .gpio(gpio),
+
+    /*
+     * I2C for board management
+     */
+    .i2c_scl_i(i2c_int_scl_i),
+    .i2c_scl_o(i2c_int_scl_o),
+    .i2c_sda_i(i2c_int_sda_i),
+    .i2c_sda_o(i2c_int_sda_o),
+
+    /*
+     * UART: 921600 bps, 8N1
+     */
+    .uart_rxd(uart_rxd),
+    .uart_txd(uart_txd_int),
+    .uart_rts(uart_rts_int),
+    .uart_cts(uart_cts),
+    .uart_rst_n(uart_rst_n),
+    .uart_suspend_n(uart_suspend_n),
+
+    /*
+     * Ethernet: QSFP28
+     */
+    .eth_gty_tx_p(fmc_dp_c2m_p),
+    .eth_gty_tx_n(fmc_dp_c2m_n),
+    .eth_gty_rx_p(fmc_dp_m2c_p),
+    .eth_gty_rx_n(fmc_dp_m2c_n),
+    .eth_gty_mgt_refclk_p({fmc_mgt_refclk_1_0_p, fmc_mgt_refclk_0_0_p}),
+    .eth_gty_mgt_refclk_n({fmc_mgt_refclk_1_0_n, fmc_mgt_refclk_0_0_n}),
+    .eth_gty_mgt_refclk_out(),
+
+    .eth_port_resetl(),
+    .eth_port_modprsl('0),
+    .eth_port_intl('1),
+
+    /*
+     * RFDC
+     */
+    .axil_rfdc_clk(axil_rfdc_clk),
+    .axil_rfdc_rst(axil_rfdc_rst),
+    .m_axil_rfdc_wr(axil_rfdc),
+    .m_axil_rfdc_rd(axil_rfdc),
+
+    .axis_rfdc_clk(axis_rfdc_clk),
+    .axis_rfdc_rst(axis_rfdc_rst),
+    .s_axis_adc(axis_adc),
+    .m_axis_dac(axis_dac)
+);
+
+endmodule
+
+`resetall

src/eth/example/HTG_ZRF8/fpga/rtl/fpga_r2.sv

@@ -0,0 +1,923 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA top-level module for HTG-ZRF8-R2
+ */
+module fpga #
+(
+    parameter logic SIM = 1'b0,
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "zynquplusRFSOC"
+)
+(
+    /*
+     * Clock: 200 MHz LVDS
+     */
+    input  wire logic         clk_pl_user1_p,
+    input  wire logic         clk_pl_user1_n,
+    input  wire logic         fpga_refclk_p,
+    input  wire logic         fpga_refclk_n,
+    input  wire logic         fpga_sysref_p,
+    input  wire logic         fpga_sysref_n,
+
+    /*
+     * GPIO
+     */
+    input  wire logic         btn,
+    input  wire logic [3:0]   sw,
+    output wire logic [3:0]   led,
+
+    /*
+     * I2C for board management
+     */
+    inout  wire logic         i2c_scl,
+    inout  wire logic         i2c_sda,
+    output wire logic         i2c_rst_n,
+
+    /*
+     * PLL
+     */
+    output wire logic         clk_fdec,
+    output wire logic         clk_finc,
+    input  wire logic         clk_intr_n,
+    input  wire logic         clk_lol_n,
+    output wire logic         clk_sync_n,
+    output wire logic         clk_rst_n,
+    output wire logic         lmk_rst,
+    output wire logic [1:0]   lmk_clkin_s,
+
+    /*
+     * UART: 921600 bps, 8N1
+     */
+    output wire logic         uart_rxd,
+    input  wire logic         uart_txd,
+    input  wire logic         uart_rts,
+    output wire logic         uart_cts,
+    output wire logic         uart_rst_n,
+    input  wire logic         uart_suspend_n,
+
+    /*
+     * FMC+
+     */
+    // output wire logic [33:0]  fmc_la_p,
+    // output wire logic [33:0]  fmc_la_n,
+    output wire logic         fmc_qsfp_modsell,
+    output wire logic         fmc_qsfp_resetl,
+    output wire logic         fmc_qsfp_lpmode,
+
+    output wire logic [7:0]   fmc_dp_c2m_p,
+    output wire logic [7:0]   fmc_dp_c2m_n,
+    input  wire logic [7:0]   fmc_dp_m2c_p,
+    input  wire logic [7:0]   fmc_dp_m2c_n,
+    input  wire logic         fmc_mgt_refclk_0_0_p,
+    input  wire logic         fmc_mgt_refclk_0_0_n,
+    input  wire logic         fmc_mgt_refclk_1_0_p,
+    input  wire logic         fmc_mgt_refclk_1_0_n,
+
+    /*
+     * RFDC
+     */
+    input  wire logic [7:0]   adc_vin_p,
+    input  wire logic [7:0]   adc_vin_n,
+
+    input  wire logic         adc_refclk_0_p,
+    input  wire logic         adc_refclk_0_n,
+    input  wire logic         adc_refclk_1_p,
+    input  wire logic         adc_refclk_1_n,
+    input  wire logic         adc_refclk_2_p,
+    input  wire logic         adc_refclk_2_n,
+    input  wire logic         adc_refclk_3_p,
+    input  wire logic         adc_refclk_3_n,
+
+    output wire logic [7:0]   dac_vout_p,
+    output wire logic [7:0]   dac_vout_n,
+
+    // input  wire logic         dac_refclk_0_p,
+    // input  wire logic         dac_refclk_0_n,
+    input  wire logic         dac_refclk_1_p,
+    input  wire logic         dac_refclk_1_n,
+
+    input  wire logic         rfdc_sysref_p,
+    input  wire logic         rfdc_sysref_n
+);
+
+// PLL
+assign clk_fdec = 1'b0;
+assign clk_finc = 1'b0;
+assign clk_sync_n = 1'b1;
+assign clk_rst_n = 1'b1;
+
+assign lmk_rst = 1'b0;
+assign lmk_clkin_s = 2'b00;
+
+wire pll_i2c_busy;
+
+// Clock and reset
+
+wire clk_pl_user1_ibufg;
+wire clk_pl_user1_bufg;
+
+// Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
+wire clk_125mhz_int;
+wire rst_125mhz_int;
+
+wire mmcm_rst = pll_i2c_busy || !clk_lol_n;
+wire mmcm_locked;
+wire mmcm_clkfb;
+
+IBUFGDS #(
+   .DIFF_TERM("FALSE"),
+   .IBUF_LOW_PWR("FALSE")   
+)
+clk_pl_user1_ibufg_inst (
+   .I (clk_pl_user1_p),
+   .IB(clk_pl_user1_n),
+   .O (clk_pl_user1_ibufg)
+);
+
+BUFG
+clk_pl_user1_bufg_inst (
+    .I(clk_pl_user1_ibufg),
+    .O(clk_pl_user1_bufg)
+);
+
+// MMCM instance
+MMCME4_BASE #(
+    // 200 MHz input
+    .CLKIN1_PERIOD(5.0),
+    .REF_JITTER1(0.010),
+    // 200 MHz input / 1 = 200 MHz PFD (range 10 MHz to 500 MHz)
+    .DIVCLK_DIVIDE(1),
+    // 200 MHz PFD * 5 = 1000 MHz VCO (range 800 MHz to 1600 MHz)
+    .CLKFBOUT_MULT_F(5),
+    .CLKFBOUT_PHASE(0),
+    // 1000 MHz / 8 = 125 MHz, 0 degrees
+    .CLKOUT0_DIVIDE_F(8),
+    .CLKOUT0_DUTY_CYCLE(0.5),
+    .CLKOUT0_PHASE(0),
+    // Not used
+    .CLKOUT1_DIVIDE(1),
+    .CLKOUT1_DUTY_CYCLE(0.5),
+    .CLKOUT1_PHASE(0),
+    // Not used
+    .CLKOUT2_DIVIDE(1),
+    .CLKOUT2_DUTY_CYCLE(0.5),
+    .CLKOUT2_PHASE(0),
+    // Not used
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.5),
+    .CLKOUT3_PHASE(0),
+    // Not used
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.5),
+    .CLKOUT4_PHASE(0),
+    .CLKOUT4_CASCADE("FALSE"),
+    // Not used
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.5),
+    .CLKOUT5_PHASE(0),
+    // Not used
+    .CLKOUT6_DIVIDE(1),
+    .CLKOUT6_DUTY_CYCLE(0.5),
+    .CLKOUT6_PHASE(0),
+
+    // optimized bandwidth
+    .BANDWIDTH("OPTIMIZED"),
+    // don't wait for lock during startup
+    .STARTUP_WAIT("FALSE")
+)
+clk_mmcm_inst (
+    // 200 MHz input
+    .CLKIN1(clk_pl_user1_bufg),
+    // direct clkfb feeback
+    .CLKFBIN(mmcm_clkfb),
+    .CLKFBOUT(mmcm_clkfb),
+    .CLKFBOUTB(),
+    // 125 MHz, 0 degrees
+    .CLKOUT0(clk_125mhz_mmcm_out),
+    .CLKOUT0B(),
+    // Not used
+    .CLKOUT1(),
+    .CLKOUT1B(),
+    // Not used
+    .CLKOUT2(),
+    .CLKOUT2B(),
+    // Not used
+    .CLKOUT3(),
+    .CLKOUT3B(),
+    // Not used
+    .CLKOUT4(),
+    // Not used
+    .CLKOUT5(),
+    // Not used
+    .CLKOUT6(),
+    // reset input
+    .RST(mmcm_rst),
+    // don't power down
+    .PWRDWN(1'b0),
+    // locked output
+    .LOCKED(mmcm_locked)
+);
+
+BUFG
+clk_125mhz_bufg_inst (
+    .I(clk_125mhz_mmcm_out),
+    .O(clk_125mhz_int)
+);
+
+taxi_sync_reset #(
+    .N(4)
+)
+sync_reset_125mhz_inst (
+    .clk(clk_125mhz_int),
+    .rst(~mmcm_locked),
+    .out(rst_125mhz_int)
+);
+
+wire fpga_refclk_ibufg;
+wire fpga_refclk_int;
+wire fpga_sysref_ibufg;
+wire fpga_sysref_int;
+
+IBUFGDS #(
+   .DIFF_TERM("FALSE"),
+   .IBUF_LOW_PWR("FALSE")   
+)
+fpga_refclk_ibufg_inst (
+   .O   (fpga_refclk_ibufg),
+   .I   (fpga_refclk_p),
+   .IB  (fpga_refclk_n) 
+);
+
+BUFG
+fpga_refclk_bufg_inst (
+    .I(fpga_refclk_ibufg),
+    .O(fpga_refclk_int)
+);
+
+IBUFGDS #(
+   .DIFF_TERM("FALSE"),
+   .IBUF_LOW_PWR("FALSE")   
+)
+fpga_sysref_ibufg_inst (
+   .O   (fpga_sysref_ibufg),
+   .I   (fpga_sysref_p),
+   .IB  (fpga_sysref_n) 
+);
+
+BUFG
+fpga_sysref_bufg_inst (
+    .I(fpga_sysref_ibufg),
+    .O(fpga_sysref_int)
+);
+
+// STARTUP instance for cfgmclk
+wire cfgmclk;
+
+STARTUPE3
+startupe3_inst (
+    .CFGCLK(),
+    .CFGMCLK(cfgmclk),
+    .DI(),
+    .DO(4'd0),
+    .DTS(1'b1),
+    .EOS(),
+    .FCSBO(1'b1),
+    .FCSBTS(1'b1),
+    .GSR(1'b0),
+    .GTS(1'b0),
+    .KEYCLEARB(1'b1),
+    .PACK(1'b0),
+    .PREQ(),
+    .USRCCLKO(1'b0),
+    .USRCCLKTS(1'b1),
+    .USRDONEO(1'b0),
+    .USRDONETS(1'b1)
+);
+
+wire cfgmclk_int;
+
+BUFG
+cfgmclk_bufg_inst (
+    .I(cfgmclk),
+    .O(cfgmclk_int)
+);
+
+wire cfgmclk_rst_int;
+
+taxi_sync_reset #(
+    .N(4)
+)
+sync_reset_cfgmclk_inst (
+    .clk(cfgmclk_int),
+    .rst(~btn),
+    .out(cfgmclk_rst_int)
+);
+
+// GPIO
+wire [3:0] sw_int;
+
+taxi_debounce_switch #(
+    .WIDTH(4),
+    .N(4),
+    .RATE(125000)
+)
+debounce_switch_inst (
+    .clk(clk_125mhz_int),
+    .rst(rst_125mhz_int),
+    .in({sw}),
+    .out({sw_int})
+);
+
+wire uart_txd_int;
+wire uart_rts_int;
+
+taxi_sync_signal #(
+    .WIDTH(2),
+    .N(2)
+)
+sync_signal_inst (
+    .clk(clk_125mhz_int),
+    .in({uart_txd, uart_rts}),
+    .out({uart_txd_int, uart_rts_int})
+);
+
+wire i2c_scl_i;
+wire i2c_scl_o;
+wire i2c_sda_i;
+wire i2c_sda_o;
+
+assign i2c_scl_i = i2c_scl;
+assign i2c_scl = i2c_scl_o ? 1'bz : 1'b0;
+assign i2c_sda_i = i2c_sda;
+assign i2c_sda = i2c_sda_o ? 1'bz : 1'b0;
+assign i2c_rst_n = 1'b1;
+
+wire i2c_init_scl_i = i2c_scl_i;
+wire i2c_init_scl_o;
+wire i2c_init_sda_i = i2c_sda_i;
+wire i2c_init_sda_o;
+
+wire i2c_int_scl_i = i2c_scl_i;
+wire i2c_int_scl_o;
+wire i2c_int_sda_i = i2c_sda_i;
+wire i2c_int_sda_o;
+
+assign i2c_scl_o = i2c_init_scl_o & i2c_int_scl_o;
+assign i2c_sda_o = i2c_init_sda_o & i2c_int_sda_o;
+
+// PLL init
+taxi_axis_if #(.DATA_W(12)) pll_i2c_cmd();
+taxi_axis_if #(.DATA_W(8)) pll_i2c_tx();
+taxi_axis_if #(.DATA_W(8)) pll_i2c_rx();
+
+assign pll_i2c_rx.tready = 1'b1;
+
+taxi_i2c_master
+pll_i2c_master_inst (
+    .clk(cfgmclk_int),
+    .rst(cfgmclk_rst_int),
+
+    /*
+     * Host interface
+     */
+    .s_axis_cmd(pll_i2c_cmd),
+    .s_axis_tx(pll_i2c_tx),
+    .m_axis_rx(pll_i2c_rx),
+
+    /*
+     * I2C interface
+     */
+    .scl_i(i2c_init_scl_i),
+    .scl_o(i2c_init_scl_o),
+    .sda_i(i2c_init_sda_i),
+    .sda_o(i2c_init_sda_o),
+
+    /*
+     * Status
+     */
+    .busy(),
+    .bus_control(),
+    .bus_active(),
+    .missed_ack(),
+
+    /*
+     * Configuration
+     */
+    .prescale(SIM ? 15 : 150),
+    .stop_on_idle(1)
+);
+
+pll_i2c_init_r2 #(
+    .SIM_SPEEDUP(SIM)
+)
+pll_i2c_init_inst (
+    .clk(cfgmclk_int),
+    .rst(cfgmclk_rst_int),
+
+    /*
+     * I2C master interface
+     */
+    .m_axis_cmd(pll_i2c_cmd),
+    .m_axis_tx(pll_i2c_tx),
+
+    /*
+     * Status
+     */
+    .busy(pll_i2c_busy),
+
+    /*
+     * Configuration
+     */
+    .start(1'b1)
+);
+
+localparam PORT_CNT = 2;
+localparam GTY_QUAD_CNT = PORT_CNT;
+localparam GTY_CNT = GTY_QUAD_CNT*4;
+localparam GTY_CLK_CNT = GTY_QUAD_CNT;
+
+assign fmc_qsfp_modsell = 1'b0;
+assign fmc_qsfp_resetl = 1'b1;
+assign fmc_qsfp_lpmode = 1'b0;
+
+// RF data converters
+localparam ADC_CNT = 8;
+localparam ADC_SAMPLE_W = 16;
+localparam ADC_SAMPLE_CNT = 4;
+localparam ADC_DATA_W = ADC_SAMPLE_W*ADC_SAMPLE_CNT;
+
+localparam DAC_CNT = ADC_CNT;
+localparam DAC_SAMPLE_W = ADC_SAMPLE_W;
+localparam DAC_SAMPLE_CNT = ADC_SAMPLE_CNT;
+localparam DAC_DATA_W = DAC_SAMPLE_W*DAC_SAMPLE_CNT;
+
+wire axil_rfdc_clk = clk_125mhz_int;
+wire axil_rfdc_rst = rst_125mhz_int;
+
+taxi_axil_if #(
+    .DATA_W(32),
+    .ADDR_W(18)
+) axil_rfdc();
+
+wire axis_rfdc_clk;
+wire axis_rfdc_rst;
+
+wire [3:0] adc_clk_out;
+wire [3:0] dac_clk_out;
+
+taxi_axis_if #(
+    .DATA_W(ADC_DATA_W),
+    .KEEP_EN(1),
+    .KEEP_W(ADC_SAMPLE_CNT),
+    .LAST_EN(0),
+    .USER_EN(0),
+    .ID_EN(0),
+    .DEST_EN(0)
+) axis_adc[ADC_CNT]();
+
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_0 = axis_adc[0].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_1 = axis_adc[1].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_2 = axis_adc[2].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_3 = axis_adc[3].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_4 = axis_adc[4].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_5 = axis_adc[5].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_6 = axis_adc[6].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [ADC_DATA_W-1:0] adc_data_7 = axis_adc[7].tdata;
+
+taxi_axis_if #(
+    .DATA_W(DAC_DATA_W),
+    .KEEP_EN(1),
+    .KEEP_W(DAC_SAMPLE_CNT),
+    .LAST_EN(0),
+    .USER_EN(0),
+    .ID_EN(0),
+    .DEST_EN(0)
+) axis_dac[DAC_CNT]();
+
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_0 = axis_dac[0].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_1 = axis_dac[1].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_2 = axis_dac[2].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_3 = axis_dac[3].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_4 = axis_dac[4].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_5 = axis_dac[5].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_6 = axis_dac[6].tdata;
+(* MARK_DEBUG = "TRUE" *)
+wire [DAC_DATA_W-1:0] dac_data_7 = axis_dac[7].tdata;
+
+wire rfdc_mmcm_in = dac_clk_out[0];
+wire rfdc_mmcm_rst = rst_125mhz_int;
+wire rfdc_mmcm_clkfb;
+wire rfdc_mmcm_locked;
+wire rfdc_mmcm_out;
+
+// MMCM instance
+MMCME4_BASE #(
+    // 62.5 MHz input
+    .CLKIN1_PERIOD(16.0),
+    .REF_JITTER1(0.010),
+    // 62.5 MHz input / 1 = 62.5 MHz PFD (range 10 MHz to 500 MHz)
+    .DIVCLK_DIVIDE(1),
+    // 62.5 MHz PFD * 20 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
+    .CLKFBOUT_MULT_F(20),
+    .CLKFBOUT_PHASE(0),
+    // 1250 MHz / 5 = 250 MHz, 0 degrees
+    .CLKOUT0_DIVIDE_F(5),
+    .CLKOUT0_DUTY_CYCLE(0.5),
+    .CLKOUT0_PHASE(0),
+    // Not used
+    .CLKOUT1_DIVIDE(1),
+    .CLKOUT1_DUTY_CYCLE(0.5),
+    .CLKOUT1_PHASE(0),
+    // Not used
+    .CLKOUT2_DIVIDE(1),
+    .CLKOUT2_DUTY_CYCLE(0.5),
+    .CLKOUT2_PHASE(0),
+    // Not used
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.5),
+    .CLKOUT3_PHASE(0),
+    // Not used
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.5),
+    .CLKOUT4_PHASE(0),
+    .CLKOUT4_CASCADE("FALSE"),
+    // Not used
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.5),
+    .CLKOUT5_PHASE(0),
+    // Not used
+    .CLKOUT6_DIVIDE(1),
+    .CLKOUT6_DUTY_CYCLE(0.5),
+    .CLKOUT6_PHASE(0),
+
+    // optimized bandwidth
+    .BANDWIDTH("OPTIMIZED"),
+    // don't wait for lock during startup
+    .STARTUP_WAIT("FALSE")
+)
+rfdc_mmcm_inst (
+    // 62.5 MHz input
+    .CLKIN1(rfdc_mmcm_in),
+    // direct clkfb feeback
+    .CLKFBIN(rfdc_mmcm_clkfb),
+    .CLKFBOUT(rfdc_mmcm_clkfb),
+    .CLKFBOUTB(),
+    // 250 MHz, 0 degrees
+    .CLKOUT0(rfdc_mmcm_out),
+    .CLKOUT0B(),
+    // Not used
+    .CLKOUT1(),
+    .CLKOUT1B(),
+    // Not used
+    .CLKOUT2(),
+    .CLKOUT2B(),
+    // Not used
+    .CLKOUT3(),
+    .CLKOUT3B(),
+    // Not used
+    .CLKOUT4(),
+    // Not used
+    .CLKOUT5(),
+    // Not used
+    .CLKOUT6(),
+    // reset input
+    .RST(rfdc_mmcm_rst),
+    // don't power down
+    .PWRDWN(1'b0),
+    // locked output
+    .LOCKED(rfdc_mmcm_locked)
+);
+
+BUFG
+axis_rfdc_bufg_inst (
+    .I(rfdc_mmcm_out),
+    .O(axis_rfdc_clk)
+);
+
+taxi_sync_reset #(
+    .N(4)
+)
+axis_rfdc_sync_reset_inst (
+    .clk(axis_rfdc_clk),
+    .rst(!rfdc_mmcm_locked || rfdc_mmcm_rst),
+    .out(axis_rfdc_rst)
+);
+
+usp_rfdc_0 rfdc_inst (
+    // Common
+    .sysref_in_p(rfdc_sysref_p),
+    .sysref_in_n(rfdc_sysref_n),
+
+    .s_axi_aclk(axil_rfdc_clk),
+    .s_axi_aresetn(!axil_rfdc_rst),
+    .s_axi_awaddr(axil_rfdc.awaddr),
+    .s_axi_awvalid(axil_rfdc.awvalid),
+    .s_axi_awready(axil_rfdc.awready),
+    .s_axi_wdata(axil_rfdc.wdata),
+    .s_axi_wstrb(axil_rfdc.wstrb),
+    .s_axi_wvalid(axil_rfdc.wvalid),
+    .s_axi_wready(axil_rfdc.wready),
+    .s_axi_bresp(axil_rfdc.bresp),
+    .s_axi_bvalid(axil_rfdc.bvalid),
+    .s_axi_bready(axil_rfdc.bready),
+    .s_axi_araddr(axil_rfdc.araddr),
+    .s_axi_arvalid(axil_rfdc.arvalid),
+    .s_axi_arready(axil_rfdc.arready),
+    .s_axi_rdata(axil_rfdc.rdata),
+    .s_axi_rresp(axil_rfdc.rresp),
+    .s_axi_rvalid(axil_rfdc.rvalid),
+    .s_axi_rready(axil_rfdc.rready),
+
+    .irq(),
+
+    // ADC
+    .adc0_clk_p(adc_refclk_0_p),
+    .adc0_clk_n(adc_refclk_0_n),
+    .clk_adc0(adc_clk_out[0]),
+
+    .adc1_clk_p(adc_refclk_1_p),
+    .adc1_clk_n(adc_refclk_1_n),
+    .clk_adc1(adc_clk_out[1]),
+
+    .adc2_clk_p(adc_refclk_2_p),
+    .adc2_clk_n(adc_refclk_2_n),
+    .clk_adc2(adc_clk_out[2]),
+
+    .adc3_clk_p(adc_refclk_3_p),
+    .adc3_clk_n(adc_refclk_3_n),
+    .clk_adc3(adc_clk_out[3]),
+
+    .vin0_01_p(adc_vin_p[7]),
+    .vin0_01_n(adc_vin_n[7]),
+    .vin0_23_p(adc_vin_p[6]),
+    .vin0_23_n(adc_vin_n[6]),
+
+    .vin1_01_p(adc_vin_p[5]),
+    .vin1_01_n(adc_vin_n[5]),
+    .vin1_23_p(adc_vin_p[4]),
+    .vin1_23_n(adc_vin_n[4]),
+
+    .vin2_01_p(adc_vin_p[3]),
+    .vin2_01_n(adc_vin_n[3]),
+    .vin2_23_p(adc_vin_p[2]),
+    .vin2_23_n(adc_vin_n[2]),
+
+    .vin3_01_p(adc_vin_p[1]),
+    .vin3_01_n(adc_vin_n[1]),
+    .vin3_23_p(adc_vin_p[0]),
+    .vin3_23_n(adc_vin_n[0]),
+
+    .m0_axis_aresetn(!axis_rfdc_rst),
+    .m0_axis_aclk(axis_rfdc_clk),
+    .m00_axis_tdata(axis_adc[7].tdata),
+    .m00_axis_tvalid(axis_adc[7].tvalid),
+    .m00_axis_tready(axis_adc[7].tready),
+    .m02_axis_tdata(axis_adc[6].tdata),
+    .m02_axis_tvalid(axis_adc[6].tvalid),
+    .m02_axis_tready(axis_adc[6].tready),
+
+    .m1_axis_aresetn(!axis_rfdc_rst),
+    .m1_axis_aclk(axis_rfdc_clk),
+    .m10_axis_tdata(axis_adc[5].tdata),
+    .m10_axis_tvalid(axis_adc[5].tvalid),
+    .m10_axis_tready(axis_adc[5].tready),
+    .m12_axis_tdata(axis_adc[4].tdata),
+    .m12_axis_tvalid(axis_adc[4].tvalid),
+    .m12_axis_tready(axis_adc[4].tready),
+
+    .m2_axis_aresetn(!axis_rfdc_rst),
+    .m2_axis_aclk(axis_rfdc_clk),
+    .m20_axis_tdata(axis_adc[3].tdata),
+    .m20_axis_tvalid(axis_adc[3].tvalid),
+    .m20_axis_tready(axis_adc[3].tready),
+    .m22_axis_tdata(axis_adc[2].tdata),
+    .m22_axis_tvalid(axis_adc[2].tvalid),
+    .m22_axis_tready(axis_adc[2].tready),
+
+    .m3_axis_aresetn(!axis_rfdc_rst),
+    .m3_axis_aclk(axis_rfdc_clk),
+    .m30_axis_tdata(axis_adc[1].tdata),
+    .m30_axis_tvalid(axis_adc[1].tvalid),
+    .m30_axis_tready(axis_adc[1].tready),
+    .m32_axis_tdata(axis_adc[0].tdata),
+    .m32_axis_tvalid(axis_adc[0].tvalid),
+    .m32_axis_tready(axis_adc[0].tready),
+
+    .adc0_01_dsa_code(5'd27),
+    .adc0_23_dsa_code(5'd27),
+    .adc0_dsa_update(1'b0),
+    .adc1_01_dsa_code(5'd27),
+    .adc1_23_dsa_code(5'd27),
+    .adc1_dsa_update(1'b0),
+    .adc2_01_dsa_code(5'd27),
+    .adc2_23_dsa_code(5'd27),
+    .adc2_dsa_update(1'b0),
+    .adc3_01_dsa_code(5'd27),
+    .adc3_23_dsa_code(5'd27),
+    .adc3_dsa_update(1'b0),
+
+    // DAC
+    .dac2_clk_p(dac_refclk_1_p),
+    .dac2_clk_n(dac_refclk_1_n),
+
+    .clk_dac0(dac_clk_out[0]),
+    .clk_dac1(dac_clk_out[1]),
+    .clk_dac2(dac_clk_out[2]),
+    .clk_dac3(dac_clk_out[3]),
+
+    .vout00_p(dac_vout_p[7]),
+    .vout00_n(dac_vout_n[7]),
+    .vout02_p(dac_vout_p[6]),
+    .vout02_n(dac_vout_n[6]),
+
+    .vout10_p(dac_vout_p[5]),
+    .vout10_n(dac_vout_n[5]),
+    .vout12_p(dac_vout_p[4]),
+    .vout12_n(dac_vout_n[4]),
+
+    .vout20_p(dac_vout_p[3]),
+    .vout20_n(dac_vout_n[3]),
+    .vout22_p(dac_vout_p[2]),
+    .vout22_n(dac_vout_n[2]),
+
+    .vout30_p(dac_vout_p[1]),
+    .vout30_n(dac_vout_n[1]),
+    .vout32_p(dac_vout_p[0]),
+    .vout32_n(dac_vout_n[0]),
+
+    .s0_axis_aresetn(!axis_rfdc_rst),
+    .s0_axis_aclk(axis_rfdc_clk),
+    .s00_axis_tdata(axis_dac[7].tdata),
+    .s00_axis_tvalid(axis_dac[7].tvalid),
+    .s00_axis_tready(axis_dac[7].tready),
+    .s02_axis_tdata(axis_dac[6].tdata),
+    .s02_axis_tvalid(axis_dac[6].tvalid),
+    .s02_axis_tready(axis_dac[6].tready),
+
+    .s1_axis_aresetn(!axis_rfdc_rst),
+    .s1_axis_aclk(axis_rfdc_clk),
+    .s10_axis_tdata(axis_dac[5].tdata),
+    .s10_axis_tvalid(axis_dac[5].tvalid),
+    .s10_axis_tready(axis_dac[5].tready),
+    .s12_axis_tdata(axis_dac[4].tdata),
+    .s12_axis_tvalid(axis_dac[4].tvalid),
+    .s12_axis_tready(axis_dac[4].tready),
+
+    .s2_axis_aresetn(!axis_rfdc_rst),
+    .s2_axis_aclk(axis_rfdc_clk),
+    .s20_axis_tdata(axis_dac[3].tdata),
+    .s20_axis_tvalid(axis_dac[3].tvalid),
+    .s20_axis_tready(axis_dac[3].tready),
+    .s22_axis_tdata(axis_dac[2].tdata),
+    .s22_axis_tvalid(axis_dac[2].tvalid),
+    .s22_axis_tready(axis_dac[2].tready),
+
+    .s3_axis_aresetn(!axis_rfdc_rst),
+    .s3_axis_aclk(axis_rfdc_clk),
+    .s30_axis_tdata(axis_dac[1].tdata),
+    .s30_axis_tvalid(axis_dac[1].tvalid),
+    .s30_axis_tready(axis_dac[1].tready),
+    .s32_axis_tdata(axis_dac[0].tdata),
+    .s32_axis_tvalid(axis_dac[0].tvalid),
+    .s32_axis_tready(axis_dac[0].tready),
+
+    .dac00_vop_code(10'd895),
+    .dac02_vop_code(10'd895),
+    .dac00_update_vop(1'b0),
+    .dac02_update_vop(1'b0),
+    .dac00_vop_done(),
+    .dac02_vop_done(),
+    .dac0_vop_busy(),
+
+    .dac10_vop_code(10'd895),
+    .dac12_vop_code(10'd895),
+    .dac10_update_vop(1'b0),
+    .dac12_update_vop(1'b0),
+    .dac10_vop_done(),
+    .dac12_vop_done(),
+    .dac1_vop_busy(),
+
+    .dac20_vop_code(10'd895),
+    .dac22_vop_code(10'd895),
+    .dac20_update_vop(1'b0),
+    .dac22_update_vop(1'b0),
+    .dac20_vop_done(),
+    .dac22_vop_done(),
+    .dac2_vop_busy(),
+
+    .dac30_vop_code(10'd895),
+    .dac32_vop_code(10'd895),
+    .dac30_update_vop(1'b0),
+    .dac32_update_vop(1'b0),
+    .dac30_vop_done(),
+    .dac32_vop_done(),
+    .dac3_vop_busy()
+);
+
+fpga_core #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .PORT_CNT(PORT_CNT),
+    .GTY_QUAD_CNT(GTY_QUAD_CNT),
+    .GTY_CNT(GTY_CNT),
+    .GTY_CLK_CNT(GTY_CLK_CNT),
+    .ADC_CNT(ADC_CNT),
+    .DAC_CNT(DAC_CNT)
+)
+core_inst (
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    .clk_125mhz(clk_125mhz_int),
+    .rst_125mhz(rst_125mhz_int),
+    .fpga_refclk(fpga_refclk_int),
+    .fpga_sysref(fpga_sysref_int),
+
+    /*
+     * GPIO
+     */
+    .sw(sw_int),
+    .led(led),
+    .gpio(),
+
+    /*
+     * I2C for board management
+     */
+    .i2c_scl_i(i2c_int_scl_i),
+    .i2c_scl_o(i2c_int_scl_o),
+    .i2c_sda_i(i2c_int_sda_i),
+    .i2c_sda_o(i2c_int_sda_o),
+
+    /*
+     * UART: 921600 bps, 8N1
+     */
+    .uart_rxd(uart_rxd),
+    .uart_txd(uart_txd_int),
+    .uart_rts(uart_rts_int),
+    .uart_cts(uart_cts),
+    .uart_rst_n(uart_rst_n),
+    .uart_suspend_n(uart_suspend_n),
+
+    /*
+     * Ethernet: QSFP28
+     */
+    .eth_gty_tx_p(fmc_dp_c2m_p),
+    .eth_gty_tx_n(fmc_dp_c2m_n),
+    .eth_gty_rx_p(fmc_dp_m2c_p),
+    .eth_gty_rx_n(fmc_dp_m2c_n),
+    .eth_gty_mgt_refclk_p({fmc_mgt_refclk_1_0_p, fmc_mgt_refclk_0_0_p}),
+    .eth_gty_mgt_refclk_n({fmc_mgt_refclk_1_0_n, fmc_mgt_refclk_0_0_n}),
+    .eth_gty_mgt_refclk_out(),
+
+    .eth_port_resetl(),
+    .eth_port_modprsl('0),
+    .eth_port_intl('1),
+
+    /*
+     * RFDC
+     */
+    .axil_rfdc_clk(axil_rfdc_clk),
+    .axil_rfdc_rst(axil_rfdc_rst),
+    .m_axil_rfdc_wr(axil_rfdc),
+    .m_axil_rfdc_rd(axil_rfdc),
+
+    .axis_rfdc_clk(axis_rfdc_clk),
+    .axis_rfdc_rst(axis_rfdc_rst),
+    .s_axis_adc(axis_adc),
+    .m_axis_dac(axis_dac)
+);
+
+endmodule
+
+`resetall

src/eth/example/HTG_ZRF8/fpga/tb/fpga_core/Makefile

@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = fpga_core
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_SIM := "1'b1"
+export PARAM_VENDOR := "\"XILINX\""
+export PARAM_FAMILY := "\"zynquplusRFSOC\""
+export PARAM_PORT_CNT := 2
+export PARAM_GTY_QUAD_CNT := $(PARAM_PORT_CNT)
+export PARAM_GTY_CNT := $(shell echo $$(( 4 * $(PARAM_GTY_QUAD_CNT) )))
+export PARAM_GTY_CLK_CNT := $(PARAM_GTY_QUAD_CNT)
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/example/HTG_ZRF8/fpga/tb/fpga_core/baser.py

@@ -0,0 +1 @@
+../../lib/taxi/src/eth/tb/baser.py

src/eth/example/HTG_ZRF8/fpga/tb/fpga_core/test_fpga_core.py

@@ -0,0 +1,259 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: MIT
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import logging
+import os
+import sys
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.log import SimLog
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer, Combine
+
+from cocotbext.eth import XgmiiFrame
+from cocotbext.uart import UartSource, UartSink
+
+try:
+    from baser import BaseRSerdesSource, BaseRSerdesSink
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSource, BaseRSerdesSink
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = SimLog("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
+
+        self.uart_source = UartSource(dut.uart_rxd, baud=921600, bits=8, stop_bits=1)
+        self.uart_sink = UartSink(dut.uart_txd, baud=921600, bits=8, stop_bits=1)
+
+        self.qsfp_sources = []
+        self.qsfp_sinks = []
+
+        for inst in dut.uut.gty_quad:
+            for ch in inst.mac_inst.ch:
+                gt_inst = ch.ch_inst.gt.gt_inst
+
+                if ch.ch_inst.CFG_LOW_LATENCY.value:
+                    clk = 2.482
+                    gbx_cfg = (66, [64, 65])
+                else:
+                    clk = 2.56
+                    gbx_cfg = None
+
+                cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
+                cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start())
+
+                self.qsfp_sources.append(BaseRSerdesSource(
+                    data=gt_inst.serdes_rx_data,
+                    data_valid=gt_inst.serdes_rx_data_valid,
+                    hdr=gt_inst.serdes_rx_hdr,
+                    hdr_valid=gt_inst.serdes_rx_hdr_valid,
+                    clock=gt_inst.rx_clk,
+                    slip=gt_inst.serdes_rx_bitslip,
+                    reverse=True,
+                    gbx_cfg=gbx_cfg
+                ))
+                self.qsfp_sinks.append(BaseRSerdesSink(
+                    data=gt_inst.serdes_tx_data,
+                    data_valid=gt_inst.serdes_tx_data_valid,
+                    hdr=gt_inst.serdes_tx_hdr,
+                    hdr_valid=gt_inst.serdes_tx_hdr_valid,
+                    gbx_sync=gt_inst.serdes_tx_gbx_sync,
+                    clock=gt_inst.tx_clk,
+                    reverse=True,
+                    gbx_cfg=gbx_cfg
+                ))
+
+        cocotb.start_soon(Clock(dut.axil_rfdc_clk, 8, units="ns").start())
+        cocotb.start_soon(Clock(dut.axis_rfdc_clk, 4, units="ns").start())
+
+        dut.i2c_scl_i.setimmediatevalue(1)
+        dut.i2c_sda_i.setimmediatevalue(1)
+        dut.sw.setimmediatevalue(0)
+
+        cocotb.start_soon(self._run_refclk())
+
+    async def init(self):
+
+        self.dut.rst_125mhz.setimmediatevalue(0)
+        self.dut.axil_rfdc_rst.setimmediatevalue(0)
+        self.dut.axis_rfdc_rst.setimmediatevalue(0)
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk_125mhz)
+
+        self.dut.rst_125mhz.value = 1
+        self.dut.axil_rfdc_rst.value = 1
+        self.dut.axis_rfdc_rst.value = 1
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk_125mhz)
+
+        self.dut.rst_125mhz.value = 0
+        self.dut.axil_rfdc_rst.value = 0
+        self.dut.axis_rfdc_rst.value = 0
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk_125mhz)
+
+    async def _run_refclk(self):
+        t = Timer(3.102, 'ns')
+        val = 2**len(self.dut.eth_gty_mgt_refclk_p)-1
+        while True:
+            self.dut.eth_gty_mgt_refclk_p.value = val
+            await t
+            self.dut.eth_gty_mgt_refclk_p.value = 0
+            await t
+
+
+async def mac_test(tb, source, sink):
+    tb.log.info("Test MAC")
+
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk_125mhz)
+
+    tb.log.info("Multiple small packets")
+
+    count = 64
+
+    pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(XgmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+
+    tb.log.info("Multiple large packets")
+
+    count = 32
+
+    pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(XgmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+
+    tb.log.info("MAC test done")
+
+
+@cocotb.test()
+async def run_test(dut):
+
+    tb = TB(dut)
+
+    await tb.init()
+
+    tests = []
+
+    for k in range(len(tb.qsfp_sources)):
+        tb.log.info("Start QSFP %d MAC loopback test", k)
+
+        tests.append(cocotb.start_soon(mac_test(tb, tb.qsfp_sources[k], tb.qsfp_sinks[k])))
+
+    await Combine(*tests)
+
+    await RisingEdge(dut.clk_125mhz)
+    await RisingEdge(dut.clk_125mhz)
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_fpga_core(request):
+    dut = "fpga_core"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
+        os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_i2c_master.f"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"),
+        os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
+        os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
+        os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['SIM'] = "1'b1"
+    parameters['VENDOR'] = "\"XILINX\""
+    parameters['FAMILY'] = "\"virtexuplus\""
+    parameters['PORT_CNT'] = 2
+    parameters['GTY_QUAD_CNT'] = parameters['PORT_CNT']
+    parameters['GTY_CNT'] = parameters['GTY_QUAD_CNT']*4
+    parameters['GTY_CLK_CNT'] = parameters['GTY_QUAD_CNT']
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/example/HTG_ZRF8/fpga/tb/fpga_core/test_fpga_core.sv

@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA core logic testbench
+ */
+module test_fpga_core #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter logic SIM = 1'b1,
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "zynquplusRFSOC",
+    parameter PORT_CNT = 2,
+    parameter GTY_QUAD_CNT = PORT_CNT,
+    parameter GTY_CNT = GTY_QUAD_CNT*4,
+    parameter GTY_CLK_CNT = GTY_QUAD_CNT,
+    parameter ADC_CNT = 8,
+    parameter ADC_SAMPLE_W = 16,
+    parameter ADC_SAMPLE_CNT = 4,
+    parameter DAC_CNT = ADC_CNT,
+    parameter DAC_SAMPLE_W = ADC_SAMPLE_W,
+    parameter DAC_SAMPLE_CNT = ADC_SAMPLE_CNT
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam ADC_DATA_W = ADC_SAMPLE_W*ADC_SAMPLE_CNT;
+localparam DAC_DATA_W = DAC_SAMPLE_W*DAC_SAMPLE_CNT;
+
+logic clk_125mhz;
+logic rst_125mhz;
+logic fpga_refclk;
+logic fpga_sysref;
+
+logic [3:0] sw;
+logic [3:0] led;
+logic [7:0] gpio;
+
+logic i2c_scl_i;
+logic i2c_scl_o;
+logic i2c_sda_i;
+logic i2c_sda_o;
+
+logic uart_rxd;
+logic uart_txd;
+logic uart_rts;
+logic uart_cts;
+logic uart_rst_n;
+logic uart_suspend_n;
+
+logic [GTY_CNT-1:0] eth_gty_tx_p;
+logic [GTY_CNT-1:0] eth_gty_tx_n;
+logic [GTY_CNT-1:0] eth_gty_rx_p;
+logic [GTY_CNT-1:0] eth_gty_rx_n;
+logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_p;
+logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_n;
+logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_out;
+
+logic [PORT_CNT-1:0] eth_port_resetl;
+logic [PORT_CNT-1:0] eth_port_modprsl;
+logic [PORT_CNT-1:0] eth_port_intl;
+
+logic axil_rfdc_clk;
+logic axil_rfdc_rst;
+
+taxi_axil_if #(
+    .DATA_W(32),
+    .ADDR_W(18)
+) m_axil_rfdc();
+
+logic axis_rfdc_clk;
+logic axis_rfdc_rst;
+
+taxi_axis_if #(
+    .DATA_W(ADC_DATA_W),
+    .KEEP_EN(1),
+    .KEEP_W(ADC_SAMPLE_CNT),
+    .LAST_EN(0),
+    .USER_EN(0),
+    .ID_EN(0),
+    .DEST_EN(0)
+) s_axis_adc[ADC_CNT]();
+
+taxi_axis_if #(
+    .DATA_W(DAC_DATA_W),
+    .KEEP_EN(1),
+    .KEEP_W(DAC_SAMPLE_CNT),
+    .LAST_EN(0),
+    .USER_EN(0),
+    .ID_EN(0),
+    .DEST_EN(0)
+) m_axis_dac[DAC_CNT]();
+
+fpga_core #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .PORT_CNT(PORT_CNT),
+    .GTY_QUAD_CNT(GTY_QUAD_CNT),
+    .GTY_CNT(GTY_CNT),
+    .GTY_CLK_CNT(GTY_CLK_CNT),
+    .ADC_CNT(ADC_CNT),
+    .DAC_CNT(DAC_CNT)
+)
+uut (
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    .clk_125mhz(clk_125mhz),
+    .rst_125mhz(rst_125mhz),
+    .fpga_refclk(fpga_refclk),
+    .fpga_sysref(fpga_sysref),
+
+    /*
+     * GPIO
+     */
+    .sw(sw),
+    .led(led),
+    .gpio(gpio),
+
+    /*
+     * I2C for board management
+     */
+    .i2c_scl_i(i2c_scl_i),
+    .i2c_scl_o(i2c_scl_o),
+    .i2c_sda_i(i2c_sda_i),
+    .i2c_sda_o(i2c_sda_o),
+
+    /*
+     * UART: 115200 bps, 8N1
+     */
+    .uart_rxd(uart_rxd),
+    .uart_txd(uart_txd),
+    .uart_rts(uart_rts),
+    .uart_cts(uart_cts),
+    .uart_rst_n(uart_rst_n),
+    .uart_suspend_n(uart_suspend_n),
+
+    /*
+     * Ethernet: FMC
+     */
+    .eth_gty_tx_p(eth_gty_tx_p),
+    .eth_gty_tx_n(eth_gty_tx_n),
+    .eth_gty_rx_p(eth_gty_rx_p),
+    .eth_gty_rx_n(eth_gty_rx_n),
+    .eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
+    .eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
+    .eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
+
+    .eth_port_resetl(eth_port_resetl),
+    .eth_port_modprsl(eth_port_modprsl),
+    .eth_port_intl(eth_port_intl),
+
+    /*
+     * RFDC
+     */
+    .axil_rfdc_clk(axil_rfdc_clk),
+    .axil_rfdc_rst(axil_rfdc_rst),
+    .m_axil_rfdc_wr(m_axil_rfdc),
+    .m_axil_rfdc_rd(m_axil_rfdc),
+
+    .axis_rfdc_clk(axis_rfdc_clk),
+    .axis_rfdc_rst(axis_rfdc_rst),
+    .s_axis_adc(s_axis_adc),
+    .m_axis_dac(m_axis_dac)
+);
+
+endmodule
+
+`resetall