bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-09 08:58:40 -08:00
Code Issues Packages Projects Releases Wiki Activity

eth: Add frame length enforcement and additional statistics outputs to taxi_axis_gmii_tx

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-04-05 22:15:39 -07:00
parent 4f45ac950d
commit 5582eddfa8
4 changed files with 286 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

228
rtl/eth/taxi_axis_gmii_tx.sv
View File

@@ -55,14 +55,25 @@ module taxi_axis_gmii_tx #
/*
* Configuration
*/
input wire logic [7:0] cfg_ifg = 8'd12,
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
input wire logic [7:0] cfg_tx_ifg = 8'd12,
input wire logic cfg_tx_enable,
/*
* Status
*/
output wire logic start_packet,
output wire logic error_underflow
output wire logic tx_start_packet,
output wire logic stat_tx_byte,
output wire logic [15:0] stat_tx_pkt_len,
output wire logic stat_tx_pkt_ucast,
output wire logic stat_tx_pkt_mcast,
output wire logic stat_tx_pkt_bcast,
output wire logic stat_tx_pkt_vlan,
output wire logic stat_tx_pkt_good,
output wire logic stat_tx_pkt_bad,
output wire logic stat_tx_err_oversize,
output wire logic stat_tx_err_user,
output wire logic stat_tx_err_underflow
);
localparam USER_W = TX_CPL_CTRL_IN_TUSER ? 2 : 1;
@@ -106,8 +117,16 @@ logic [3:0] mii_msn_reg = 4'b0, mii_msn_next;
logic frame_reg = 1'b0, frame_next;
logic frame_error_reg = 1'b0, frame_error_next;
logic [7:0] frame_ptr_reg = '0, frame_ptr_next;
logic [MIN_LEN_W-1:0] frame_min_count_reg = '0, frame_min_count_next;
logic [3:0] hdr_ptr_reg = '0, hdr_ptr_next;
logic is_mcast_reg = 1'b0, is_mcast_next;
logic is_bcast_reg = 1'b0, is_bcast_next;
logic is_8021q_reg = 1'b0, is_8021q_next;
logic [15:0] frame_len_reg = '0, frame_len_next;
logic [15:0] frame_len_lim_reg = '0, frame_len_lim_next;
logic [1:0] fcs_ptr_reg = '0, fcs_ptr_next;
logic [2:0] pre_cnt_reg = '0, pre_cnt_next;
logic [7:0] ifg_cnt_reg = '0, ifg_cnt_next;
logic [7:0] gmii_txd_reg = 8'd0, gmii_txd_next;
logic gmii_tx_en_reg = 1'b0, gmii_tx_en_next;
@@ -121,7 +140,18 @@ logic m_axis_tx_cpl_valid_reg = 1'b0, m_axis_tx_cpl_valid_next;
logic start_packet_int_reg = 1'b0, start_packet_int_next;
logic start_packet_reg = 1'b0, start_packet_next;
logic error_underflow_reg = 1'b0, error_underflow_next;
logic stat_tx_byte_reg = 1'b0, stat_tx_byte_next;
logic [15:0] stat_tx_pkt_len_reg = '0, stat_tx_pkt_len_next;
logic stat_tx_pkt_ucast_reg = 1'b0, stat_tx_pkt_ucast_next;
logic stat_tx_pkt_mcast_reg = 1'b0, stat_tx_pkt_mcast_next;
logic stat_tx_pkt_bcast_reg = 1'b0, stat_tx_pkt_bcast_next;
logic stat_tx_pkt_vlan_reg = 1'b0, stat_tx_pkt_vlan_next;
logic stat_tx_pkt_good_reg = 1'b0, stat_tx_pkt_good_next;
logic stat_tx_pkt_bad_reg = 1'b0, stat_tx_pkt_bad_next;
logic stat_tx_err_oversize_reg = 1'b0, stat_tx_err_oversize_next;
logic stat_tx_err_user_reg = 1'b0, stat_tx_err_user_next;
logic stat_tx_err_underflow_reg = 1'b0, stat_tx_err_underflow_next;
logic [31:0] crc_state = '1;
wire [31:0] crc_next;
@@ -141,8 +171,18 @@ assign m_axis_tx_cpl.tid = m_axis_tx_cpl_tag_reg;
assign m_axis_tx_cpl.tdest = '0;
assign m_axis_tx_cpl.tuser = '0;
assign start_packet = start_packet_reg;
assign error_underflow = error_underflow_reg;
assign tx_start_packet = start_packet_reg;
assign stat_tx_byte = stat_tx_byte_reg;
assign stat_tx_pkt_len = stat_tx_pkt_len_reg;
assign stat_tx_pkt_ucast = stat_tx_pkt_ucast_reg;
assign stat_tx_pkt_mcast = stat_tx_pkt_mcast_reg;
assign stat_tx_pkt_bcast = stat_tx_pkt_bcast_reg;
assign stat_tx_pkt_vlan = stat_tx_pkt_vlan_reg;
assign stat_tx_pkt_good = stat_tx_pkt_good_reg;
assign stat_tx_pkt_bad = stat_tx_pkt_bad_reg;
assign stat_tx_err_oversize = stat_tx_err_oversize_reg;
assign stat_tx_err_user = stat_tx_err_user_reg;
assign stat_tx_err_underflow = stat_tx_err_underflow_reg;
taxi_lfsr #(
.LFSR_W(32),
@@ -170,8 +210,16 @@ always_comb begin
frame_next = frame_reg;
frame_error_next = frame_error_reg;
frame_ptr_next = frame_ptr_reg;
frame_min_count_next = frame_min_count_reg;
hdr_ptr_next = hdr_ptr_reg;
is_mcast_next = is_mcast_reg;
is_bcast_next = is_bcast_reg;
is_8021q_next = is_8021q_reg;
frame_len_next = frame_len_reg;
frame_len_lim_next = frame_len_lim_reg;
fcs_ptr_next = fcs_ptr_reg;
pre_cnt_next = pre_cnt_reg;
ifg_cnt_next = ifg_cnt_reg;
s_axis_tx_tready_next = 1'b0;
@@ -197,7 +245,18 @@ always_comb begin
start_packet_int_next = start_packet_int_reg;
start_packet_next = 1'b0;
error_underflow_next = 1'b0;
stat_tx_byte_next = 1'b0;
stat_tx_pkt_len_next = '0;
stat_tx_pkt_ucast_next = 1'b0;
stat_tx_pkt_mcast_next = 1'b0;
stat_tx_pkt_bcast_next = 1'b0;
stat_tx_pkt_vlan_next = 1'b0;
stat_tx_pkt_good_next = 1'b0;
stat_tx_pkt_bad_next = 1'b0;
stat_tx_err_oversize_next = 1'b0;
stat_tx_err_user_next = 1'b0;
stat_tx_err_underflow_next = 1'b0;
if (s_axis_tx.tvalid && s_axis_tx.tready) begin
frame_next = !s_axis_tx.tlast;
@@ -221,17 +280,72 @@ always_comb begin
start_packet_next = 1'b1;
end
end else begin
// counter for min frame length enforcement
if (frame_min_count_reg != 0) begin
frame_min_count_next = frame_min_count_reg - 1;
end
// counter to measure frame length
if (&frame_len_reg == 0) begin
frame_len_next = frame_len_reg + 1;
end
// counter for max frame length enforcement
if (frame_len_lim_reg != 0) begin
frame_len_lim_next = frame_len_lim_reg - 1;
end
// address and ethertype checks
if (&hdr_ptr_reg == 0) begin
hdr_ptr_next = hdr_ptr_reg + 1;
end
case (hdr_ptr_reg)
4'd0: begin
is_mcast_next = s_tdata_reg[0];
is_bcast_next = s_tdata_reg == 8'hff;
end
4'd1: is_bcast_next = is_bcast_reg && s_tdata_reg == 8'hff;
4'd2: is_bcast_next = is_bcast_reg && s_tdata_reg == 8'hff;
4'd3: is_bcast_next = is_bcast_reg && s_tdata_reg == 8'hff;
4'd4: is_bcast_next = is_bcast_reg && s_tdata_reg == 8'hff;
4'd5: is_bcast_next = is_bcast_reg && s_tdata_reg == 8'hff;
4'd12: is_8021q_next = s_tdata_reg == 8'h81;
4'd13: is_8021q_next = is_8021q_reg && s_tdata_reg == 8'h00;
default: begin
// do nothing
end
endcase
if (&fcs_ptr_reg == 0) begin
fcs_ptr_next = fcs_ptr_reg + 1;
end
if (pre_cnt_reg != 0) begin
pre_cnt_next = pre_cnt_reg - 1;
end
if (ifg_cnt_reg != 0) begin
ifg_cnt_next = ifg_cnt_reg - 1;
end
case (state_reg)
STATE_IDLE: begin
// idle state - wait for packet
reset_crc = 1'b1;
mii_odd_next = 1'b0;
frame_ptr_next = 1;
hdr_ptr_next = 0;
frame_len_next = 1;
frame_len_lim_next = cfg_tx_max_pkt_len;
pre_cnt_next = 3'd6;
frame_error_next = 1'b0;
frame_min_count_next = MIN_LEN_W'(MIN_FRAME_LEN-4-1);
gmii_txd_next = '0;
gmii_tx_en_next = 1'b0;
if (s_axis_tx.tvalid && cfg_tx_enable) begin
mii_odd_next = 1'b1;
gmii_txd_next = ETH_PRE;
@@ -246,18 +360,23 @@ always_comb begin
reset_crc = 1'b1;
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 1;
hdr_ptr_next = 0;
frame_len_next = 1;
frame_len_lim_next = cfg_tx_max_pkt_len;
frame_error_next = 1'b0;
frame_min_count_next = MIN_LEN_W'(MIN_FRAME_LEN-4-1);
gmii_txd_next = ETH_PRE;
gmii_tx_en_next = 1'b1;
if (frame_ptr_reg == 6) begin
if (pre_cnt_reg == 1) begin
s_axis_tx_tready_next = 1'b1;
s_tdata_next = s_axis_tx.tdata;
state_next = STATE_PREAMBLE;
end else if (frame_ptr_reg == 7) begin
end else if (pre_cnt_reg == 0) begin
// end of preamble; start payload
frame_ptr_next = '0;
stat_tx_byte_next = 1'b1;
if (s_axis_tx_tready_reg) begin
s_axis_tx_tready_next = 1'b1;
s_tdata_next = s_axis_tx.tdata;
@@ -281,19 +400,18 @@ always_comb begin
mii_odd_next = 1'b1;
if (frame_min_count_reg != 0) begin
frame_min_count_next = frame_min_count_reg - 1;
end
gmii_txd_next = s_tdata_reg;
gmii_tx_en_next = 1'b1;
s_tdata_next = s_axis_tx.tdata;
if (!s_axis_tx.tvalid || s_axis_tx.tlast) begin
stat_tx_byte_next = 1'b1;
if (!s_axis_tx.tvalid || s_axis_tx.tlast || frame_len_lim_reg < 6) begin
s_axis_tx_tready_next = frame_next; // drop frame
frame_error_next = !s_axis_tx.tvalid || s_axis_tx.tuser[0];
error_underflow_next = !s_axis_tx.tvalid;
frame_error_next = !s_axis_tx.tvalid || s_axis_tx.tuser[0] || frame_len_lim_reg < 6;
stat_tx_err_user_next = s_axis_tx.tuser[0];
stat_tx_err_underflow_next = !s_axis_tx.tvalid;
state_next = STATE_LAST;
end else begin
@@ -307,16 +425,18 @@ always_comb begin
s_axis_tx_tready_next = frame_next; // drop frame
mii_odd_next = 1'b1;
fcs_ptr_next = 2'd0;
gmii_txd_next = s_tdata_reg;
gmii_tx_en_next = 1'b1;
gmii_tx_er_next = frame_error_reg;
stat_tx_byte_next = 1'b1;
if (PADDING_EN && frame_min_count_reg != 0) begin
frame_min_count_next = frame_min_count_reg - 1;
s_tdata_next = 8'd0;
state_next = STATE_PAD;
end else begin
frame_ptr_next = '0;
state_next = STATE_FCS;
end
end
@@ -326,17 +446,19 @@ always_comb begin
update_crc = 1'b1;
mii_odd_next = 1'b1;
fcs_ptr_next = 2'd0;
gmii_txd_next = 8'd0;
gmii_txd_next = s_tdata_reg;
gmii_tx_en_next = 1'b1;
gmii_tx_er_next = frame_error_reg;
s_tdata_next = 8'd0;
stat_tx_byte_next = 1'b1;
if (frame_min_count_reg != 0) begin
frame_min_count_next = frame_min_count_reg - 1;
state_next = STATE_PAD;
end else begin
frame_ptr_next = '0;
state_next = STATE_FCS;
end
end
@@ -345,9 +467,9 @@ always_comb begin
s_axis_tx_tready_next = frame_next; // drop frame
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 1;
ifg_cnt_next = cfg_tx_ifg;
case (frame_ptr_reg[1:0])
case (fcs_ptr_reg)
2'd0: gmii_txd_next = ~crc_state[7:0];
2'd1: gmii_txd_next = ~crc_state[15:8];
2'd2: gmii_txd_next = ~crc_state[23:16];
@@ -356,10 +478,19 @@ always_comb begin
gmii_tx_en_next = 1'b1;
gmii_tx_er_next = frame_error_reg;
if (frame_ptr_reg < 3) begin
stat_tx_byte_next = 1'b1;
if (&fcs_ptr_reg == 0) begin
state_next = STATE_FCS;
end else begin
frame_ptr_next = '0;
stat_tx_pkt_len_next = frame_len_reg;
stat_tx_pkt_good_next = !frame_error_reg;
stat_tx_pkt_bad_next = frame_error_reg;
stat_tx_pkt_ucast_next = !is_mcast_reg;
stat_tx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_tx_pkt_bcast_next = is_bcast_reg;
stat_tx_pkt_vlan_next = is_8021q_reg;
stat_tx_err_oversize_next = frame_len_lim_reg == 0;
state_next = STATE_IFG;
end
end
@@ -368,9 +499,8 @@ always_comb begin
s_axis_tx_tready_next = frame_next; // drop frame
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 1;
if (frame_ptr_reg < cfg_ifg-1 || frame_reg) begin
if (ifg_cnt_reg[7:1] != 0 || frame_reg) begin
state_next = STATE_IFG;
end else begin
state_next = STATE_IDLE;
@@ -394,8 +524,16 @@ always_ff @(posedge clk) begin
frame_reg <= frame_next;
frame_error_reg <= frame_error_next;
frame_ptr_reg <= frame_ptr_next;
frame_min_count_reg <= frame_min_count_next;
hdr_ptr_reg <= hdr_ptr_next;
is_mcast_reg <= is_mcast_next;
is_bcast_reg <= is_bcast_next;
is_8021q_reg <= is_8021q_next;
frame_len_reg <= frame_len_next;
frame_len_lim_reg <= frame_len_lim_next;
fcs_ptr_reg <= fcs_ptr_next;
pre_cnt_reg <= pre_cnt_next;
ifg_cnt_reg <= ifg_cnt_next;
m_axis_tx_cpl_ts_reg <= m_axis_tx_cpl_ts_next;
m_axis_tx_cpl_tag_reg <= m_axis_tx_cpl_tag_next;
@@ -420,7 +558,17 @@ always_ff @(posedge clk) begin
start_packet_int_reg <= start_packet_int_next;
start_packet_reg <= start_packet_next;
error_underflow_reg <= error_underflow_next;
stat_tx_byte_reg <= stat_tx_byte_next;
stat_tx_pkt_len_reg <= stat_tx_pkt_len_next;
stat_tx_pkt_ucast_reg <= stat_tx_pkt_ucast_next;
stat_tx_pkt_mcast_reg <= stat_tx_pkt_mcast_next;
stat_tx_pkt_bcast_reg <= stat_tx_pkt_bcast_next;
stat_tx_pkt_vlan_reg <= stat_tx_pkt_vlan_next;
stat_tx_pkt_good_reg <= stat_tx_pkt_good_next;
stat_tx_pkt_bad_reg <= stat_tx_pkt_bad_next;
stat_tx_err_oversize_reg <= stat_tx_err_oversize_next;
stat_tx_err_user_reg <= stat_tx_err_user_next;
stat_tx_err_underflow_reg <= stat_tx_err_underflow_next;
if (rst) begin
state_reg <= STATE_IDLE;
@@ -436,7 +584,17 @@ always_ff @(posedge clk) begin
start_packet_int_reg <= 1'b0;
start_packet_reg <= 1'b0;
error_underflow_reg <= 1'b0;
stat_tx_byte_reg <= 1'b0;
stat_tx_pkt_len_reg <= '0;
stat_tx_pkt_ucast_reg <= 1'b0;
stat_tx_pkt_mcast_reg <= 1'b0;
stat_tx_pkt_bcast_reg <= 1'b0;
stat_tx_pkt_vlan_reg <= 1'b0;
stat_tx_pkt_good_reg <= 1'b0;
stat_tx_pkt_bad_reg <= 1'b0;
stat_tx_err_oversize_reg <= 1'b0;
stat_tx_err_user_reg <= 1'b0;
stat_tx_err_underflow_reg <= 1'b0;
end
end