eth: Add frame length enforcement and additional statistics outputs to taxi_axis_gmii_tx

Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-04-05 22:15:39 -07:00
parent 4f45ac950d
commit 5582eddfa8
4 changed files with 286 additions and 49 deletions

View File

@@ -46,7 +46,8 @@ class TB:
dut.clk_enable.setimmediatevalue(1)
dut.mii_select.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
dut.cfg_tx_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
async def reset(self):
@@ -83,7 +84,8 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_
tb = TB(dut)
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.mii_select.value = mii_sel
@@ -124,7 +126,8 @@ async def run_test_underrun(dut, ifg=12, enable_gen=None, mii_sel=False):
tb = TB(dut)
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.mii_select.value = mii_sel
@@ -175,7 +178,8 @@ async def run_test_error(dut, ifg=12, enable_gen=None, mii_sel=False):
tb = TB(dut)
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.mii_select.value = mii_sel
@@ -208,6 +212,44 @@ async def run_test_error(dut, ifg=12, enable_gen=None, mii_sel=False):
await RisingEdge(dut.clk)
async def run_test_oversize(dut, ifg=12, enable_gen=None, mii_sel=False):
tb = TB(dut)
tb.dut.cfg_tx_max_pkt_len.value = 1518
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.mii_select.value = mii_sel
if enable_gen is not None:
tb.set_enable_generator(enable_gen())
await tb.reset()
test_data = bytes(x for x in range(60))
for k in range(3):
test_frame = AxiStreamFrame(test_data)
if k == 1:
test_frame = AxiStreamFrame(bytes(x % 256 for x in range(1515)))
await tb.source.send(test_frame)
for k in range(3):
rx_frame = await tb.sink.recv()
if k == 1:
assert rx_frame.error[-1] == 1
else:
assert rx_frame.get_payload() == test_data
assert rx_frame.check_fcs()
assert rx_frame.error is None
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def size_list():
return list(range(60, 128)) + [512, 1514] + [60]*10
@@ -230,7 +272,11 @@ if cocotb.SIM_NAME:
factory.add_option("mii_sel", [False, True])
factory.generate_tests()
for test in [run_test_underrun, run_test_error]:
for test in [
run_test_underrun,
run_test_error,
run_test_oversize,
]:
factory = TestFactory(test)
factory.add_option("ifg", [12])

View File

@@ -46,11 +46,22 @@ logic [PTP_TS_W-1:0] ptp_ts;
logic clk_enable;
logic mii_select;
logic [7:0] cfg_ifg;
logic [15:0] cfg_tx_max_pkt_len;
logic [7:0] cfg_tx_ifg;
logic cfg_tx_enable;
logic start_packet;
logic error_underflow;
logic tx_start_packet;
logic stat_tx_byte;
logic [15:0] stat_tx_pkt_len;
logic stat_tx_pkt_ucast;
logic stat_tx_pkt_mcast;
logic stat_tx_pkt_bcast;
logic stat_tx_pkt_vlan;
logic stat_tx_pkt_good;
logic stat_tx_pkt_bad;
logic stat_tx_err_oversize;
logic stat_tx_err_user;
logic stat_tx_err_underflow;
taxi_axis_gmii_tx #(
.DATA_W(DATA_W),
@@ -91,14 +102,25 @@ uut (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
/*
* Status
*/
.start_packet(start_packet),
.error_underflow(error_underflow)
.tx_start_packet(tx_start_packet),
.stat_tx_byte(stat_tx_byte),
.stat_tx_pkt_len(stat_tx_pkt_len),
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
.stat_tx_pkt_good(stat_tx_pkt_good),
.stat_tx_pkt_bad(stat_tx_pkt_bad),
.stat_tx_err_oversize(stat_tx_err_oversize),
.stat_tx_err_user(stat_tx_err_user),
.stat_tx_err_underflow(stat_tx_err_underflow)
);
endmodule