From 56215865da00d1636be584e950e794fb0f6f517e Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 6 Mar 2025 16:16:29 -0800 Subject: [PATCH] axi: Normalize unpacked dimension Signed-off-by: Alex Forencich --- rtl/axi/taxi_axi_ram.sv | 2 +- rtl/axi/taxi_axil_dp_ram.sv | 4 ++-- rtl/axi/taxi_axil_ram.sv | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/rtl/axi/taxi_axi_ram.sv b/rtl/axi/taxi_axi_ram.sv index afee68c..2b212fd 100644 --- a/rtl/axi/taxi_axi_ram.sv +++ b/rtl/axi/taxi_axi_ram.sv @@ -98,7 +98,7 @@ logic s_axi_rlast_pipe_reg = 1'b0; logic s_axi_rvalid_pipe_reg = 1'b0; // (* RAM_STYLE="BLOCK" *) -logic [DATA_W-1:0] mem[(2**VALID_ADDR_W)-1:0]; +logic [DATA_W-1:0] mem[2**VALID_ADDR_W]; wire [VALID_ADDR_W-1:0] read_addr_valid = VALID_ADDR_W'(read_addr_reg >> (ADDR_W - VALID_ADDR_W)); wire [VALID_ADDR_W-1:0] write_addr_valid = VALID_ADDR_W'(write_addr_reg >> (ADDR_W - VALID_ADDR_W)); diff --git a/rtl/axi/taxi_axil_dp_ram.sv b/rtl/axi/taxi_axil_dp_ram.sv index 576e753..f838f34 100644 --- a/rtl/axi/taxi_axil_dp_ram.sv +++ b/rtl/axi/taxi_axil_dp_ram.sv @@ -94,9 +94,9 @@ logic s_axil_b_rvalid_reg = 1'b0, s_axil_b_rvalid_next; logic [DATA_W-1:0] s_axil_b_rdata_pipe_reg = '0; logic s_axil_b_rvalid_pipe_reg = 1'b0; -// (* RAM_STYLE="BLOCK" *) // verilator lint_off MULTIDRIVEN -logic [DATA_W-1:0] mem[(2**VALID_ADDR_W)-1:0]; +// (* RAM_STYLE="BLOCK" *) +logic [DATA_W-1:0] mem[2**VALID_ADDR_W]; // verilator lint_on MULTIDRIVEN wire [VALID_ADDR_W-1:0] s_axil_a_awaddr_valid = VALID_ADDR_W'(s_axil_wr_a.awaddr >> (ADDR_W - VALID_ADDR_W)); diff --git a/rtl/axi/taxi_axil_ram.sv b/rtl/axi/taxi_axil_ram.sv index 41d2c31..106a2a3 100644 --- a/rtl/axi/taxi_axil_ram.sv +++ b/rtl/axi/taxi_axil_ram.sv @@ -67,7 +67,7 @@ logic [DATA_W-1:0] s_axil_rdata_pipe_reg = '0; logic s_axil_rvalid_pipe_reg = 1'b0; // (* RAM_STYLE="BLOCK" *) -logic [DATA_W-1:0] mem[(2**VALID_ADDR_W)-1:0]; +logic [DATA_W-1:0] mem[2**VALID_ADDR_W]; wire [VALID_ADDR_W-1:0] s_axil_awaddr_valid = VALID_ADDR_W'(s_axil_wr.awaddr >> (ADDR_W - VALID_ADDR_W)); wire [VALID_ADDR_W-1:0] s_axil_araddr_valid = VALID_ADDR_W'(s_axil_rd.araddr >> (ADDR_W - VALID_ADDR_W));