axi: Add AXI RAM interface and AXI dual port RAM

Signed-off-by: Alex Forencich <alex@alexforencich.com>
2026-04-07 04:38:42 -07:00 · 2026-03-19 18:12:37 -07:00
parent 9a352ae302
commit 5652bb0016
10 changed files with 1399 additions and 0 deletions
--- a/README.md
+++ b/README.md
@@ -91,6 +91,8 @@ The Taxi transport library contains many smaller components that can be composed
    *  Width converter
    *  Synchronous FIFO
    *  Single-port RAM
+    *  Dual-port RAM
+    *  RAM interface
 *  AXI lite
    *  SV interface for AXI lite
    *  AXI lite to AXI adapter