From 56a3c9f1bab83284722cd69bd27dc85e1c8fe391 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 28 Feb 2025 23:24:40 -0800 Subject: [PATCH] axis: Add AXI stream arbitrated multiplexer module and testbench Signed-off-by: Alex Forencich --- rtl/axis/taxi_axis_arb_mux.f | 4 + rtl/axis/taxi_axis_arb_mux.sv | 306 +++++++++++++++ tb/axis/taxi_axis_arb_mux/Makefile | 61 +++ .../test_taxi_axis_arb_mux.py | 363 ++++++++++++++++++ .../test_taxi_axis_arb_mux.sv | 95 +++++ 5 files changed, 829 insertions(+) create mode 100644 rtl/axis/taxi_axis_arb_mux.f create mode 100644 rtl/axis/taxi_axis_arb_mux.sv create mode 100644 tb/axis/taxi_axis_arb_mux/Makefile create mode 100644 tb/axis/taxi_axis_arb_mux/test_taxi_axis_arb_mux.py create mode 100644 tb/axis/taxi_axis_arb_mux/test_taxi_axis_arb_mux.sv diff --git a/rtl/axis/taxi_axis_arb_mux.f b/rtl/axis/taxi_axis_arb_mux.f new file mode 100644 index 0000000..ef7656d --- /dev/null +++ b/rtl/axis/taxi_axis_arb_mux.f @@ -0,0 +1,4 @@ +taxi_axis_arb_mux.sv +taxi_axis_if.sv +../prim/taxi_arbiter.sv +../prim/taxi_penc.sv diff --git a/rtl/axis/taxi_axis_arb_mux.sv b/rtl/axis/taxi_axis_arb_mux.sv new file mode 100644 index 0000000..c72a215 --- /dev/null +++ b/rtl/axis/taxi_axis_arb_mux.sv @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2014-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4-Stream arbitrated multiplexer + */ +module taxi_axis_arb_mux # +( + // Number of AXI stream inputs + parameter S_COUNT = 4, + // Update tid with routing information + parameter logic UPDATE_TID = 1'b0, + // select round robin arbitration + parameter logic ARB_ROUND_ROBIN = 1'b0, + // LSB priority selection + parameter logic ARB_LSB_HIGH_PRIO = 1'b1 +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4-Stream inputs (sink) + */ + taxi_axis_if.snk s_axis[S_COUNT], + + /* + * AXI4-Stream output (source) + */ + taxi_axis_if.src m_axis +); + +// extract parameters +localparam DATA_W = s_axis.DATA_W; +localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN; +localparam KEEP_W = s_axis.KEEP_W; +localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN; +localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN; +localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN; +localparam S_ID_W = s_axis.ID_W; +localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN; +localparam DEST_W = s_axis.DEST_W; +localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN; +localparam USER_W = s_axis.USER_W; + +localparam M_ID_W = m_axis.ID_W; + +localparam CL_S_COUNT = $clog2(S_COUNT); + +localparam S_ID_W_INT = S_ID_W > 0 ? S_ID_W : 1; + +// check configuration +if (UPDATE_TID) begin + if (!ID_EN) + $fatal(0, "Error: UPDATE_TID set requires ID_EN set (instance %m)"); + + if (M_ID_W < CL_S_COUNT) + $fatal(0, "Error: M_ID_W too small for port count (instance %m)"); +end + +// internal datapath +logic [DATA_W-1:0] m_axis_tdata_int; +logic [KEEP_W-1:0] m_axis_tkeep_int; +logic [KEEP_W-1:0] m_axis_tstrb_int; +logic m_axis_tvalid_int; +logic m_axis_tready_int_reg = 1'b0; +logic m_axis_tlast_int; +logic [M_ID_W-1:0] m_axis_tid_int; +logic [DEST_W-1:0] m_axis_tdest_int; +logic [USER_W-1:0] m_axis_tuser_int; +wire m_axis_tready_int_early; + +if (S_COUNT == 1) begin + // degenerate case + + assign s_axis[0].tready = m_axis_tready_int_reg; + + always_comb begin + // pass through selected packet data + m_axis_tdata_int = s_axis[0].tdata; + m_axis_tkeep_int = s_axis[0].tkeep; + m_axis_tstrb_int = s_axis[0].tstrb; + m_axis_tvalid_int = s_axis[0].tvalid && m_axis_tready_int_reg; + m_axis_tlast_int = s_axis[0].tlast; + m_axis_tid_int = M_ID_W'(s_axis[0].tid); + m_axis_tdest_int = s_axis[0].tdest; + m_axis_tuser_int = s_axis[0].tuser; + end + +end else begin + + wire [S_COUNT-1:0] req; + wire [S_COUNT-1:0] ack; + wire [S_COUNT-1:0] grant; + wire grant_valid; + wire [CL_S_COUNT-1:0] grant_index; + + // input registers to pipeline arbitration delay + logic [DATA_W-1:0] s_axis_tdata_reg[S_COUNT] = '{S_COUNT{'0}}; + logic [KEEP_W-1:0] s_axis_tkeep_reg[S_COUNT] = '{S_COUNT{'0}}; + logic [KEEP_W-1:0] s_axis_tstrb_reg[S_COUNT] = '{S_COUNT{'0}}; + logic [S_COUNT-1:0] s_axis_tvalid_reg = '0; + logic [S_COUNT-1:0] s_axis_tlast_reg = '0; + logic [S_ID_W-1:0] s_axis_tid_reg[S_COUNT] = '{S_COUNT{'0}}; + logic [DEST_W-1:0] s_axis_tdest_reg[S_COUNT] = '{S_COUNT{'0}}; + logic [USER_W-1:0] s_axis_tuser_reg[S_COUNT] = '{S_COUNT{'0}}; + + // unpack interface array + wire [S_COUNT-1:0] s_axis_tvalid; + wire [S_COUNT-1:0] s_axis_tready; + + for (genvar n = 0; n < S_COUNT; n = n + 1) begin + assign s_axis_tvalid[n] = s_axis[n].tvalid; + assign s_axis[n].tready = s_axis_tready[n]; + end + + assign s_axis_tready = ~s_axis_tvalid_reg | ({S_COUNT{m_axis_tready_int_reg}} & grant); + + // mux for incoming packet + wire [DATA_W-1:0] current_s_tdata = s_axis_tdata_reg[grant_index]; + wire [KEEP_W-1:0] current_s_tkeep = s_axis_tkeep_reg[grant_index]; + wire [KEEP_W-1:0] current_s_tstrb = s_axis_tstrb_reg[grant_index]; + wire current_s_tvalid = s_axis_tvalid_reg[grant_index]; + wire current_s_tready = s_axis_tready[grant_index]; + wire current_s_tlast = s_axis_tlast_reg[grant_index]; + wire [S_ID_W-1:0] current_s_tid = s_axis_tid_reg[grant_index]; + wire [DEST_W-1:0] current_s_tdest = s_axis_tdest_reg[grant_index]; + wire [USER_W-1:0] current_s_tuser = s_axis_tuser_reg[grant_index]; + + // arbiter instance + taxi_arbiter #( + .PORTS(S_COUNT), + .ARB_ROUND_ROBIN(ARB_ROUND_ROBIN), + .ARB_BLOCK(1'b1), + .ARB_BLOCK_ACK(1'b1), + .LSB_HIGH_PRIO(ARB_LSB_HIGH_PRIO) + ) + arb_inst ( + .clk(clk), + .rst(rst), + .req(req), + .ack(ack), + .grant(grant), + .grant_valid(grant_valid), + .grant_index(grant_index) + ); + + assign req = s_axis_tvalid | (s_axis_tvalid_reg & ~grant); + assign ack = grant & s_axis_tvalid_reg & {S_COUNT{m_axis_tready_int_reg}} & (LAST_EN ? s_axis_tlast_reg : {S_COUNT{1'b1}}); + + always_comb begin + // pass through selected packet data + m_axis_tdata_int = current_s_tdata; + m_axis_tkeep_int = current_s_tkeep; + m_axis_tstrb_int = current_s_tstrb; + m_axis_tvalid_int = current_s_tvalid && m_axis_tready_int_reg && grant_valid; + m_axis_tlast_int = current_s_tlast; + m_axis_tid_int = M_ID_W'(current_s_tid); + if (UPDATE_TID && S_COUNT > 1) begin + m_axis_tid_int[M_ID_W-1:M_ID_W-CL_S_COUNT] = grant_index; + end + m_axis_tdest_int = current_s_tdest; + m_axis_tuser_int = current_s_tuser; + end + + for (genvar n = 0; n < S_COUNT; n = n + 1) begin + always_ff @(posedge clk) begin + // register inputs + if (s_axis_tready[n]) begin + s_axis_tdata_reg[n] <= s_axis[n].tdata; + s_axis_tkeep_reg[n] <= s_axis[n].tkeep; + s_axis_tstrb_reg[n] <= s_axis[n].tstrb; + s_axis_tvalid_reg[n] <= s_axis[n].tvalid; + s_axis_tlast_reg[n] <= s_axis[n].tlast; + s_axis_tid_reg[n] <= s_axis[n].tid; + s_axis_tdest_reg[n] <= s_axis[n].tdest; + s_axis_tuser_reg[n] <= s_axis[n].tuser; + end + + if (rst) begin + s_axis_tvalid_reg[n] <= 1'b0; + end + end + end + +end + +// output datapath logic +logic [DATA_W-1:0] m_axis_tdata_reg = '0; +logic [KEEP_W-1:0] m_axis_tkeep_reg = '0; +logic [KEEP_W-1:0] m_axis_tstrb_reg = '0; +logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; +logic m_axis_tlast_reg = 1'b0; +logic [M_ID_W-1:0] m_axis_tid_reg = '0; +logic [DEST_W-1:0] m_axis_tdest_reg = '0; +logic [USER_W-1:0] m_axis_tuser_reg = '0; + +logic [DATA_W-1:0] temp_m_axis_tdata_reg = '0; +logic [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0; +logic [KEEP_W-1:0] temp_m_axis_tstrb_reg = '0; +logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next; +logic temp_m_axis_tlast_reg = 1'b0; +logic [M_ID_W-1:0] temp_m_axis_tid_reg = '0; +logic [DEST_W-1:0] temp_m_axis_tdest_reg = '0; +logic [USER_W-1:0] temp_m_axis_tuser_reg = '0; + +// datapath control +logic store_axis_int_to_output; +logic store_axis_int_to_temp; +logic store_axis_temp_to_output; + +assign m_axis.tdata = m_axis_tdata_reg; +assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1; +assign m_axis.tstrb = STRB_EN ? m_axis_tstrb_reg : m_axis.tkeep; +assign m_axis.tvalid = m_axis_tvalid_reg; +assign m_axis.tlast = LAST_EN ? m_axis_tlast_reg : 1'b1; +assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0; +assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0; +assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0; + +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); + +always_comb begin + // transfer sink ready state to source + m_axis_tvalid_next = m_axis_tvalid_reg; + temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg; + + store_axis_int_to_output = 1'b0; + store_axis_int_to_temp = 1'b0; + store_axis_temp_to_output = 1'b0; + + if (m_axis_tready_int_reg) begin + // input is ready + if (m_axis.tready || !m_axis_tvalid_reg) begin + // output is ready or currently not valid, transfer data to output + m_axis_tvalid_next = m_axis_tvalid_int; + store_axis_int_to_output = 1'b1; + end else begin + // output is not ready, store input in temp + temp_m_axis_tvalid_next = m_axis_tvalid_int; + store_axis_int_to_temp = 1'b1; + end + end else if (m_axis.tready) begin + // input is not ready, but output is ready + m_axis_tvalid_next = temp_m_axis_tvalid_reg; + temp_m_axis_tvalid_next = 1'b0; + store_axis_temp_to_output = 1'b1; + end +end + +always_ff @(posedge clk) begin + m_axis_tvalid_reg <= m_axis_tvalid_next; + m_axis_tready_int_reg <= m_axis_tready_int_early; + temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next; + + // datapath + if (store_axis_int_to_output) begin + m_axis_tdata_reg <= m_axis_tdata_int; + m_axis_tkeep_reg <= m_axis_tkeep_int; + m_axis_tstrb_reg <= m_axis_tstrb_int; + m_axis_tlast_reg <= m_axis_tlast_int; + m_axis_tid_reg <= m_axis_tid_int; + m_axis_tdest_reg <= m_axis_tdest_int; + m_axis_tuser_reg <= m_axis_tuser_int; + end else if (store_axis_temp_to_output) begin + m_axis_tdata_reg <= temp_m_axis_tdata_reg; + m_axis_tkeep_reg <= temp_m_axis_tkeep_reg; + m_axis_tstrb_reg <= temp_m_axis_tstrb_reg; + m_axis_tlast_reg <= temp_m_axis_tlast_reg; + m_axis_tid_reg <= temp_m_axis_tid_reg; + m_axis_tdest_reg <= temp_m_axis_tdest_reg; + m_axis_tuser_reg <= temp_m_axis_tuser_reg; + end + + if (store_axis_int_to_temp) begin + temp_m_axis_tdata_reg <= m_axis_tdata_int; + temp_m_axis_tkeep_reg <= m_axis_tkeep_int; + temp_m_axis_tstrb_reg <= m_axis_tstrb_int; + temp_m_axis_tlast_reg <= m_axis_tlast_int; + temp_m_axis_tid_reg <= m_axis_tid_int; + temp_m_axis_tdest_reg <= m_axis_tdest_int; + temp_m_axis_tuser_reg <= m_axis_tuser_int; + end + + if (rst) begin + m_axis_tvalid_reg <= 1'b0; + m_axis_tready_int_reg <= 1'b0; + temp_m_axis_tvalid_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/tb/axis/taxi_axis_arb_mux/Makefile b/tb/axis/taxi_axis_arb_mux/Makefile new file mode 100644 index 0000000..6909cbc --- /dev/null +++ b/tb/axis/taxi_axis_arb_mux/Makefile @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2021-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = taxi_axis_arb_mux +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += ../../../rtl/axis/$(DUT).f + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_S_COUNT := 4 +export PARAM_DATA_W := 8 +export PARAM_KEEP_EN := $(shell expr $(PARAM_DATA_W) \> 8 ) +export PARAM_KEEP_W := $(shell expr \( $(PARAM_DATA_W) + 7 \) / 8 ) +export PARAM_STRB_EN := 0 +export PARAM_LAST_EN := 1 +export PARAM_ID_EN := 1 +export PARAM_S_ID_W := 8 +export PARAM_M_ID_W := $(shell python -c "print($(PARAM_S_ID_W) + ($(PARAM_S_COUNT)-1).bit_length())") +export PARAM_DEST_EN := 1 +export PARAM_DEST_W := 8 +export PARAM_USER_EN := 1 +export PARAM_USER_W := 1 +export PARAM_UPDATE_TID := 1 +export PARAM_ARB_ROUND_ROBIN := 0 +export PARAM_ARB_LSB_HIGH_PRIO := 1 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/tb/axis/taxi_axis_arb_mux/test_taxi_axis_arb_mux.py b/tb/axis/taxi_axis_arb_mux/test_taxi_axis_arb_mux.py new file mode 100644 index 0000000..b292674 --- /dev/null +++ b/tb/axis/taxi_axis_arb_mux/test_taxi_axis_arb_mux.py @@ -0,0 +1,363 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os +import random + +import cocotb_test.simulator +import pytest + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Event +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink + + +class TB(object): + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) + + self.source = [AxiStreamSource(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.s_axis] + self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst) + + def set_idle_generator(self, generator=None): + if generator: + for source in self.source: + source.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.sink.set_pause_generator(generator()) + + async def reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + +async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None, port=0): + + tb = TB(dut) + + id_width = len(tb.source[0].bus.tid) + id_count = 2**id_width + id_mask = id_count-1 + + src_width = (len(tb.source)-1).bit_length() + src_mask = 2**src_width-1 if src_width else 0 + src_shift = id_width-src_width + max_count = 2**src_shift + count_mask = max_count-1 + + cur_id = 1 + + await tb.reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + test_frames = [] + + for test_data in [payload_data(x) for x in payload_lengths()]: + test_frame = AxiStreamFrame(test_data) + test_frame.tid = cur_id | (port << src_shift) + test_frame.tdest = cur_id + + test_frames.append(test_frame) + await tb.source[port].send(test_frame) + + cur_id = (cur_id + 1) % max_count + + for test_frame in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert (rx_frame.tid & id_mask) == test_frame.tid + assert ((rx_frame.tid >> src_shift) & src_mask) == port + assert (rx_frame.tid >> id_width) == port + assert rx_frame.tdest == test_frame.tdest + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_tuser_assert(dut, port=0): + + tb = TB(dut) + + await tb.reset() + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32)) + test_frame = AxiStreamFrame(test_data, tuser=1) + await tb.source[port].send(test_frame) + + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_data + assert rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_arb_test(dut): + + tb = TB(dut) + + byte_lanes = tb.source[0].byte_lanes + id_width = len(tb.source[0].bus.tid) + id_count = 2**id_width + id_mask = id_count-1 + + src_width = (len(tb.source)-1).bit_length() + src_mask = 2**src_width-1 if src_width else 0 + src_shift = id_width-src_width + max_count = 2**src_shift + count_mask = max_count-1 + + cur_id = 1 + + await tb.reset() + + test_frames = [] + + length = byte_lanes*16 + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + for k in range(5): + test_frame = AxiStreamFrame(test_data, tx_complete=Event()) + + src_ind = 0 + + if k == 0: + src_ind = 0 + elif k == 4: + await test_frames[1].tx_complete.wait() + for j in range(8): + await RisingEdge(dut.clk) + src_ind = 0 + else: + src_ind = 1 + + test_frame.tid = cur_id | (src_ind << src_shift) + test_frame.tdest = 0 + + test_frames.append(test_frame) + await tb.source[src_ind].send(test_frame) + + cur_id = (cur_id + 1) % max_count + + for k in [0, 1, 2, 4, 3]: + test_frame = test_frames[k] + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert (rx_frame.tid & id_mask) == test_frame.tid + assert ((rx_frame.tid >> src_shift) & src_mask) == (rx_frame.tid >> id_width) + assert rx_frame.tdest == test_frame.tdest + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + byte_lanes = tb.source[0].byte_lanes + id_width = len(tb.source[0].bus.tid) + id_count = 2**id_width + id_mask = id_count-1 + + src_width = (len(tb.source)-1).bit_length() + src_mask = 2**src_width-1 if src_width else 0 + src_shift = id_width-src_width + max_count = 2**src_shift + count_mask = max_count-1 + + cur_id = 1 + + await tb.reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + test_frames = [list() for x in tb.source] + + for p in range(len(tb.source)): + for k in range(128): + length = random.randint(1, byte_lanes*16) + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + test_frame = AxiStreamFrame(test_data) + test_frame.tid = cur_id | (p << src_shift) + test_frame.tdest = cur_id + + test_frames[p].append(test_frame) + await tb.source[p].send(test_frame) + + cur_id = (cur_id + 1) % max_count + + while any(test_frames): + rx_frame = await tb.sink.recv() + + test_frame = None + + for lst in test_frames: + if lst and lst[0].tid == (rx_frame.tid & id_mask): + test_frame = lst.pop(0) + break + + assert test_frame is not None + + assert rx_frame.tdata == test_frame.tdata + assert (rx_frame.tid & id_mask) == test_frame.tid + assert ((rx_frame.tid >> src_shift) & src_mask) == (rx_frame.tid >> id_width) + assert rx_frame.tdest == test_frame.tdest + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +def size_list(): + data_width = len(cocotb.top.m_axis.tdata) + byte_width = data_width // 8 + return list(range(1, byte_width*4+1))+[512]+[1]*64 + + +def incrementing_payload(length): + return bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + +if cocotb.SIM_NAME: + + ports = len(cocotb.top.s_axis) + + factory = TestFactory(run_test) + factory.add_option("payload_lengths", [size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.add_option("port", list(range(ports))) + factory.generate_tests() + + for test in [run_test_tuser_assert]: + factory = TestFactory(test) + factory.add_option("port", list(range(ports))) + factory.generate_tests() + + if ports > 1: + factory = TestFactory(run_arb_test) + factory.generate_tests() + + factory = TestFactory(run_stress_test) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.dirname(__file__) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +@pytest.mark.parametrize("round_robin", [0, 1]) +@pytest.mark.parametrize("data_w", [8, 16, 32]) +@pytest.mark.parametrize("s_count", [1, 4]) +def test_taxi_axis_arb_mux(request, s_count, data_w, round_robin): + dut = "taxi_axis_arb_mux" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, "axis", f"{dut}.f"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['S_COUNT'] = s_count + parameters['DATA_W'] = data_w + parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8) + parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8 + parameters['STRB_EN'] = 0 + parameters['LAST_EN'] = 1 + parameters['ID_EN'] = 1 + parameters['S_ID_W'] = 8 + parameters['M_ID_W'] = parameters['S_ID_W'] + (s_count-1).bit_length() + parameters['DEST_EN'] = 1 + parameters['DEST_W'] = 8 + parameters['USER_EN'] = 1 + parameters['USER_W'] = 1 + parameters['UPDATE_TID'] = 1 + parameters['ARB_ROUND_ROBIN'] = round_robin + parameters['ARB_LSB_HIGH_PRIO'] = 1 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/tb/axis/taxi_axis_arb_mux/test_taxi_axis_arb_mux.sv b/tb/axis/taxi_axis_arb_mux/test_taxi_axis_arb_mux.sv new file mode 100644 index 0000000..33920e1 --- /dev/null +++ b/tb/axis/taxi_axis_arb_mux/test_taxi_axis_arb_mux.sv @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4-Stream arbitrated multiplexer testbench + */ +module test_taxi_axis_arb_mux # +( + /* verilator lint_off WIDTHTRUNC */ + parameter S_COUNT = 4, + parameter DATA_W = 8, + parameter logic KEEP_EN = (DATA_W>8), + parameter KEEP_W = ((DATA_W+7)/8), + parameter logic STRB_EN = 1'b0, + parameter logic LAST_EN = 1'b1, + parameter logic ID_EN = 1'b0, + parameter S_ID_W = 8, + parameter M_ID_W = S_ID_W+$clog2(S_COUNT), + parameter logic DEST_EN = 1'b0, + parameter DEST_W = 8, + parameter logic USER_EN = 1'b1, + parameter USER_W = 1, + parameter logic UPDATE_TID = 1'b0, + parameter logic ARB_ROUND_ROBIN = 1'b0, + parameter logic ARB_LSB_HIGH_PRIO = 1'b1 + /* verilator lint_on WIDTHTRUNC */ +) +(); + +logic clk; +logic rst; + +taxi_axis_if #( + .DATA_W(DATA_W), + .KEEP_EN(KEEP_EN), + .KEEP_W(KEEP_W), + .STRB_EN(STRB_EN), + .LAST_EN(LAST_EN), + .ID_EN(ID_EN), + .ID_W(S_ID_W), + .DEST_EN(DEST_EN), + .DEST_W(DEST_W), + .USER_EN(USER_EN), + .USER_W(USER_W) +) s_axis[S_COUNT](); + +taxi_axis_if #( + .DATA_W(DATA_W), + .KEEP_EN(KEEP_EN), + .KEEP_W(KEEP_W), + .STRB_EN(STRB_EN), + .LAST_EN(LAST_EN), + .ID_EN(ID_EN), + .ID_W(M_ID_W), + .DEST_EN(DEST_EN), + .DEST_W(DEST_W), + .USER_EN(USER_EN), + .USER_W(USER_W) +) m_axis(); + +taxi_axis_arb_mux #( + .S_COUNT(S_COUNT), + .UPDATE_TID(UPDATE_TID), + .ARB_ROUND_ROBIN(ARB_ROUND_ROBIN), + .ARB_LSB_HIGH_PRIO(ARB_LSB_HIGH_PRIO) +) +uut ( + .clk(clk), + .rst(rst), + + /* + * AXI4-Stream input (sink) + */ + .s_axis(s_axis), + + /* + * AXI4-Stream output (source) + */ + .m_axis(m_axis) +); + +endmodule + +`resetall