From 577c572c5d4954342c6c48519d35dc367928113d Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 28 Apr 2025 17:12:55 -0700 Subject: [PATCH] example: Update example designs Signed-off-by: Alex Forencich --- example/ADM_PCIE_9V3/fpga/fpga/Makefile | 2 +- example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile | 2 +- example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py | 8 ++++---- example/Alveo/fpga/fpga_AU200/Makefile | 2 +- example/Alveo/fpga/fpga_AU200_10g/Makefile | 2 +- example/Alveo/fpga/fpga_AU250/Makefile | 2 +- example/Alveo/fpga/fpga_AU250_10g/Makefile | 2 +- example/Alveo/fpga/fpga_AU280/Makefile | 2 +- example/Alveo/fpga/fpga_AU280_10g/Makefile | 2 +- example/Alveo/fpga/fpga_AU45N/Makefile | 2 +- example/Alveo/fpga/fpga_AU45N_10g/Makefile | 2 +- example/Alveo/fpga/fpga_AU50/Makefile | 2 +- example/Alveo/fpga/fpga_AU50_10g/Makefile | 2 +- example/Alveo/fpga/fpga_AU55C/Makefile | 2 +- example/Alveo/fpga/fpga_AU55C_10g/Makefile | 2 +- example/Alveo/fpga/fpga_AU55N/Makefile | 2 +- example/Alveo/fpga/fpga_AU55N_10g/Makefile | 2 +- example/Alveo/fpga/fpga_VCU1525/Makefile | 2 +- example/Alveo/fpga/fpga_VCU1525_10g/Makefile | 2 +- example/Alveo/fpga/fpga_X3522/Makefile | 2 +- example/Alveo/fpga/fpga_X3522_10g/Makefile | 2 +- example/Alveo/fpga/tb/fpga_core/test_fpga_core.py | 8 ++++---- example/KCU105/fpga/fpga_10g/Makefile | 2 +- example/KCU105/fpga/tb/fpga_core/test_fpga_core.py | 8 ++++---- example/KR260/fpga/fpga_10g/Makefile | 2 +- example/KR260/fpga/tb/fpga_core/test_fpga_core.py | 8 ++++---- example/Nexus_K3P_Q/fpga/fpga/Makefile | 2 +- example/Nexus_K3P_Q/fpga/fpga_10g/Makefile | 2 +- example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py | 8 ++++---- example/Nexus_K3P_S/fpga/fpga_K35/Makefile | 2 +- example/Nexus_K3P_S/fpga/fpga_K3P/Makefile | 2 +- example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile | 2 +- example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py | 8 ++++---- example/VCU108/fpga/fpga/Makefile | 2 +- example/VCU108/fpga/fpga_10g/Makefile | 2 +- example/VCU108/fpga/tb/fpga_core/test_fpga_core.py | 8 ++++---- example/VCU118/fpga/fpga/Makefile | 2 +- example/VCU118/fpga/fpga_10g/Makefile | 2 +- example/VCU118/fpga/tb/fpga_core/test_fpga_core.py | 8 ++++---- example/ZCU102/fpga/fpga_10g/Makefile | 2 +- example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py | 8 ++++---- example/ZCU106/fpga/fpga_10g/Makefile | 2 +- example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py | 8 ++++---- example/ZCU111/fpga/fpga/Makefile | 2 +- example/ZCU111/fpga/fpga_10g/Makefile | 2 +- example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py | 8 ++++---- example/fb2CG/fpga/fpga/Makefile | 2 +- example/fb2CG/fpga/fpga_10g/Makefile | 2 +- example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py | 8 ++++---- 49 files changed, 85 insertions(+), 85 deletions(-) diff --git a/example/ADM_PCIE_9V3/fpga/fpga/Makefile b/example/ADM_PCIE_9V3/fpga/fpga/Makefile index b015ad1..8b922c8 100644 --- a/example/ADM_PCIE_9V3/fpga/fpga/Makefile +++ b/example/ADM_PCIE_9V3/fpga/fpga/Makefile @@ -28,7 +28,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile b/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile index 33207be..55a10de 100644 --- a/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile +++ b/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile @@ -28,7 +28,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py b/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py index 354b9ce..088d05d 100644 --- a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py @@ -48,11 +48,11 @@ class TB: for inst in dut.gty_quad: for ch in inst.mac_inst.ch: - cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start()) - cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) - self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True)) + self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) + self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True)) dut.user_sw.setimmediatevalue(0) diff --git a/example/Alveo/fpga/fpga_AU200/Makefile b/example/Alveo/fpga/fpga_AU200/Makefile index 083aea0..0e26a27 100644 --- a/example/Alveo/fpga/fpga_AU200/Makefile +++ b/example/Alveo/fpga/fpga_AU200/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU200_10g/Makefile b/example/Alveo/fpga/fpga_AU200_10g/Makefile index a559084..fe6f0a0 100644 --- a/example/Alveo/fpga/fpga_AU200_10g/Makefile +++ b/example/Alveo/fpga/fpga_AU200_10g/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU250/Makefile b/example/Alveo/fpga/fpga_AU250/Makefile index 1d90d47..6b7095c 100644 --- a/example/Alveo/fpga/fpga_AU250/Makefile +++ b/example/Alveo/fpga/fpga_AU250/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU250_10g/Makefile b/example/Alveo/fpga/fpga_AU250_10g/Makefile index da86713..64d731d 100644 --- a/example/Alveo/fpga/fpga_AU250_10g/Makefile +++ b/example/Alveo/fpga/fpga_AU250_10g/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU280/Makefile b/example/Alveo/fpga/fpga_AU280/Makefile index f067711..be9d24d 100644 --- a/example/Alveo/fpga/fpga_AU280/Makefile +++ b/example/Alveo/fpga/fpga_AU280/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU280_10g/Makefile b/example/Alveo/fpga/fpga_AU280_10g/Makefile index e200cde..a1722ef 100644 --- a/example/Alveo/fpga/fpga_AU280_10g/Makefile +++ b/example/Alveo/fpga/fpga_AU280_10g/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU45N/Makefile b/example/Alveo/fpga/fpga_AU45N/Makefile index bc2b977..96e6d6b 100644 --- a/example/Alveo/fpga/fpga_AU45N/Makefile +++ b/example/Alveo/fpga/fpga_AU45N/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU45N_10g/Makefile b/example/Alveo/fpga/fpga_AU45N_10g/Makefile index 739b3da..9d340e0 100644 --- a/example/Alveo/fpga/fpga_AU45N_10g/Makefile +++ b/example/Alveo/fpga/fpga_AU45N_10g/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU50/Makefile b/example/Alveo/fpga/fpga_AU50/Makefile index 6526c75..979cbf0 100644 --- a/example/Alveo/fpga/fpga_AU50/Makefile +++ b/example/Alveo/fpga/fpga_AU50/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU50_10g/Makefile b/example/Alveo/fpga/fpga_AU50_10g/Makefile index f8aa891..a11090b 100644 --- a/example/Alveo/fpga/fpga_AU50_10g/Makefile +++ b/example/Alveo/fpga/fpga_AU50_10g/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU55C/Makefile b/example/Alveo/fpga/fpga_AU55C/Makefile index 4af6072..57332be 100644 --- a/example/Alveo/fpga/fpga_AU55C/Makefile +++ b/example/Alveo/fpga/fpga_AU55C/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU55C_10g/Makefile b/example/Alveo/fpga/fpga_AU55C_10g/Makefile index d329d4a..1c440fc 100644 --- a/example/Alveo/fpga/fpga_AU55C_10g/Makefile +++ b/example/Alveo/fpga/fpga_AU55C_10g/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU55N/Makefile b/example/Alveo/fpga/fpga_AU55N/Makefile index 3a5d695..c329764 100644 --- a/example/Alveo/fpga/fpga_AU55N/Makefile +++ b/example/Alveo/fpga/fpga_AU55N/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_AU55N_10g/Makefile b/example/Alveo/fpga/fpga_AU55N_10g/Makefile index 5534bf4..ecd2dc5 100644 --- a/example/Alveo/fpga/fpga_AU55N_10g/Makefile +++ b/example/Alveo/fpga/fpga_AU55N_10g/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_VCU1525/Makefile b/example/Alveo/fpga/fpga_VCU1525/Makefile index 6da773f..b831781 100644 --- a/example/Alveo/fpga/fpga_VCU1525/Makefile +++ b/example/Alveo/fpga/fpga_VCU1525/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_VCU1525_10g/Makefile b/example/Alveo/fpga/fpga_VCU1525_10g/Makefile index 8819fd2..f459065 100644 --- a/example/Alveo/fpga/fpga_VCU1525_10g/Makefile +++ b/example/Alveo/fpga/fpga_VCU1525_10g/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_X3522/Makefile b/example/Alveo/fpga/fpga_X3522/Makefile index 73b3c47..f81f0fd 100644 --- a/example/Alveo/fpga/fpga_X3522/Makefile +++ b/example/Alveo/fpga/fpga_X3522/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/fpga_X3522_10g/Makefile b/example/Alveo/fpga/fpga_X3522_10g/Makefile index f69532a..d44561c 100644 --- a/example/Alveo/fpga/fpga_X3522_10g/Makefile +++ b/example/Alveo/fpga/fpga_X3522_10g/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py b/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py index f02bf9c..ed4e595 100644 --- a/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py @@ -51,11 +51,11 @@ class TB: for inst in dut.gty_quad: for ch in inst.mac_inst.ch: - cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start()) - cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) - self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True)) + self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) + self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True)) dut.sw.setimmediatevalue(0) dut.eth_port_modprsl.setimmediatevalue(0) diff --git a/example/KCU105/fpga/fpga_10g/Makefile b/example/KCU105/fpga/fpga_10g/Makefile index 71e08fb..aca362f 100644 --- a/example/KCU105/fpga/fpga_10g/Makefile +++ b/example/KCU105/fpga/fpga_10g/Makefile @@ -32,7 +32,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl -IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gth_10g_156.tcl +IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py b/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py index 300aec1..1e70efc 100644 --- a/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py @@ -71,11 +71,11 @@ class TB: cocotb.start_soon(Clock(dut.sfp_mgt_refclk_0_p, 6.4, units="ns").start()) for ch in dut.sfp_mac.sfp_mac_inst.ch: - cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 6.4, units="ns").start()) - cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 6.4, units="ns").start()) - self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) - self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True)) + self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) + self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True)) self.uart_source = UartSource(dut.uart_rxd, baud=921600, bits=8, stop_bits=1) self.uart_sink = UartSink(dut.uart_txd, baud=921600, bits=8, stop_bits=1) diff --git a/example/KR260/fpga/fpga_10g/Makefile b/example/KR260/fpga/fpga_10g/Makefile index c731f80..db28579 100644 --- a/example/KR260/fpga/fpga_10g/Makefile +++ b/example/KR260/fpga/fpga_10g/Makefile @@ -29,7 +29,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gth_10g_156.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/example/KR260/fpga/tb/fpga_core/test_fpga_core.py b/example/KR260/fpga/tb/fpga_core/test_fpga_core.py index c798ec9..f45a7de 100644 --- a/example/KR260/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/KR260/fpga/tb/fpga_core/test_fpga_core.py @@ -60,11 +60,11 @@ class TB: ch = dut.sfp_mac.sfp_mac_inst.ch[0] - cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 6.4, units="ns").start()) - cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 6.4, units="ns").start()) - self.sfp_source = BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True) - self.sfp_sink = BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True) + self.sfp_source = BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True) + self.sfp_sink = BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True) cocotb.start_soon(self._run_clk()) diff --git a/example/Nexus_K3P_Q/fpga/fpga/Makefile b/example/Nexus_K3P_Q/fpga/fpga/Makefile index 8166241..c0a4edf 100644 --- a/example/Nexus_K3P_Q/fpga/fpga/Makefile +++ b/example/Nexus_K3P_Q/fpga/fpga/Makefile @@ -28,7 +28,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Nexus_K3P_Q/fpga/fpga_10g/Makefile b/example/Nexus_K3P_Q/fpga/fpga_10g/Makefile index 9b9da25..ff5ceee 100644 --- a/example/Nexus_K3P_Q/fpga/fpga_10g/Makefile +++ b/example/Nexus_K3P_Q/fpga/fpga_10g/Makefile @@ -28,7 +28,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py b/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py index f8508b9..57188e8 100644 --- a/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py @@ -48,11 +48,11 @@ class TB: for inst in dut.gty_quad: for ch in inst.mac_inst.ch: - cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start()) - cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) - self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True)) + self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) + self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True)) dut.qsfp_0_modprsl.setimmediatevalue(0) dut.qsfp_0_intl.setimmediatevalue(0) diff --git a/example/Nexus_K3P_S/fpga/fpga_K35/Makefile b/example/Nexus_K3P_S/fpga/fpga_K35/Makefile index b46d1b7..ba303b0 100644 --- a/example/Nexus_K3P_S/fpga/fpga_K35/Makefile +++ b/example/Nexus_K3P_S/fpga/fpga_K35/Makefile @@ -27,7 +27,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gth_10g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Nexus_K3P_S/fpga/fpga_K3P/Makefile b/example/Nexus_K3P_S/fpga/fpga_K3P/Makefile index d4eee3a..9337034 100644 --- a/example/Nexus_K3P_S/fpga/fpga_K3P/Makefile +++ b/example/Nexus_K3P_S/fpga/fpga_K3P/Makefile @@ -27,7 +27,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile b/example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile index 7557085..105fb40 100644 --- a/example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile +++ b/example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile @@ -27,7 +27,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py b/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py index 48d75c9..06e04c6 100644 --- a/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py @@ -47,11 +47,11 @@ class TB: self.sfp_sinks = [] for ch in dut.sfp_mac_inst.ch: - cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start()) - cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start()) - self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) - self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True)) + self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) + self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True)) dut.sfp_npres.setimmediatevalue(0) dut.sfp_los.setimmediatevalue(0) diff --git a/example/VCU108/fpga/fpga/Makefile b/example/VCU108/fpga/fpga/Makefile index d1fac90..75dc8e4 100644 --- a/example/VCU108/fpga/fpga/Makefile +++ b/example/VCU108/fpga/fpga/Makefile @@ -32,7 +32,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl -IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl +IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl include ../common/vivado.mk diff --git a/example/VCU108/fpga/fpga_10g/Makefile b/example/VCU108/fpga/fpga_10g/Makefile index 27c7874..36d91aa 100644 --- a/example/VCU108/fpga/fpga_10g/Makefile +++ b/example/VCU108/fpga/fpga_10g/Makefile @@ -32,7 +32,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl -IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl +IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl include ../common/vivado.mk diff --git a/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py b/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py index 68b1129..121253f 100644 --- a/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py @@ -58,11 +58,11 @@ class TB: self.qsfp_sinks = [] for ch in dut.qsfp_mac_inst.ch: - cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start()) - cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) - self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True)) + self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) + self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True)) dut.phy_gmii_clk_en.setimmediatevalue(1) diff --git a/example/VCU118/fpga/fpga/Makefile b/example/VCU118/fpga/fpga/Makefile index 503336f..6e2ea36 100644 --- a/example/VCU118/fpga/fpga/Makefile +++ b/example/VCU118/fpga/fpga/Makefile @@ -33,7 +33,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl -IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl +IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl include ../common/vivado.mk diff --git a/example/VCU118/fpga/fpga_10g/Makefile b/example/VCU118/fpga/fpga_10g/Makefile index 79e6898..087478e 100644 --- a/example/VCU118/fpga/fpga_10g/Makefile +++ b/example/VCU118/fpga/fpga_10g/Makefile @@ -33,7 +33,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl -IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl +IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl include ../common/vivado.mk diff --git a/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py b/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py index a5ed410..f1721d6 100644 --- a/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py @@ -59,11 +59,11 @@ class TB: for inst in dut.gty_quad: for ch in inst.mac_inst.ch: - cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start()) - cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) - self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True)) + self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) + self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True)) dut.phy_gmii_clk_en.setimmediatevalue(1) diff --git a/example/ZCU102/fpga/fpga_10g/Makefile b/example/ZCU102/fpga/fpga_10g/Makefile index eb9483d..2b532f0 100644 --- a/example/ZCU102/fpga/fpga_10g/Makefile +++ b/example/ZCU102/fpga/fpga_10g/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gth_10g_156.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index cd478b2..79c5246 100644 --- a/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -77,11 +77,11 @@ class TB: cocotb.start_soon(Clock(dut.sfp_mgt_refclk_0_p, 6.4, units="ns").start()) for ch in dut.sfp_mac.sfp_mac_inst.ch: - cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 6.4, units="ns").start()) - cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 6.4, units="ns").start()) - self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) - self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True)) + self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) + self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True)) self.uart_source = UartSource(dut.uart_rxd, baud=2000000, bits=8, stop_bits=1) self.uart_sink = UartSink(dut.uart_txd, baud=2000000, bits=8, stop_bits=1) diff --git a/example/ZCU106/fpga/fpga_10g/Makefile b/example/ZCU106/fpga/fpga_10g/Makefile index 4e19721..df42fa3 100644 --- a/example/ZCU106/fpga/fpga_10g/Makefile +++ b/example/ZCU106/fpga/fpga_10g/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gth_10g_156.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py b/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py index 0f6abcd..a8c0d81 100644 --- a/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py @@ -65,11 +65,11 @@ class TB: cocotb.start_soon(Clock(dut.sfp_mgt_refclk_0_p, 6.4, units="ns").start()) for ch in dut.sfp_mac.sfp_mac_inst.ch: - cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 6.4, units="ns").start()) - cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 6.4, units="ns").start()) - self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) - self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True)) + self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) + self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True)) self.uart_source = UartSource(dut.uart_rxd, baud=2000000, bits=8, stop_bits=1) self.uart_sink = UartSink(dut.uart_txd, baud=2000000, bits=8, stop_bits=1) diff --git a/example/ZCU111/fpga/fpga/Makefile b/example/ZCU111/fpga/fpga/Makefile index da82f1a..bfaaa39 100644 --- a/example/ZCU111/fpga/fpga/Makefile +++ b/example/ZCU111/fpga/fpga/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/ZCU111/fpga/fpga_10g/Makefile b/example/ZCU111/fpga/fpga_10g/Makefile index 4966e0e..bcd112a 100644 --- a/example/ZCU111/fpga/fpga_10g/Makefile +++ b/example/ZCU111/fpga/fpga_10g/Makefile @@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl # Configuration #CONFIG_TCL_FILES = ./config.tcl diff --git a/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py b/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py index 7a7d9ff..a1980c2 100644 --- a/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py @@ -49,11 +49,11 @@ class TB: cocotb.start_soon(Clock(dut.sfp_mgt_refclk_0_p, 6.4, units="ns").start()) for ch in dut.sfp_mac_inst.ch: - cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 6.4, units="ns").start()) - cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 6.4, units="ns").start()) - self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) - self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True)) + self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) + self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True)) self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1) self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1) diff --git a/example/fb2CG/fpga/fpga/Makefile b/example/fb2CG/fpga/fpga/Makefile index 43256eb..18e8464 100644 --- a/example/fb2CG/fpga/fpga/Makefile +++ b/example/fb2CG/fpga/fpga/Makefile @@ -28,7 +28,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/example/fb2CG/fpga/fpga_10g/Makefile b/example/fb2CG/fpga/fpga_10g/Makefile index 4925d32..a6bdd09 100644 --- a/example/fb2CG/fpga/fpga_10g/Makefile +++ b/example/fb2CG/fpga/fpga_10g/Makefile @@ -28,7 +28,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl # IP -IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl +IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl # Configuration # CONFIG_TCL_FILES = ./config.tcl diff --git a/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py b/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py index 4d9be27..f344c66 100644 --- a/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py @@ -49,11 +49,11 @@ class TB: for inst in dut.gty_quad: for ch in inst.mac_inst.ch: - cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start()) - cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start()) + cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) - self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True)) + self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)) + self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True)) dut.qsfp_0_mod_prsnt_n.setimmediatevalue(0) dut.qsfp_0_intr_n.setimmediatevalue(0)