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eth: Add MAC pause control modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
200
rtl/eth/taxi_mac_pause_ctrl_rx.sv
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200
rtl/eth/taxi_mac_pause_ctrl_rx.sv
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2023-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* PFC and pause frame receive handling
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*/
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module taxi_mac_pause_ctrl_rx #
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(
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parameter MCF_PARAMS_SIZE = 18,
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parameter logic PFC_EN = 1'b1
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* MAC control frame interface
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*/
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input wire logic mcf_valid,
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input wire logic [47:0] mcf_eth_dst,
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input wire logic [47:0] mcf_eth_src,
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input wire logic [15:0] mcf_eth_type,
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input wire logic [15:0] mcf_opcode,
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input wire logic [MCF_PARAMS_SIZE*8-1:0] mcf_params,
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/*
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* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
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*/
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input wire logic rx_lfc_en,
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output wire logic rx_lfc_req,
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input wire logic rx_lfc_ack,
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/*
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* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
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*/
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input wire logic [7:0] rx_pfc_en,
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output wire logic [7:0] rx_pfc_req,
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input wire logic [7:0] rx_pfc_ack,
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/*
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* Configuration
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*/
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input wire logic [15:0] cfg_rx_lfc_opcode = 16'h0001,
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input wire logic cfg_rx_lfc_en = 1'b0,
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input wire logic [15:0] cfg_rx_pfc_opcode = 16'h0101,
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input wire logic cfg_rx_pfc_en = 1'b0,
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input wire logic [9:0] cfg_quanta_step,
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input wire logic cfg_quanta_clk_en = 1'b1,
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/*
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* Status
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*/
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output wire logic stat_rx_lfc_pkt,
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output wire logic stat_rx_lfc_xon,
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output wire logic stat_rx_lfc_xoff,
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output wire logic stat_rx_lfc_paused,
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output wire logic stat_rx_pfc_pkt,
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output wire logic [7:0] stat_rx_pfc_xon,
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output wire logic [7:0] stat_rx_pfc_xoff,
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output wire logic [7:0] stat_rx_pfc_paused
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);
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localparam QW = 16;
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localparam QFB = 8;
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// check configuration
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if (MCF_PARAMS_SIZE < (PFC_EN ? 18 : 2))
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$fatal(0, "Error: MCF_PARAMS_SIZE too small for requested configuration (instance %m)");
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logic lfc_req_reg = 1'b0, lfc_req_next;
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logic [7:0] pfc_req_reg = 8'd0, pfc_req_next;
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logic [QW+QFB-1:0] lfc_quanta_reg = '0, lfc_quanta_next;
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logic [QW+QFB-1:0] pfc_quanta_reg[0:7], pfc_quanta_next[0:7];
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logic stat_rx_lfc_pkt_reg = 1'b0, stat_rx_lfc_pkt_next;
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logic stat_rx_lfc_xon_reg = 1'b0, stat_rx_lfc_xon_next;
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logic stat_rx_lfc_xoff_reg = 1'b0, stat_rx_lfc_xoff_next;
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logic stat_rx_pfc_pkt_reg = 1'b0, stat_rx_pfc_pkt_next;
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logic [7:0] stat_rx_pfc_xon_reg = '0, stat_rx_pfc_xon_next;
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logic [7:0] stat_rx_pfc_xoff_reg = '0, stat_rx_pfc_xoff_next;
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assign rx_lfc_req = lfc_req_reg;
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assign rx_pfc_req = pfc_req_reg;
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assign stat_rx_lfc_pkt = stat_rx_lfc_pkt_reg;
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assign stat_rx_lfc_xon = stat_rx_lfc_xon_reg;
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assign stat_rx_lfc_xoff = stat_rx_lfc_xoff_reg;
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assign stat_rx_lfc_paused = lfc_req_reg;
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assign stat_rx_pfc_pkt = stat_rx_pfc_pkt_reg;
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assign stat_rx_pfc_xon = stat_rx_pfc_xon_reg;
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assign stat_rx_pfc_xoff = stat_rx_pfc_xoff_reg;
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assign stat_rx_pfc_paused = pfc_req_reg;
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initial begin
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for (integer k = 0; k < 8; k = k + 1) begin
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pfc_quanta_reg[k] = '0;
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end
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end
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always_comb begin
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stat_rx_lfc_pkt_next = 1'b0;
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stat_rx_lfc_xon_next = 1'b0;
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stat_rx_lfc_xoff_next = 1'b0;
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stat_rx_pfc_pkt_next = 1'b0;
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stat_rx_pfc_xon_next = '0;
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stat_rx_pfc_xoff_next = '0;
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if (cfg_quanta_clk_en && rx_lfc_ack) begin
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if (lfc_quanta_reg > (QW+QFB)'(cfg_quanta_step)) begin
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lfc_quanta_next = lfc_quanta_reg - (QW+QFB)'(cfg_quanta_step);
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end else begin
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lfc_quanta_next = '0;
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end
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end else begin
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lfc_quanta_next = lfc_quanta_reg;
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end
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lfc_req_next = (lfc_quanta_reg != 0) && rx_lfc_en && cfg_rx_lfc_en;
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for (integer k = 0; k < 8; k = k + 1) begin
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if (cfg_quanta_clk_en && rx_pfc_ack[k]) begin
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if (pfc_quanta_reg[k] > (QW+QFB)'(cfg_quanta_step)) begin
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pfc_quanta_next[k] = pfc_quanta_reg[k] - (QW+QFB)'(cfg_quanta_step);
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end else begin
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pfc_quanta_next[k] = '0;
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end
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end else begin
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pfc_quanta_next[k] = pfc_quanta_reg[k];
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end
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pfc_req_next[k] = (pfc_quanta_reg[k] != 0) && rx_pfc_en[k] && cfg_rx_pfc_en;
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end
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if (mcf_valid) begin
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if (mcf_opcode == cfg_rx_lfc_opcode && cfg_rx_lfc_en) begin
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stat_rx_lfc_pkt_next = 1'b1;
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stat_rx_lfc_xon_next = {mcf_params[7:0], mcf_params[15:8]} == 0;
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stat_rx_lfc_xoff_next = {mcf_params[7:0], mcf_params[15:8]} != 0;
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lfc_quanta_next = {mcf_params[7:0], mcf_params[15:8], {QFB{1'b0}}};
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end else if (PFC_EN && mcf_opcode == cfg_rx_pfc_opcode && cfg_rx_pfc_en) begin
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stat_rx_pfc_pkt_next = 1'b1;
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for (integer k = 0; k < 8; k = k + 1) begin
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if (mcf_params[k+8]) begin
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stat_rx_pfc_xon_next[k] = {mcf_params[16+(k*QW)+0 +: 8], mcf_params[16+(k*QW)+8 +: 8]} == 0;
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stat_rx_pfc_xoff_next[k] = {mcf_params[16+(k*QW)+0 +: 8], mcf_params[16+(k*QW)+8 +: 8]} != 0;
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pfc_quanta_next[k] = {mcf_params[16+(k*QW)+0 +: 8], mcf_params[16+(k*QW)+8 +: 8], {QFB{1'b0}}};
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end
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end
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end
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end
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end
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always_ff @(posedge clk) begin
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lfc_req_reg <= lfc_req_next;
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pfc_req_reg <= pfc_req_next;
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lfc_quanta_reg <= lfc_quanta_next;
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for (integer k = 0; k < 8; k = k + 1) begin
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pfc_quanta_reg[k] <= pfc_quanta_next[k];
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end
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stat_rx_lfc_pkt_reg <= stat_rx_lfc_pkt_next;
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stat_rx_lfc_xon_reg <= stat_rx_lfc_xon_next;
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stat_rx_lfc_xoff_reg <= stat_rx_lfc_xoff_next;
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stat_rx_pfc_pkt_reg <= stat_rx_pfc_pkt_next;
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stat_rx_pfc_xon_reg <= stat_rx_pfc_xon_next;
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stat_rx_pfc_xoff_reg <= stat_rx_pfc_xoff_next;
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if (rst) begin
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lfc_req_reg <= 1'b0;
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pfc_req_reg <= 8'd0;
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lfc_quanta_reg <= '0;
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for (integer k = 0; k < 8; k = k + 1) begin
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pfc_quanta_reg[k] <= '0;
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end
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stat_rx_lfc_pkt_reg <= 1'b0;
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stat_rx_lfc_xon_reg <= 1'b0;
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stat_rx_lfc_xoff_reg <= 1'b0;
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stat_rx_pfc_pkt_reg <= 1'b0;
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stat_rx_pfc_xon_reg <= '0;
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stat_rx_pfc_xoff_reg <= '0;
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end
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end
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endmodule
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`resetall
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