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eth: Add MAC pause control modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
46
tb/eth/taxi_mac_pause_ctrl_rx/Makefile
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46
tb/eth/taxi_mac_pause_ctrl_rx/Makefile
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@@ -0,0 +1,46 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2023-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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DUT = taxi_mac_pause_ctrl_rx
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = $(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_MCF_PARAMS_SIZE := 18
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export PARAM_PFC_EN := "1'b1"
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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424
tb/eth/taxi_mac_pause_ctrl_rx/test_taxi_mac_pause_ctrl_rx.py
Normal file
424
tb/eth/taxi_mac_pause_ctrl_rx/test_taxi_mac_pause_ctrl_rx.py
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@@ -0,0 +1,424 @@
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#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2023-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import logging
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import os
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import struct
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from scapy.layers.l2 import Ether
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from scapy.utils import mac2str
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import cocotb_test.simulator
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.regression import TestFactory
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from cocotb.utils import get_sim_time
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from cocotbext.axi.stream import define_stream
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McfBus, McfTransaction, McfSource, McfSink, McfMonitor = define_stream("Mcf",
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signals=["valid", "eth_dst", "eth_src", "eth_type", "opcode", "params"],
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optional_signals=["ready", "id", "dest", "user"]
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)
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class TB:
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
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self.mcf_source = McfSource(McfBus.from_prefix(dut, "mcf"), dut.clk, dut.rst)
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dut.rx_lfc_en.setimmediatevalue(0)
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dut.rx_lfc_ack.setimmediatevalue(0)
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dut.rx_pfc_en.setimmediatevalue(0)
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dut.rx_pfc_ack.setimmediatevalue(0)
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dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
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dut.cfg_rx_lfc_en.setimmediatevalue(0)
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dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
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dut.cfg_rx_pfc_en.setimmediatevalue(0)
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dut.cfg_quanta_step.setimmediatevalue(256)
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dut.cfg_quanta_clk_en.setimmediatevalue(1)
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def send_mcf(self, pkt):
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mcf = McfTransaction()
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mcf.eth_dst = int.from_bytes(mac2str(pkt[Ether].dst), 'big')
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mcf.eth_src = int.from_bytes(mac2str(pkt[Ether].src), 'big')
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mcf.eth_type = pkt[Ether].type
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mcf.opcode = int.from_bytes(bytes(pkt[Ether].payload)[0:2], 'big')
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mcf.params = int.from_bytes(bytes(pkt[Ether].payload)[2:], 'little')
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await self.mcf_source.send(mcf)
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async def run_test_lfc(dut):
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tb = TB(dut)
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await tb.reset()
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dut.rx_lfc_en.value = 1
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dut.rx_lfc_ack.value = 0
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dut.rx_pfc_en.value = 0
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dut.rx_pfc_ack.value = 0
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dut.cfg_rx_lfc_opcode.value = 0x0001
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dut.cfg_rx_lfc_en.value = 1
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dut.cfg_rx_pfc_opcode.value = 0x0101
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dut.cfg_rx_pfc_en.value = 0
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dut.cfg_quanta_step.value = int(10000*256 / (512*156.25))
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dut.cfg_quanta_clk_en.value = 1
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tb.log.info("Test release time accuracy")
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eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
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test_pkt = eth / struct.pack('!HH', 0x0001, 100)
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await tb.send_mcf(test_pkt)
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while dut.rx_lfc_req.value == 0:
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await RisingEdge(dut.clk)
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dut.rx_lfc_ack.value = 1
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start_time = get_sim_time('sec')
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while dut.rx_lfc_req.value:
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await RisingEdge(dut.clk)
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stop_time = get_sim_time('sec')
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dut.rx_lfc_ack.value = 0
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pause_time = stop_time-start_time
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pause_quanta = pause_time / (512 * 1/10e9)
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tb.log.info("pause time : %g s", pause_time)
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tb.log.info("pause quanta : %f", pause_quanta)
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assert round(pause_quanta) == 100
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tb.log.info("Test release time accuracy (with refresh)")
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eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
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test_pkt = eth / struct.pack('!HH', 0x0001, 100)
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await tb.send_mcf(test_pkt)
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while dut.rx_lfc_req.value == 0:
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await RisingEdge(dut.clk)
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dut.rx_lfc_ack.value = 1
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for k in range(400):
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await RisingEdge(dut.clk)
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await tb.send_mcf(test_pkt)
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start_time = get_sim_time('sec')
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while dut.rx_lfc_req.value:
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await RisingEdge(dut.clk)
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stop_time = get_sim_time('sec')
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dut.rx_lfc_ack.value = 0
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pause_time = stop_time-start_time
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pause_quanta = pause_time / (512 * 1/10e9)
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tb.log.info("pause time : %g s", pause_time)
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tb.log.info("pause quanta : %f", pause_quanta)
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assert round(pause_quanta) == 100
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tb.log.info("Test explicit release")
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eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
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test_pkt = eth / struct.pack('!HH', 0x0001, 100)
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await tb.send_mcf(test_pkt)
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while dut.rx_lfc_req.value == 0:
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await RisingEdge(dut.clk)
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dut.rx_lfc_ack.value = 1
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start_time = get_sim_time('sec')
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eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
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test_pkt = eth / struct.pack('!HH', 0x0001, 0)
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await tb.send_mcf(test_pkt)
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while dut.rx_lfc_req.value:
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await RisingEdge(dut.clk)
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stop_time = get_sim_time('sec')
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dut.rx_lfc_ack.value = 0
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pause_time = stop_time-start_time
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pause_quanta = pause_time / (512 * 1/10e9)
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tb.log.info("pause time : %g s", pause_time)
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tb.log.info("pause quanta : %f", pause_quanta)
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assert round(pause_quanta) < 50
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_test_pfc(dut):
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tb = TB(dut)
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await tb.reset()
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dut.rx_lfc_en.value = 0
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dut.rx_lfc_ack.value = 0
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dut.rx_pfc_en.value = 0xFF
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dut.rx_pfc_ack.value = 0
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dut.cfg_rx_lfc_opcode.value = 0x0001
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dut.cfg_rx_lfc_en.value = 0
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dut.cfg_rx_pfc_opcode.value = 0x0101
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dut.cfg_rx_pfc_en.value = 1
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dut.cfg_quanta_step.value = int(10000*256 / (512*156.25))
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dut.cfg_quanta_clk_en.value = 1
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tb.log.info("Test release time accuracy")
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eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
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test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0001, 100, 0, 0, 0, 0, 0, 0, 0)
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await tb.send_mcf(test_pkt)
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while dut.rx_pfc_req.value == 0x00:
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await RisingEdge(dut.clk)
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dut.rx_pfc_ack.value = 0x01
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start_time = get_sim_time('sec')
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while dut.rx_pfc_req.value:
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await RisingEdge(dut.clk)
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stop_time = get_sim_time('sec')
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dut.rx_pfc_ack.value = 0x00
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pause_time = stop_time-start_time
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pause_quanta = pause_time / (512 * 1/10e9)
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tb.log.info("pause time : %g s", pause_time)
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tb.log.info("pause quanta : %f", pause_quanta)
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assert round(pause_quanta) == 100
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tb.log.info("Test release time accuracy (with refresh)")
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eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
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test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0001, 100, 0, 0, 0, 0, 0, 0, 0)
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await tb.send_mcf(test_pkt)
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while dut.rx_pfc_req.value == 0x00:
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await RisingEdge(dut.clk)
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dut.rx_pfc_ack.value = 0x01
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for k in range(400):
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await RisingEdge(dut.clk)
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await tb.send_mcf(test_pkt)
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start_time = get_sim_time('sec')
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while dut.rx_pfc_req.value:
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await RisingEdge(dut.clk)
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stop_time = get_sim_time('sec')
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dut.rx_pfc_ack.value = 0x00
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pause_time = stop_time-start_time
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pause_quanta = pause_time / (512 * 1/10e9)
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tb.log.info("pause time : %g s", pause_time)
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tb.log.info("pause quanta : %f", pause_quanta)
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assert round(pause_quanta) == 100
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tb.log.info("Test explicit release")
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eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
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test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0001, 100, 0, 0, 0, 0, 0, 0, 0)
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await tb.send_mcf(test_pkt)
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while dut.rx_pfc_req.value == 0x00:
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await RisingEdge(dut.clk)
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dut.rx_pfc_ack.value = 0x01
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start_time = get_sim_time('sec')
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eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
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test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0001, 0, 0, 0, 0, 0, 0, 0, 0)
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await tb.send_mcf(test_pkt)
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while dut.rx_pfc_req.value:
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await RisingEdge(dut.clk)
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stop_time = get_sim_time('sec')
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dut.rx_pfc_ack.value = 0x00
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pause_time = stop_time-start_time
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pause_quanta = pause_time / (512 * 1/10e9)
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tb.log.info("pause time : %g s", pause_time)
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tb.log.info("pause quanta : %f", pause_quanta)
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assert round(pause_quanta) < 50
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tb.log.info("Test all channels")
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eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
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test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80)
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await tb.send_mcf(test_pkt)
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while dut.rx_pfc_req.value != 0xff:
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await RisingEdge(dut.clk)
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dut.rx_pfc_ack.value = 0xff
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start_time = get_sim_time('sec')
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for k in range(8):
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while dut.rx_pfc_req.value & (1 << k) != 0x00:
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await RisingEdge(dut.clk)
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stop_time = get_sim_time('sec')
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pause_time = stop_time-start_time
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pause_quanta = pause_time / (512 * 1/10e9)
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tb.log.info("pause time : %g s", pause_time)
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tb.log.info("pause quanta : %f", pause_quanta)
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assert round(pause_quanta) == (k+1)*10
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dut.rx_pfc_ack.value = 0
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tb.log.info("Test isolation")
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eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
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test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0001, 100, 0, 0, 0, 0, 0, 0, 0)
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await tb.send_mcf(test_pkt)
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while dut.rx_pfc_req.value & 0x01 == 0x00:
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await RisingEdge(dut.clk)
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dut.rx_pfc_ack.value = 0x01
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start_time = get_sim_time('sec')
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eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
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test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0002, 0, 200, 0, 0, 0, 0, 0, 0)
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await tb.send_mcf(test_pkt)
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while dut.rx_pfc_req.value & 0x02 == 0x00:
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await RisingEdge(dut.clk)
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dut.rx_pfc_ack.value = 0x03
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eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
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test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0002, 0, 0, 0, 0, 0, 0, 0, 0)
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await tb.send_mcf(test_pkt)
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while dut.rx_pfc_req.value:
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await RisingEdge(dut.clk)
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stop_time = get_sim_time('sec')
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dut.rx_pfc_ack.value = 0x00
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pause_time = stop_time-start_time
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pause_quanta = pause_time / (512 * 1/10e9)
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tb.log.info("pause time : %g s", pause_time)
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tb.log.info("pause quanta : %f", pause_quanta)
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assert round(pause_quanta) == 100
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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if cocotb.SIM_NAME:
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for test in [run_test_lfc, run_test_pfc]:
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factory = TestFactory(test)
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||||
factory.generate_tests()
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||||
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||||
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# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
def test_taxi_mac_pause_ctrl_rx(request):
|
||||
dut = "taxi_mac_pause_ctrl_rx"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, "eth", f"{dut}.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['MCF_PARAMS_SIZE'] = 18
|
||||
parameters['PFC_EN'] = "1'b1"
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Reference in New Issue
Block a user