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apb: Add APB to AXI lite adapter module and testbench

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2026-02-15 12:49:30 -08:00
parent 51e0909327
commit 5951547d11
5 changed files with 998 additions and 0 deletions
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1
README.md
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@@ -77,6 +77,7 @@ The Taxi transport library contains many smaller components that can be composed
* APB
* SV interface for APB
* APB to AXI lite adapter
* Interconnect
* Width converter
* Single-port RAM

601
src/apb/rtl/taxi_apb_axil_adapter.sv Normal file
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@@ -0,0 +1,601 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2026 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* APB to AXI4 lite adapter
*/
module taxi_apb_axil_adapter
(
input wire logic clk,
input wire logic rst,
/*
* APB slave interface
*/
taxi_apb_if.slv s_apb,
/*
* AXI4-Lite master interface
*/
taxi_axil_if.wr_mst m_axil_wr,
taxi_axil_if.rd_mst m_axil_rd
);
// extract parameters
localparam APB_DATA_W = s_apb.DATA_W;
localparam APB_ADDR_W = s_apb.ADDR_W;
localparam APB_STRB_W = s_apb.STRB_W;
localparam logic PAUSER_EN = (m_axil_wr.AWUSER_EN || m_axil_wr.ARUSER_EN) && s_apb.PAUSER_EN;
localparam PAUSER_W = s_apb.PAUSER_W;
localparam logic PWUSER_EN = m_axil_wr.WUSER_EN && s_apb.PWUSER_EN;
localparam PWUSER_W = s_apb.PWUSER_W;
localparam logic PRUSER_EN = m_axil_rd.RUSER_EN && s_apb.PRUSER_EN;
localparam PRUSER_W = s_apb.PRUSER_W;
localparam logic PBUSER_EN = m_axil_wr.BUSER_EN && s_apb.PBUSER_EN;
localparam PBUSER_W = s_apb.PBUSER_W;
localparam AXIL_DATA_W = m_axil_rd.DATA_W;
localparam AXIL_ADDR_W = m_axil_rd.ADDR_W;
localparam AXIL_STRB_W = m_axil_rd.STRB_W;
localparam logic AWUSER_EN = m_axil_wr.AWUSER_EN && s_apb.PAUSER_EN;
localparam AWUSER_W = m_axil_wr.AWUSER_W;
localparam logic WUSER_EN = m_axil_wr.WUSER_EN && s_apb.PWUSER_EN;
localparam WUSER_W = m_axil_wr.WUSER_W;
localparam logic BUSER_EN = m_axil_wr.BUSER_EN && s_apb.PBUSER_EN;
localparam BUSER_W = m_axil_wr.BUSER_W;
localparam logic ARUSER_EN = m_axil_rd.ARUSER_EN && s_apb.PAUSER_EN;
localparam ARUSER_W = m_axil_rd.ARUSER_W;
localparam logic RUSER_EN = m_axil_rd.RUSER_EN && s_apb.PRUSER_EN;
localparam RUSER_W = m_axil_rd.RUSER_W;
localparam AUSER_W = ARUSER_W > AWUSER_W ? ARUSER_W : AWUSER_W;
localparam APB_ADDR_BIT_OFFSET = $clog2(APB_STRB_W);
localparam AXIL_ADDR_BIT_OFFSET = $clog2(AXIL_STRB_W);
localparam APB_BYTE_LANES = APB_STRB_W;
localparam AXIL_BYTE_LANES = AXIL_STRB_W;
localparam APB_BYTE_W = APB_DATA_W/APB_BYTE_LANES;
localparam AXIL_BYTE_W = AXIL_DATA_W/AXIL_BYTE_LANES;
localparam APB_ADDR_MASK = {APB_ADDR_W{1'b1}} << APB_ADDR_BIT_OFFSET;
localparam AXIL_ADDR_MASK = {AXIL_ADDR_W{1'b1}} << AXIL_ADDR_BIT_OFFSET;
// check configuration
if (APB_BYTE_W * APB_STRB_W != APB_DATA_W)
$fatal(0, "Error: APB interface data width not evenly divisible (instance %m)");
if (AXIL_BYTE_W * AXIL_STRB_W != AXIL_DATA_W)
$fatal(0, "Error: AXI lite interface data width not evenly divisible (instance %m)");
if (APB_BYTE_W != AXIL_BYTE_W)
$fatal(0, "Error: byte size mismatch (instance %m)");
if (2**$clog2(APB_BYTE_LANES) != APB_BYTE_LANES)
$fatal(0, "Error: APB interface byte lane count must be even power of two (instance %m)");
if (2**$clog2(AXIL_BYTE_LANES) != AXIL_BYTE_LANES)
$fatal(0, "Error: AXI lite interface byte lane count must be even power of two (instance %m)");
if (m_axil_wr.DATA_W != m_axil_rd.DATA_W)
$fatal(0, "Error: AXI interface configuration mismatch (instance %m)");
if (AXIL_BYTE_LANES == APB_BYTE_LANES) begin : bypass
// same width; translate
localparam [0:0]
STATE_IDLE = 1'd0,
STATE_DATA = 1'd1;
logic [0:0] state_reg = STATE_IDLE, state_next;
logic s_apb_pready_reg = 1'b0, s_apb_pready_next;
logic [APB_DATA_W-1:0] s_apb_prdata_reg = '0, s_apb_prdata_next;
logic s_apb_pslverr_reg = 1'b0, s_apb_pslverr_next;
logic [PRUSER_W-1:0] s_apb_pruser_reg = '0, s_apb_pruser_next;
logic [PBUSER_W-1:0] s_apb_pbuser_reg = '0, s_apb_pbuser_next;
logic [AXIL_ADDR_W-1:0] m_axil_addr_reg = '0, m_axil_addr_next;
logic [2:0] m_axil_prot_reg = 3'd0, m_axil_prot_next;
logic [AUSER_W-1:0] m_axil_auser_reg = '0, m_axil_auser_next;
logic m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
logic [AXIL_DATA_W-1:0] m_axil_wdata_reg = '0, m_axil_wdata_next;
logic [AXIL_STRB_W-1:0] m_axil_wstrb_reg = '0, m_axil_wstrb_next;
logic [WUSER_W-1:0] m_axil_wuser_reg = '0, m_axil_wuser_next;
logic m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
logic m_axil_bready_reg = 1'b0, m_axil_bready_next;
logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
logic m_axil_rready_reg = 1'b0, m_axil_rready_next;
assign s_apb.pready = s_apb_pready_reg;
assign s_apb.prdata = s_apb_prdata_reg;
assign s_apb.pslverr = s_apb_pslverr_reg;
assign s_apb.pruser = PRUSER_EN ? s_apb_pruser_reg : '0;
assign s_apb.pbuser = PBUSER_EN ? s_apb_pbuser_reg : '0;
assign m_axil_wr.awaddr = m_axil_addr_reg;
assign m_axil_wr.awprot = m_axil_prot_reg;
assign m_axil_wr.awuser = AWUSER_EN ? m_axil_auser_reg : '0;
assign m_axil_wr.awvalid = m_axil_awvalid_reg;
assign m_axil_wr.wdata = m_axil_wdata_reg;
assign m_axil_wr.wstrb = m_axil_wstrb_reg;
assign m_axil_wr.wuser = WUSER_EN ? m_axil_wuser_reg : '0;
assign m_axil_wr.wvalid = m_axil_wvalid_reg;
assign m_axil_wr.bready = m_axil_bready_reg;
assign m_axil_rd.araddr = m_axil_addr_reg;
assign m_axil_rd.arprot = m_axil_prot_reg;
assign m_axil_rd.aruser = ARUSER_EN ? m_axil_auser_reg : '0;
assign m_axil_rd.arvalid = m_axil_arvalid_reg;
assign m_axil_rd.rready = m_axil_rready_reg;
always_comb begin
state_next = STATE_IDLE;
s_apb_pready_next = 1'b0;
s_apb_prdata_next = s_apb_prdata_reg;
s_apb_pslverr_next = s_apb_pslverr_reg;
s_apb_pruser_next = s_apb_pruser_reg;
s_apb_pbuser_next = s_apb_pbuser_reg;
m_axil_addr_next = m_axil_addr_reg;
m_axil_prot_next = m_axil_prot_reg;
m_axil_auser_next = m_axil_auser_reg;
m_axil_awvalid_next = m_axil_awvalid_reg && !m_axil_wr.awready;
m_axil_wdata_next = m_axil_wdata_reg;
m_axil_wstrb_next = m_axil_wstrb_reg;
m_axil_wuser_next = m_axil_wuser_reg;
m_axil_wvalid_next = m_axil_wvalid_reg && !m_axil_wr.wready;
m_axil_bready_next = 1'b0;
m_axil_arvalid_next = m_axil_arvalid_reg && !m_axil_rd.arready;
m_axil_rready_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
m_axil_addr_next = s_apb.paddr;
m_axil_prot_next = s_apb.pprot;
m_axil_wdata_next = s_apb.pwdata;
m_axil_wstrb_next = s_apb.pstrb;
m_axil_auser_next = s_apb.pauser;
m_axil_wuser_next = s_apb.pwuser;
if (s_apb.psel && s_apb.penable && !s_apb.pready) begin
if (s_apb.pwrite) begin
m_axil_awvalid_next = 1'b1;
m_axil_wvalid_next = 1'b1;
m_axil_bready_next = 1'b1;
end else begin
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b1;
end
state_next = STATE_DATA;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DATA: begin
if (s_apb.pwrite) begin
m_axil_bready_next = 1'b1;
end else begin
m_axil_rready_next = 1'b1;
end
s_apb_pready_next = 1'b0;
s_apb_prdata_next = m_axil_rd.rdata;
s_apb_pslverr_next = s_apb.pwrite ? m_axil_wr.bresp[1] : m_axil_rd.rresp[1];
s_apb_pruser_next = m_axil_rd.ruser;
s_apb_pbuser_next = m_axil_wr.buser;
if (s_apb.pwrite ? (m_axil_wr.bready && m_axil_wr.bvalid) : (m_axil_rd.rready && m_axil_rd.rvalid)) begin
m_axil_bready_next = 1'b0;
m_axil_rready_next = 1'b0;
s_apb_pready_next = 1'b1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_DATA;
end
end
endcase
end
always_ff @(posedge clk) begin
state_reg <= state_next;
s_apb_pready_reg <= s_apb_pready_next;
s_apb_prdata_reg <= s_apb_prdata_next;
s_apb_pslverr_reg <= s_apb_pslverr_next;
s_apb_pruser_reg <= s_apb_pruser_next;
s_apb_pbuser_reg <= s_apb_pbuser_next;
m_axil_addr_reg <= m_axil_addr_next;
m_axil_prot_reg <= m_axil_prot_next;
m_axil_auser_reg <= m_axil_auser_next;
m_axil_awvalid_reg <= m_axil_awvalid_next;
m_axil_wdata_reg <= m_axil_wdata_next;
m_axil_wstrb_reg <= m_axil_wstrb_next;
m_axil_wuser_reg <= m_axil_wuser_next;
m_axil_wvalid_reg <= m_axil_wvalid_next;
m_axil_bready_reg <= m_axil_bready_next;
m_axil_arvalid_reg <= m_axil_arvalid_next;
m_axil_rready_reg <= m_axil_rready_next;
if (rst) begin
state_reg <= STATE_IDLE;
s_apb_pready_reg <= 1'b0;
m_axil_awvalid_reg <= 1'b0;
m_axil_wvalid_reg <= 1'b0;
m_axil_bready_reg <= 1'b0;
m_axil_arvalid_reg <= 1'b0;
m_axil_rready_reg <= 1'b0;
end
end
end else if (AXIL_BYTE_LANES > APB_BYTE_LANES) begin : upsize
// output is wider; upsize
localparam [0:0]
STATE_IDLE = 1'd0,
STATE_DATA = 1'd1;
logic [0:0] state_reg = STATE_IDLE, state_next;
logic s_apb_pready_reg = 1'b0, s_apb_pready_next;
logic [APB_DATA_W-1:0] s_apb_prdata_reg = '0, s_apb_prdata_next;
logic s_apb_pslverr_reg = 1'b0, s_apb_pslverr_next;
logic [PRUSER_W-1:0] s_apb_pruser_reg = '0, s_apb_pruser_next;
logic [PBUSER_W-1:0] s_apb_pbuser_reg = '0, s_apb_pbuser_next;
logic [AXIL_ADDR_W-1:0] m_axil_addr_reg = '0, m_axil_addr_next;
logic [2:0] m_axil_prot_reg = 3'd0, m_axil_prot_next;
logic [AUSER_W-1:0] m_axil_auser_reg = '0, m_axil_auser_next;
logic m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
logic [AXIL_DATA_W-1:0] m_axil_wdata_reg = '0, m_axil_wdata_next;
logic [AXIL_STRB_W-1:0] m_axil_wstrb_reg = '0, m_axil_wstrb_next;
logic [WUSER_W-1:0] m_axil_wuser_reg = '0, m_axil_wuser_next;
logic m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
logic m_axil_bready_reg = 1'b0, m_axil_bready_next;
logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
logic m_axil_rready_reg = 1'b0, m_axil_rready_next;
assign s_apb.pready = s_apb_pready_reg;
assign s_apb.prdata = s_apb_prdata_reg;
assign s_apb.pslverr = s_apb_pslverr_reg;
assign s_apb.pruser = PRUSER_EN ? s_apb_pruser_reg : '0;
assign s_apb.pbuser = PBUSER_EN ? s_apb_pbuser_reg : '0;
assign m_axil_wr.awaddr = m_axil_addr_reg;
assign m_axil_wr.awprot = m_axil_prot_reg;
assign m_axil_wr.awuser = AWUSER_EN ? m_axil_auser_reg : '0;
assign m_axil_wr.awvalid = m_axil_awvalid_reg;
assign m_axil_wr.wdata = m_axil_wdata_reg;
assign m_axil_wr.wstrb = m_axil_wstrb_reg;
assign m_axil_wr.wuser = WUSER_EN ? m_axil_wuser_reg : '0;
assign m_axil_wr.wvalid = m_axil_wvalid_reg;
assign m_axil_wr.bready = m_axil_bready_reg;
assign m_axil_rd.araddr = m_axil_addr_reg;
assign m_axil_rd.arprot = m_axil_prot_reg;
assign m_axil_rd.aruser = ARUSER_EN ? m_axil_auser_reg : '0;
assign m_axil_rd.arvalid = m_axil_arvalid_reg;
assign m_axil_rd.rready = m_axil_rready_reg;
always_comb begin
state_next = STATE_IDLE;
s_apb_pready_next = 1'b0;
s_apb_prdata_next = s_apb_prdata_reg;
s_apb_pslverr_next = s_apb_pslverr_reg;
s_apb_pruser_next = s_apb_pruser_reg;
s_apb_pbuser_next = s_apb_pbuser_reg;
m_axil_addr_next = m_axil_addr_reg;
m_axil_prot_next = m_axil_prot_reg;
m_axil_auser_next = m_axil_auser_reg;
m_axil_awvalid_next = m_axil_awvalid_reg && !m_axil_wr.awready;
m_axil_wdata_next = m_axil_wdata_reg;
m_axil_wstrb_next = m_axil_wstrb_reg;
m_axil_wuser_next = m_axil_wuser_reg;
m_axil_wvalid_next = m_axil_wvalid_reg && !m_axil_wr.wready;
m_axil_bready_next = 1'b0;
m_axil_arvalid_next = m_axil_arvalid_reg && !m_axil_rd.arready;
m_axil_rready_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
m_axil_addr_next = s_apb.paddr;
m_axil_prot_next = s_apb.pprot;
m_axil_wdata_next = {(AXIL_BYTE_LANES/APB_BYTE_LANES){s_apb.pwdata}};
m_axil_wstrb_next = '0;
m_axil_wstrb_next[s_apb.paddr[AXIL_ADDR_BIT_OFFSET - 1:APB_ADDR_BIT_OFFSET] * APB_STRB_W +: APB_STRB_W] = s_apb.pstrb;
m_axil_auser_next = s_apb.pauser;
m_axil_wuser_next = s_apb.pwuser;
if (s_apb.psel && s_apb.penable && !s_apb.pready) begin
if (s_apb.pwrite) begin
m_axil_awvalid_next = 1'b1;
m_axil_wvalid_next = 1'b1;
m_axil_bready_next = 1'b1;
end else begin
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b1;
end
state_next = STATE_DATA;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DATA: begin
if (s_apb.pwrite) begin
m_axil_bready_next = 1'b1;
end else begin
m_axil_rready_next = 1'b1;
end
s_apb_pready_next = 1'b0;
s_apb_prdata_next = m_axil_rd.rdata[m_axil_addr_reg[AXIL_ADDR_BIT_OFFSET - 1:APB_ADDR_BIT_OFFSET] * APB_DATA_W +: APB_DATA_W];
s_apb_pslverr_next = s_apb.pwrite ? m_axil_wr.bresp[1] : m_axil_rd.rresp[1];
s_apb_pruser_next = m_axil_rd.ruser;
s_apb_pbuser_next = m_axil_wr.buser;
if (s_apb.pwrite ? (m_axil_wr.bready && m_axil_wr.bvalid) : (m_axil_rd.rready && m_axil_rd.rvalid)) begin
m_axil_bready_next = 1'b0;
m_axil_rready_next = 1'b0;
s_apb_pready_next = 1'b1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_DATA;
end
end
endcase
end
always_ff @(posedge clk) begin
state_reg <= state_next;
s_apb_pready_reg <= s_apb_pready_next;
s_apb_prdata_reg <= s_apb_prdata_next;
s_apb_pslverr_reg <= s_apb_pslverr_next;
s_apb_pruser_reg <= s_apb_pruser_next;
s_apb_pbuser_reg <= s_apb_pbuser_next;
m_axil_addr_reg <= m_axil_addr_next;
m_axil_prot_reg <= m_axil_prot_next;
m_axil_auser_reg <= m_axil_auser_next;
m_axil_awvalid_reg <= m_axil_awvalid_next;
m_axil_wdata_reg <= m_axil_wdata_next;
m_axil_wstrb_reg <= m_axil_wstrb_next;
m_axil_wuser_reg <= m_axil_wuser_next;
m_axil_wvalid_reg <= m_axil_wvalid_next;
m_axil_bready_reg <= m_axil_bready_next;
m_axil_arvalid_reg <= m_axil_arvalid_next;
m_axil_rready_reg <= m_axil_rready_next;
if (rst) begin
state_reg <= STATE_IDLE;
s_apb_pready_reg <= 1'b0;
m_axil_awvalid_reg <= 1'b0;
m_axil_wvalid_reg <= 1'b0;
m_axil_bready_reg <= 1'b0;
m_axil_arvalid_reg <= 1'b0;
m_axil_rready_reg <= 1'b0;
end
end
end else begin : downsize
// output is narrower; downsize
// output bus is wider
localparam DATA_W = APB_DATA_W;
localparam STRB_W = APB_STRB_W;
// required number of segments in wider bus
localparam SEG_COUNT = APB_BYTE_LANES / AXIL_BYTE_LANES;
localparam SEG_COUNT_W = $clog2(SEG_COUNT);
// data width and keep width per segment
localparam SEG_DATA_W = DATA_W / SEG_COUNT;
localparam SEG_STRB_W = STRB_W / SEG_COUNT;
localparam [0:0]
STATE_IDLE = 1'd0,
STATE_DATA = 1'd1;
logic [0:0] state_reg = STATE_IDLE, state_next;
logic [DATA_W-1:0] data_reg = '0, data_next;
logic [STRB_W-1:0] strb_reg = '0, strb_next;
logic [SEG_COUNT_W-1:0] current_seg_reg = '0, current_seg_next;
logic s_apb_pready_reg = 1'b0, s_apb_pready_next;
logic [APB_DATA_W-1:0] s_apb_prdata_reg = '0, s_apb_prdata_next;
logic s_apb_pslverr_reg = 1'b0, s_apb_pslverr_next;
logic [PRUSER_W-1:0] s_apb_pruser_reg = '0, s_apb_pruser_next;
logic [PBUSER_W-1:0] s_apb_pbuser_reg = '0, s_apb_pbuser_next;
logic [AXIL_ADDR_W-1:0] m_axil_addr_reg = '0, m_axil_addr_next;
logic [2:0] m_axil_prot_reg = 3'd0, m_axil_prot_next;
logic [AUSER_W-1:0] m_axil_auser_reg = '0, m_axil_auser_next;
logic m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
logic [AXIL_DATA_W-1:0] m_axil_wdata_reg = '0, m_axil_wdata_next;
logic [AXIL_STRB_W-1:0] m_axil_wstrb_reg = '0, m_axil_wstrb_next;
logic [WUSER_W-1:0] m_axil_wuser_reg = '0, m_axil_wuser_next;
logic m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
logic m_axil_bready_reg = 1'b0, m_axil_bready_next;
logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
logic m_axil_rready_reg = 1'b0, m_axil_rready_next;
assign s_apb.pready = s_apb_pready_reg;
assign s_apb.prdata = s_apb_prdata_reg;
assign s_apb.pslverr = s_apb_pslverr_reg;
assign s_apb.pruser = PRUSER_EN ? s_apb_pruser_reg : '0;
assign s_apb.pbuser = PBUSER_EN ? s_apb_pbuser_reg : '0;
assign m_axil_wr.awaddr = m_axil_addr_reg;
assign m_axil_wr.awprot = m_axil_prot_reg;
assign m_axil_wr.awuser = AWUSER_EN ? m_axil_auser_reg : '0;
assign m_axil_wr.awvalid = m_axil_awvalid_reg;
assign m_axil_wr.wdata = m_axil_wdata_reg;
assign m_axil_wr.wstrb = m_axil_wstrb_reg;
assign m_axil_wr.wuser = WUSER_EN ? m_axil_wuser_reg : '0;
assign m_axil_wr.wvalid = m_axil_wvalid_reg;
assign m_axil_wr.bready = m_axil_bready_reg;
assign m_axil_rd.araddr = m_axil_addr_reg;
assign m_axil_rd.arprot = m_axil_prot_reg;
assign m_axil_rd.aruser = ARUSER_EN ? m_axil_auser_reg : '0;
assign m_axil_rd.arvalid = m_axil_arvalid_reg;
assign m_axil_rd.rready = m_axil_rready_reg;
always_comb begin
state_next = STATE_IDLE;
data_next = data_reg;
strb_next = strb_reg;
current_seg_next = current_seg_reg;
s_apb_pready_next = 1'b0;
s_apb_prdata_next = s_apb_prdata_reg;
s_apb_pslverr_next = s_apb_pslverr_reg;
s_apb_pruser_next = s_apb_pruser_reg;
s_apb_pbuser_next = s_apb_pbuser_reg;
m_axil_addr_next = m_axil_addr_reg;
m_axil_prot_next = m_axil_prot_reg;
m_axil_auser_next = m_axil_auser_reg;
m_axil_awvalid_next = m_axil_awvalid_reg && !m_axil_wr.awready;
m_axil_wdata_next = m_axil_wdata_reg;
m_axil_wstrb_next = m_axil_wstrb_reg;
m_axil_wuser_next = m_axil_wuser_reg;
m_axil_wvalid_next = m_axil_wvalid_reg && !m_axil_wr.wready;
m_axil_bready_next = 1'b0;
m_axil_arvalid_next = m_axil_arvalid_reg && !m_axil_rd.arready;
m_axil_rready_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
current_seg_next = s_apb.paddr[AXIL_ADDR_BIT_OFFSET +: SEG_COUNT_W];
m_axil_addr_next = s_apb.paddr;
m_axil_prot_next = s_apb.pprot;
data_next = s_apb.pwdata;
strb_next = s_apb.pstrb;
m_axil_wdata_next = data_next[current_seg_next*SEG_DATA_W +: SEG_DATA_W];
m_axil_wstrb_next = strb_next[current_seg_next*SEG_STRB_W +: SEG_STRB_W];
m_axil_auser_next = s_apb.pauser;
m_axil_wuser_next = s_apb.pwuser;
s_apb_pslverr_next = 1'b0;
if (s_apb.psel && s_apb.penable && !s_apb.pready) begin
if (s_apb.pwrite) begin
m_axil_awvalid_next = 1'b1;
m_axil_wvalid_next = 1'b1;
m_axil_bready_next = 1'b1;
end else begin
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b1;
end
state_next = STATE_DATA;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DATA: begin
if (s_apb.pwrite) begin
m_axil_bready_next = 1'b1;
end else begin
m_axil_rready_next = 1'b1;
end
s_apb_pready_next = 1'b0;
s_apb_prdata_next[current_seg_reg*SEG_DATA_W +: SEG_DATA_W] = m_axil_rd.rdata;
if (s_apb.pwrite ? m_axil_wr.bresp[1] : m_axil_rd.rresp[1]) begin
s_apb_pslverr_next = 1'b1;
end
s_apb_pruser_next = m_axil_rd.ruser;
s_apb_pbuser_next = m_axil_wr.buser;
if (s_apb.pwrite ? (m_axil_wr.bready && m_axil_wr.bvalid) : (m_axil_rd.rready && m_axil_rd.rvalid)) begin
m_axil_bready_next = 1'b0;
m_axil_rready_next = 1'b0;
current_seg_next = current_seg_reg + 1;
m_axil_addr_next = (m_axil_addr_reg & AXIL_ADDR_MASK) + SEG_STRB_W;
m_axil_wdata_next = data_next[current_seg_next*SEG_DATA_W +: SEG_DATA_W];
m_axil_wstrb_next = strb_next[current_seg_next*SEG_STRB_W +: SEG_STRB_W];
if (current_seg_reg == SEG_COUNT_W'(SEG_COUNT-1)) begin
s_apb_pready_next = 1'b1;
state_next = STATE_IDLE;
end else begin
if (s_apb.pwrite) begin
m_axil_awvalid_next = 1'b1;
m_axil_wvalid_next = 1'b1;
m_axil_bready_next = 1'b1;
end else begin
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b1;
end
state_next = STATE_DATA;
end
end else begin
state_next = STATE_DATA;
end
end
endcase
end
always_ff @(posedge clk) begin
state_reg <= state_next;
data_reg <= data_next;
strb_reg <= strb_next;
current_seg_reg <= current_seg_next;
s_apb_pready_reg <= s_apb_pready_next;
s_apb_prdata_reg <= s_apb_prdata_next;
s_apb_pslverr_reg <= s_apb_pslverr_next;
s_apb_pruser_reg <= s_apb_pruser_next;
s_apb_pbuser_reg <= s_apb_pbuser_next;
m_axil_addr_reg <= m_axil_addr_next;
m_axil_prot_reg <= m_axil_prot_next;
m_axil_auser_reg <= m_axil_auser_next;
m_axil_awvalid_reg <= m_axil_awvalid_next;
m_axil_wdata_reg <= m_axil_wdata_next;
m_axil_wstrb_reg <= m_axil_wstrb_next;
m_axil_wuser_reg <= m_axil_wuser_next;
m_axil_wvalid_reg <= m_axil_wvalid_next;
m_axil_bready_reg <= m_axil_bready_next;
m_axil_arvalid_reg <= m_axil_arvalid_next;
m_axil_rready_reg <= m_axil_rready_next;
if (rst) begin
state_reg <= STATE_IDLE;
s_apb_pready_reg <= 1'b0;
m_axil_awvalid_reg <= 1'b0;
m_axil_wvalid_reg <= 1'b0;
m_axil_bready_reg <= 1'b0;
m_axil_arvalid_reg <= 1'b0;
m_axil_rready_reg <= 1'b0;
end
end
end
endmodule
`resetall

64
src/apb/tb/taxi_apb_axil_adapter/Makefile Normal file
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# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2020-2026 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_apb_axil_adapter
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
VERILOG_SOURCES += $(RTL_DIR)/taxi_apb_if.sv
VERILOG_SOURCES += $(TAXI_SRC_DIR)/axi/rtl/taxi_axil_if.sv
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_ADDR_W := 32
export PARAM_APB_DATA_W := 32
export PARAM_APB_STRB_W := $(shell expr $(PARAM_APB_DATA_W) / 8 )
export PARAM_AXIL_DATA_W := 32
export PARAM_AXIL_STRB_W := $(shell expr $(PARAM_AXIL_DATA_W) / 8 )
export PARAM_PAUSER_EN := 0
export PARAM_PAUSER_W := 1
export PARAM_PWUSER_EN := 0
export PARAM_PWUSER_W := 1
export PARAM_PBUSER_EN := 0
export PARAM_PBUSER_W := 1
export PARAM_PRUSER_EN := 0
export PARAM_PRUSER_W := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

242
src/apb/tb/taxi_apb_axil_adapter/test_taxi_apb_axil_adapter.py Normal file
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#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2020-2026 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import random
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory
from cocotbext.axi import ApbBus, ApbMaster, AxiLiteBus, AxiLiteRam
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.apb_master = ApbMaster(ApbBus.from_entity(dut.s_apb), dut.clk, dut.rst)
self.axil_ram = AxiLiteRam(AxiLiteBus.from_entity(dut.m_axil), dut.clk, dut.rst, size=2**16)
def set_idle_generator(self, generator=None):
if generator:
self.apb_master.set_pause_generator(generator())
self.axil_ram.write_if.b_channel.set_pause_generator(generator())
self.axil_ram.read_if.r_channel.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.axil_ram.write_if.aw_channel.set_pause_generator(generator())
self.axil_ram.write_if.w_channel.set_pause_generator(generator())
self.axil_ram.read_if.ar_channel.set_pause_generator(generator())
async def cycle_reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = tb.apb_master.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
tb.axil_ram.write(addr-128, b'\xaa'*(length+256))
await tb.apb_master.write(addr, test_data)
tb.log.debug("%s", tb.axil_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
assert tb.axil_ram.read(addr, length) == test_data
assert tb.axil_ram.read(addr-1, 1) == b'\xaa'
assert tb.axil_ram.read(addr+length, 1) == b'\xaa'
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = tb.apb_master.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
tb.axil_ram.write(addr, test_data)
data = await tb.apb_master.read(addr, length)
assert data.data == test_data
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
async def worker(master, offset, aperture, count=16):
for k in range(count):
length = random.randint(1, min(32, aperture))
addr = offset+random.randint(0, aperture-length)
test_data = bytearray([x % 256 for x in range(length)])
await Timer(random.randint(1, 100), 'ns')
await master.write(addr, test_data)
await Timer(random.randint(1, 100), 'ns')
data = await master.read(addr, length)
assert data.data == test_data
workers = []
for k in range(16):
workers.append(cocotb.start_soon(worker(tb.apb_master, k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
if getattr(cocotb, 'top', None) is not None:
for test in [run_test_write, run_test_read]:
factory = TestFactory(test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
factory = TestFactory(run_stress_test)
factory.generate_tests()
# cocotb-test
tests_dir = os.path.abspath(os.path.dirname(__file__))
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("axil_data_w", [8, 16, 32])
@pytest.mark.parametrize("apb_data_w", [8, 16, 32])
def test_taxi_apb_axil_adapter(request, apb_data_w, axil_data_w):
dut = "taxi_apb_axil_adapter"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.sv"),
os.path.join(rtl_dir, "taxi_apb_if.sv"),
os.path.join(taxi_src_dir, "axi", "rtl", "taxi_axil_if.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['ADDR_W'] = 32
parameters['APB_DATA_W'] = apb_data_w
parameters['APB_STRB_W'] = parameters['APB_DATA_W'] // 8
parameters['AXIL_DATA_W'] = axil_data_w
parameters['AXIL_STRB_W'] = parameters['AXIL_DATA_W'] // 8
parameters["PAUSER_EN"] = 0
parameters["PAUSER_W"] = 1
parameters["PWUSER_EN"] = 0
parameters["PWUSER_W"] = 1
parameters["PRUSER_EN"] = 0
parameters["PRUSER_W"] = 1
parameters["PBUSER_EN"] = 0
parameters["PBUSER_W"] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

90
src/apb/tb/taxi_apb_axil_adapter/test_taxi_apb_axil_adapter.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2026 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* APB to AXI4 lite adapter testbench
*/
module test_taxi_apb_axil_adapter #
(
/* verilator lint_off WIDTHTRUNC */
parameter ADDR_W = 32,
parameter APB_DATA_W = 32,
parameter APB_STRB_W = (APB_DATA_W/8),
parameter AXIL_DATA_W = 32,
parameter AXIL_STRB_W = (AXIL_DATA_W/8),
parameter logic PAUSER_EN = 1'b0,
parameter PAUSER_W = 1,
parameter logic PWUSER_EN = 1'b0,
parameter PWUSER_W = 1,
parameter logic PRUSER_EN = 1'b0,
parameter PRUSER_W = 1,
parameter logic PBUSER_EN = 1'b0,
parameter PBUSER_W = 1
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_apb_if #(
.DATA_W(APB_DATA_W),
.ADDR_W(ADDR_W),
.STRB_W(APB_STRB_W),
.PAUSER_EN(PAUSER_EN),
.PAUSER_W(PAUSER_W),
.PWUSER_EN(PWUSER_EN),
.PWUSER_W(PWUSER_W),
.PRUSER_EN(PRUSER_EN),
.PRUSER_W(PRUSER_W),
.PBUSER_EN(PBUSER_EN),
.PBUSER_W(PBUSER_W)
) s_apb();
taxi_axil_if #(
.DATA_W(AXIL_DATA_W),
.ADDR_W(ADDR_W),
.STRB_W(AXIL_STRB_W),
.AWUSER_EN(PAUSER_EN),
.AWUSER_W(PAUSER_W),
.WUSER_EN(PWUSER_EN),
.WUSER_W(PWUSER_W),
.BUSER_EN(PBUSER_EN),
.BUSER_W(PBUSER_W),
.ARUSER_EN(PAUSER_EN),
.ARUSER_W(PAUSER_W),
.RUSER_EN(PRUSER_EN),
.RUSER_W(PRUSER_W)
) m_axil();
taxi_apb_axil_adapter
uut (
.clk(clk),
.rst(rst),
/*
* APB slave interface
*/
.s_apb(s_apb),
/*
* AXI4-Lite master interface
*/
.m_axil_wr(m_axil),
.m_axil_rd(m_axil)
);
endmodule
`resetall