From 59a420b4127f8b5451b1414956b5e8c86f626865 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 14 Apr 2026 22:46:47 -0700 Subject: [PATCH] eth: Minor example design cleanup Signed-off-by: Alex Forencich --- src/eth/example/HTG940/fpga/rtl/fpga.sv | 14 +++++++------- src/eth/example/HTG940/fpga/rtl/fpga_core.sv | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/eth/example/HTG940/fpga/rtl/fpga.sv b/src/eth/example/HTG940/fpga/rtl/fpga.sv index adb077d..f3ae2f5 100644 --- a/src/eth/example/HTG940/fpga/rtl/fpga.sv +++ b/src/eth/example/HTG940/fpga/rtl/fpga.sv @@ -22,7 +22,7 @@ module fpga # // vendor ("GENERIC", "XILINX", "ALTERA") parameter string VENDOR = "XILINX", // device family - parameter string FAMILY = "zynquplus", + parameter string FAMILY = "virtexuplus", // Use 90 degree clock for RGMII transmit parameter logic USE_CLK90 = 1'b0 ) @@ -88,13 +88,13 @@ wire mmcm_locked; wire mmcm_clkfb; IBUFGDS #( - .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE") + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") ) ref_clk_ibufg_inst ( - .O (ref_clk_ibufg), - .I (ref_clk_p), - .IB (ref_clk_n) + .O (ref_clk_ibufg), + .I (ref_clk_p), + .IB (ref_clk_n) ); // MMCM instance @@ -269,7 +269,7 @@ idelayctrl_inst ( ); for (genvar n = 0; n < 4; n = n + 1) begin : phy_rxd_idelay_bit - + IDELAYE3 #( .DELAY_SRC("IDATAIN"), .CASCADE("NONE"), diff --git a/src/eth/example/HTG940/fpga/rtl/fpga_core.sv b/src/eth/example/HTG940/fpga/rtl/fpga_core.sv index c8a40a4..6087413 100644 --- a/src/eth/example/HTG940/fpga/rtl/fpga_core.sv +++ b/src/eth/example/HTG940/fpga/rtl/fpga_core.sv @@ -22,7 +22,7 @@ module fpga_core # // vendor ("GENERIC", "XILINX", "ALTERA") parameter string VENDOR = "XILINX", // device family - parameter string FAMILY = "zynquplus", + parameter string FAMILY = "virtexuplus", // Use 90 degree clock for RGMII transmit parameter logic USE_CLK90 = 1'b1 )