dma: Add AXI streaming DMA module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-12-07 16:28:40 -08:00 · 2025-11-03 17:14:24 -08:00
parent 9442bb7fbb
commit 5b0c83fc57
8 changed files with 2115 additions and 0 deletions
--- a/README.md
+++ b/README.md
@@ -64,6 +64,7 @@ To facilitate the dual-license model, contributions to the project can only be a
    *  SV interface for segmented RAM
    *  SV interface for DMA descriptors
    *  AXI central DMA
+    *  AXI streaming DMA
    *  Segmented SDP RAM
    *  Segmented dual-clock SDP RAM
 *  Ethernet