diff --git a/src/axi/rtl/taxi_axi_ram_if_rd.sv b/src/axi/rtl/taxi_axi_ram_if_rd.sv
index 3744bb6..f004d0b 100644
--- a/src/axi/rtl/taxi_axi_ram_if_rd.sv
+++ b/src/axi/rtl/taxi_axi_ram_if_rd.sv
@@ -81,6 +81,12 @@ if (2**$clog2(BYTE_LANES) != BYTE_LANES)
 if (s_axi_rd.ADDR_W < ADDR_W)
     $fatal(0, "Error: AXI address width is insufficient (instance %m)");
 
+if (s_axi_rd.ARUSER_EN && s_axi_rd.ARUSER_W > AUSER_W)
+    $fatal(0, "Error: AUESR_W setting is insufficient (instance %m)");
+
+if (s_axi_rd.RUSER_EN && s_axi_rd.RUSER_W > RUSER_W)
+    $fatal(0, "Error: RUESR_W setting is insufficient (instance %m)");
+
 typedef enum logic [0:0] {
     STATE_IDLE,
     STATE_BURST
@@ -161,7 +167,7 @@ always_comb begin
                 read_prot_next = s_axi_rd.arprot;
                 read_qos_next = s_axi_rd.arqos;
                 read_region_next = s_axi_rd.arregion;
-                read_auser_next = s_axi_rd.aruser;
+                read_auser_next = AUSER_W'(s_axi_rd.aruser);
                 read_count_next = s_axi_rd.arlen;
                 read_size_next = s_axi_rd.arsize <= 3'($clog2(STRB_W)) ? s_axi_rd.arsize : 3'($clog2(STRB_W));
                 read_burst_next = s_axi_rd.arburst;
diff --git a/src/axi/rtl/taxi_axi_ram_if_rdwr.sv b/src/axi/rtl/taxi_axi_ram_if_rdwr.sv
index 9d96243..d7f109d 100644
--- a/src/axi/rtl/taxi_axi_ram_if_rdwr.sv
+++ b/src/axi/rtl/taxi_axi_ram_if_rdwr.sv
@@ -31,8 +31,6 @@ module taxi_axi_ram_if_rdwr #
     parameter WUSER_W = 1,
     // Width of ruser signal
     parameter RUSER_W = 1,
-    // Width of auser output
-    // parameter AUSER_W = (ARUSER_EN && (!AWUSER_EN || ARUSER_W > AWUSER_W)) ? ARUSER_W : AWUSER_W,
     // Extra pipeline register on output
     parameter logic PIPELINE_OUTPUT = 1'b0,
     // Interleave read and write burst cycles
diff --git a/src/axi/rtl/taxi_axi_ram_if_wr.sv b/src/axi/rtl/taxi_axi_ram_if_wr.sv
index 506ff9e..6b67031 100644
--- a/src/axi/rtl/taxi_axi_ram_if_wr.sv
+++ b/src/axi/rtl/taxi_axi_ram_if_wr.sv
@@ -76,6 +76,12 @@ if (2**$clog2(BYTE_LANES) != BYTE_LANES)
 if (s_axi_wr.ADDR_W < ADDR_W)
     $fatal(0, "Error: AXI address width is insufficient (instance %m)");
 
+if (s_axi_wr.AWUSER_EN && s_axi_wr.AWUSER_W > AUSER_W)
+    $fatal(0, "Error: AUESR_W setting is insufficient (instance %m)");
+
+if (s_axi_wr.WUSER_EN && s_axi_wr.WUSER_W > WUSER_W)
+    $fatal(0, "Error: WUESR_W setting is insufficient (instance %m)");
+
 typedef enum logic [1:0] {
     STATE_IDLE,
     STATE_BURST,
@@ -156,7 +162,7 @@ always_comb begin
                 write_prot_next = s_axi_wr.awprot;
                 write_qos_next = s_axi_wr.awqos;
                 write_region_next = s_axi_wr.awregion;
-                write_auser_next = s_axi_wr.awuser;
+                write_auser_next = AUSER_W'(s_axi_wr.awuser);
                 write_count_next = s_axi_wr.awlen;
                 write_size_next = s_axi_wr.awsize <= 3'($clog2(STRB_W)) ? s_axi_wr.awsize : 3'($clog2(STRB_W));
                 write_burst_next = s_axi_wr.awburst;