diff --git a/src/eth/rtl/taxi_axis_basex_rx_8.sv b/src/eth/rtl/taxi_axis_basex_rx_8.sv index af18a7d..a235bce 100644 --- a/src/eth/rtl/taxi_axis_basex_rx_8.sv +++ b/src/eth/rtl/taxi_axis_basex_rx_8.sv @@ -493,21 +493,9 @@ always_ff @(posedge clk) begin rx_an_cfg_valid_reg <= 1'b0; - start_packet_int_reg <= 1'b0; start_packet_reg <= 1'b0; - if (start_packet_int_reg) begin - ptp_ts_out_reg <= ptp_ts; - start_packet_reg <= 1'b1; - end - if (!GBX_IF_EN || encoded_rx_data_valid) begin - if (in_frame_reg) begin - in_frame_reg <= encoded_rx_data_k == 0; - end else if (encoded_rx_data_k == 0 && encoded_rx_data == ETH_SFD) begin - in_frame_reg <= 1'b1; - start_packet_int_reg <= 1'b1; - end if (!SGMII_EN || !rep_stall_reg) begin encoded_rx_data_d0_reg <= encoded_rx_data; @@ -519,6 +507,21 @@ always_ff @(posedge clk) begin encoded_rx_data_k_d0_reg <= encoded_rx_data_k; end + if (start_packet_int_reg) begin + ptp_ts_out_reg <= ptp_ts; + if (!SGMII_EN || ((rep_cnt_reg == 0 || rep_cnt_reg[0]) && !rep_stall_reg)) begin + start_packet_int_reg <= 1'b0; + start_packet_reg <= 1'b1; + end + end + + if (in_frame_reg) begin + in_frame_reg <= encoded_rx_data_k == 0; + end else if (encoded_rx_data_k == 0 && encoded_rx_data == ETH_SFD) begin + in_frame_reg <= 1'b1; + start_packet_int_reg <= 1'b1; + end + input_k28p5_d0_reg <= 1'b0; input_i_d0_reg <= 1'b0; input_c_d0_reg <= 1'b0; diff --git a/src/eth/tb/basex.py b/src/eth/tb/basex.py index 9225998..3926bbf 100644 --- a/src/eth/tb/basex.py +++ b/src/eth/tb/basex.py @@ -455,7 +455,7 @@ class BaseXSerdesSource(): d = frame.data[frame_offset] if frame.sim_time_sfd is None and not in_pre: frame.sim_time_sfd = sim_time + (clk_period // self.byte_lanes * k) - gbx_delay - if d == EthPre.SFD: + if d == EthPre.SFD and (not self.gmii_rep_count or rep_cnt == 1): in_pre = False if frame.error[frame_offset]: # /V/