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eth: Use SV enums in MAC logic

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-02-27 15:04:08 -08:00
parent 8d7cdaa689
commit 5df2aa3cfd
12 changed files with 266 additions and 179 deletions
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38
src/eth/rtl/taxi_axis_baser_rx_32.sv
View File

@@ -92,11 +92,12 @@ if (m_axis_rx.DATA_W != DATA_W)
if (m_axis_rx.USER_W != USER_W)
$fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)");
localparam [7:0]
typedef enum logic [7:0] {
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
ETH_SFD = 8'hD5
} eth_pre_t;
localparam [6:0]
typedef enum logic [6:0] {
CTRL_IDLE = 7'h00,
CTRL_LPI = 7'h06,
CTRL_ERROR = 7'h1e,
@@ -105,17 +106,20 @@ localparam [6:0]
CTRL_RES_2 = 7'h4b,
CTRL_RES_3 = 7'h55,
CTRL_RES_4 = 7'h66,
CTRL_RES_5 = 7'h78;
CTRL_RES_5 = 7'h78
} baser_ctrl_t;
localparam [3:0]
typedef enum logic [3:0] {
O_SEQ_OS = 4'h0,
O_SIG_OS = 4'hf;
O_SIG_OS = 4'hf
} baser_o_t;
localparam [1:0]
typedef enum logic [1:0] {
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
SYNC_CTRL = 2'b01
} baser_sync_t;
localparam [7:0]
typedef enum logic [7:0] {
BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
@@ -130,15 +134,17 @@ localparam [7:0]
BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff // D6 D5 D4 D3 D2 D1 D0 BT
} baser_block_type_t;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PREAMBLE = 2'd1,
STATE_PAYLOAD = 2'd2,
STATE_LAST = 2'd3;
typedef enum logic [1:0] {
STATE_IDLE,
STATE_PREAMBLE,
STATE_PAYLOAD,
STATE_LAST
} state_t;
logic [1:0] state_reg = STATE_IDLE, state_next;
state_t state_reg = STATE_IDLE, state_next;
// datapath control signals
logic reset_crc;

36
src/eth/rtl/taxi_axis_baser_rx_64.sv
View File

@@ -93,11 +93,12 @@ if (m_axis_rx.DATA_W != DATA_W)
if (m_axis_rx.USER_W != USER_W)
$fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)");
localparam [7:0]
typedef enum logic [7:0] {
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
ETH_SFD = 8'hD5
} eth_pre_t;
localparam [6:0]
typedef enum logic [6:0] {
CTRL_IDLE = 7'h00,
CTRL_LPI = 7'h06,
CTRL_ERROR = 7'h1e,
@@ -106,17 +107,20 @@ localparam [6:0]
CTRL_RES_2 = 7'h4b,
CTRL_RES_3 = 7'h55,
CTRL_RES_4 = 7'h66,
CTRL_RES_5 = 7'h78;
CTRL_RES_5 = 7'h78
} baser_ctrl_t;
localparam [3:0]
typedef enum logic [3:0] {
O_SEQ_OS = 4'h0,
O_SIG_OS = 4'hf;
O_SIG_OS = 4'hf
} baser_o_t;
localparam [1:0]
typedef enum logic [1:0] {
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
SYNC_CTRL = 2'b01
} baser_sync_t;
localparam [7:0]
typedef enum logic [7:0] {
BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
@@ -131,14 +135,16 @@ localparam [7:0]
BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff // D6 D5 D4 D3 D2 D1 D0 BT
} baser_block_type_t;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PAYLOAD = 2'd1,
STATE_LAST = 2'd2;
typedef enum logic [1:0] {
STATE_IDLE,
STATE_PAYLOAD,
STATE_LAST
} state_t;
logic [1:0] state_reg = STATE_IDLE, state_next;
state_t state_reg = STATE_IDLE, state_next;
logic lanes_swapped_reg = 1'b0;
logic lanes_swapped_d1_reg = 1'b0;

59
src/eth/rtl/taxi_axis_baser_tx_32.sv
View File

@@ -102,11 +102,12 @@ if (s_axis_tx.DATA_W != DATA_W)
if (s_axis_tx.USER_W != USER_W)
$fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)");
localparam [7:0]
typedef enum logic [7:0] {
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
ETH_SFD = 8'hD5
} eth_pre_t;
localparam [6:0]
typedef enum logic [6:0] {
CTRL_IDLE = 7'h00,
CTRL_LPI = 7'h06,
CTRL_ERROR = 7'h1e,
@@ -115,17 +116,20 @@ localparam [6:0]
CTRL_RES_2 = 7'h4b,
CTRL_RES_3 = 7'h55,
CTRL_RES_4 = 7'h66,
CTRL_RES_5 = 7'h78;
CTRL_RES_5 = 7'h78
} baser_ctrl_t;
localparam [3:0]
typedef enum logic [3:0] {
O_SEQ_OS = 4'h0,
O_SIG_OS = 4'hf;
O_SIG_OS = 4'hf
} baser_o_t;
localparam [1:0]
typedef enum logic [1:0] {
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
SYNC_CTRL = 2'b01
} baser_sync_t;
localparam [7:0]
typedef enum logic [7:0] {
BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
@@ -140,9 +144,10 @@ localparam [7:0]
BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff // D6 D5 D4 D3 D2 D1 D0 BT
} baser_block_type_t;
localparam [2:0]
typedef enum logic [2:0] {
OUTPUT_TYPE_IDLE = 3'd0,
OUTPUT_TYPE_ERROR = 3'd1,
OUTPUT_TYPE_START = 3'd2,
@@ -150,20 +155,22 @@ localparam [2:0]
OUTPUT_TYPE_TERM_0 = 3'd4,
OUTPUT_TYPE_TERM_1 = 3'd5,
OUTPUT_TYPE_TERM_2 = 3'd6,
OUTPUT_TYPE_TERM_3 = 3'd7;
OUTPUT_TYPE_TERM_3 = 3'd7
} out_type_t;
localparam [3:0]
STATE_IDLE = 4'd0,
STATE_PREAMBLE = 4'd1,
STATE_PAYLOAD = 4'd2,
STATE_PAD = 4'd3,
STATE_FCS_1 = 4'd4,
STATE_FCS_2 = 4'd5,
STATE_FCS_3 = 4'd6,
STATE_ERR = 4'd7,
STATE_IFG = 4'd8;
typedef enum logic [3:0] {
STATE_IDLE,
STATE_PREAMBLE,
STATE_PAYLOAD,
STATE_PAD,
STATE_FCS_1,
STATE_FCS_2,
STATE_FCS_3,
STATE_ERR,
STATE_IFG
} state_t;
logic [3:0] state_reg = STATE_IDLE, state_next;
state_t state_reg = STATE_IDLE, state_next;
// datapath control signals
logic reset_crc;
@@ -174,8 +181,8 @@ logic [EMPTY_W-1:0] s_empty_reg = '0, s_empty_next;
logic [DATA_W-1:0] fcs_output_data_0;
logic [DATA_W-1:0] fcs_output_data_1;
logic [2:0] fcs_output_type_0;
logic [2:0] fcs_output_type_1;
out_type_t fcs_output_type_0;
out_type_t fcs_output_type_1;
logic [7:0] ifg_offset;
@@ -216,7 +223,7 @@ logic [GBX_CNT-1:0] tx_gbx_sync_reg = '0;
logic [DATA_W-1:0] output_data_reg = '0, output_data_next;
logic [DATA_W-1:0] output_data_d1_reg = '0;
logic [2:0] output_type_reg = OUTPUT_TYPE_IDLE, output_type_next;
out_type_t output_type_reg = OUTPUT_TYPE_IDLE, output_type_next;
logic start_packet_reg = 1'b0, start_packet_next;

55
src/eth/rtl/taxi_axis_baser_tx_64.sv
View File

@@ -103,11 +103,12 @@ if (s_axis_tx.DATA_W != DATA_W)
if (s_axis_tx.USER_W != USER_W)
$fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)");
localparam [7:0]
typedef enum logic [7:0] {
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
ETH_SFD = 8'hD5
} eth_pre_t;
localparam [6:0]
typedef enum logic [6:0] {
CTRL_IDLE = 7'h00,
CTRL_LPI = 7'h06,
CTRL_ERROR = 7'h1e,
@@ -116,17 +117,20 @@ localparam [6:0]
CTRL_RES_2 = 7'h4b,
CTRL_RES_3 = 7'h55,
CTRL_RES_4 = 7'h66,
CTRL_RES_5 = 7'h78;
CTRL_RES_5 = 7'h78
} baser_ctrl_t;
localparam [3:0]
typedef enum logic [3:0] {
O_SEQ_OS = 4'h0,
O_SIG_OS = 4'hf;
O_SIG_OS = 4'hf
} baser_o_t;
localparam [1:0]
typedef enum logic [1:0] {
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
SYNC_CTRL = 2'b01
} baser_sync_t;
localparam [7:0]
typedef enum logic [7:0] {
BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
@@ -141,9 +145,10 @@ localparam [7:0]
BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff // D6 D5 D4 D3 D2 D1 D0 BT
} baser_block_type_t;
localparam [3:0]
typedef enum logic [3:0] {
OUTPUT_TYPE_IDLE = 4'd0,
OUTPUT_TYPE_ERROR = 4'd1,
OUTPUT_TYPE_START_0 = 4'd2,
@@ -156,18 +161,20 @@ localparam [3:0]
OUTPUT_TYPE_TERM_4 = 4'd12,
OUTPUT_TYPE_TERM_5 = 4'd13,
OUTPUT_TYPE_TERM_6 = 4'd14,
OUTPUT_TYPE_TERM_7 = 4'd15;
OUTPUT_TYPE_TERM_7 = 4'd15
} out_type_t;
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_PAYLOAD = 3'd1,
STATE_PAD = 3'd2,
STATE_FCS_1 = 3'd3,
STATE_FCS_2 = 3'd4,
STATE_ERR = 3'd5,
STATE_IFG = 3'd6;
typedef enum logic [2:0] {
STATE_IDLE,
STATE_PAYLOAD,
STATE_PAD,
STATE_FCS_1,
STATE_FCS_2,
STATE_ERR,
STATE_IFG
} state_t;
logic [2:0] state_reg = STATE_IDLE, state_next;
state_t state_reg = STATE_IDLE, state_next;
// datapath control signals
logic reset_crc;
@@ -184,8 +191,8 @@ logic [EMPTY_W-1:0] s_empty_reg = '0, s_empty_next;
logic [DATA_W-1:0] fcs_output_data_0;
logic [DATA_W-1:0] fcs_output_data_1;
logic [3:0] fcs_output_type_0;
logic [3:0] fcs_output_type_1;
out_type_t fcs_output_type_0;
out_type_t fcs_output_type_1;
logic [7:0] ifg_offset;
@@ -226,7 +233,7 @@ logic encoded_tx_hdr_valid_reg = 1'b0;
logic [GBX_CNT-1:0] tx_gbx_sync_reg = '0;
logic [DATA_W-1:0] output_data_reg = '0, output_data_next;
logic [3:0] output_type_reg = OUTPUT_TYPE_IDLE, output_type_next;
out_type_t output_type_reg = OUTPUT_TYPE_IDLE, output_type_next;
logic [1:0] start_packet_reg = 2'b00;

16
src/eth/rtl/taxi_axis_gmii_rx.sv
View File

@@ -87,16 +87,18 @@ if (m_axis_rx.DATA_W != DATA_W)
if (m_axis_rx.USER_W != USER_W)
$fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)");
localparam [7:0]
typedef enum logic [7:0] {
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
ETH_SFD = 8'hD5
} eth_pre_t;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PIPE = 2'd1,
STATE_PAYLOAD = 2'd2;
typedef enum logic [1:0] {
STATE_IDLE,
STATE_PIPE,
STATE_PAYLOAD
} state_t;
logic [1:0] state_reg = STATE_IDLE, state_next;
state_t state_reg = STATE_IDLE, state_next;
// datapath control signals
logic reset_crc;

24
src/eth/rtl/taxi_axis_gmii_tx.sv
View File

@@ -91,20 +91,22 @@ if (s_axis_tx.DATA_W != DATA_W)
if (s_axis_tx.USER_W != USER_W)
$fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)");
localparam [7:0]
typedef enum logic [7:0] {
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
ETH_SFD = 8'hD5
} eth_pre_t;
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_PREAMBLE = 3'd1,
STATE_PAYLOAD = 3'd2,
STATE_LAST = 3'd3,
STATE_PAD = 3'd4,
STATE_FCS = 3'd5,
STATE_IFG = 3'd6;
typedef enum logic [2:0] {
STATE_IDLE,
STATE_PREAMBLE,
STATE_PAYLOAD,
STATE_LAST,
STATE_PAD,
STATE_FCS,
STATE_IFG
} state_t;
logic [2:0] state_reg = STATE_IDLE, state_next;
state_t state_reg = STATE_IDLE, state_next;
// datapath control signals
logic reset_crc;

32
src/eth/rtl/taxi_axis_xgmii_rx_32.sv
View File

@@ -88,23 +88,35 @@ if (m_axis_rx.DATA_W != DATA_W)
if (m_axis_rx.USER_W != USER_W)
$fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)");
localparam [7:0]
typedef enum logic [7:0] {
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
ETH_SFD = 8'hD5
} eth_pre_t;
localparam [7:0]
typedef enum logic [7:0] {
XGMII_IDLE = 8'h07,
XGMII_LPI = 8'h06,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe;
XGMII_ERROR = 8'hfe,
XGMII_SEQ_OS = 8'h9c,
XGMII_RES_0 = 8'h1c,
XGMII_RES_1 = 8'h3c,
XGMII_RES_2 = 8'h7c,
XGMII_RES_3 = 8'hbc,
XGMII_RES_4 = 8'hdc,
XGMII_RES_5 = 8'hf7,
XGMII_SIG_OS = 8'h5c
} xgmii_ctrl_t;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PREAMBLE = 2'd1,
STATE_PAYLOAD = 2'd2,
STATE_LAST = 2'd3;
typedef enum logic [1:0] {
STATE_IDLE,
STATE_PREAMBLE,
STATE_PAYLOAD,
STATE_LAST
} state_t;
logic [1:0] state_reg = STATE_IDLE, state_next;
state_t state_reg = STATE_IDLE, state_next;
logic term_present_reg = 1'b0;
logic term_first_cycle_reg = 1'b0;

31
src/eth/rtl/taxi_axis_xgmii_rx_64.sv
View File

@@ -89,22 +89,34 @@ if (m_axis_rx.DATA_W != DATA_W)
if (m_axis_rx.USER_W != USER_W)
$fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)");
localparam [7:0]
typedef enum logic [7:0] {
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
ETH_SFD = 8'hD5
} eth_pre_t;
localparam [7:0]
typedef enum logic [7:0] {
XGMII_IDLE = 8'h07,
XGMII_LPI = 8'h06,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe;
XGMII_ERROR = 8'hfe,
XGMII_SEQ_OS = 8'h9c,
XGMII_RES_0 = 8'h1c,
XGMII_RES_1 = 8'h3c,
XGMII_RES_2 = 8'h7c,
XGMII_RES_3 = 8'hbc,
XGMII_RES_4 = 8'hdc,
XGMII_RES_5 = 8'hf7,
XGMII_SIG_OS = 8'h5c
} xgmii_ctrl_t;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PAYLOAD = 2'd1,
STATE_LAST = 2'd2;
typedef enum logic [1:0] {
STATE_IDLE,
STATE_PAYLOAD,
STATE_LAST
} state_t;
logic [1:0] state_reg = STATE_IDLE, state_next;
state_t state_reg = STATE_IDLE, state_next;
logic lanes_swapped_reg = 1'b0;
logic lanes_swapped_d1_reg = 1'b0;
@@ -120,7 +132,6 @@ logic framing_error_reg = 1'b0, framing_error_d0_reg = 1'b0;
logic [DATA_W-1:0] xgmii_rxd_d0_reg = '0;
logic [DATA_W-1:0] xgmii_rxd_d1_reg = '0;
logic xgmii_start_swap_reg = 1'b0;
logic xgmii_start_d0_reg = 1'b0;
logic xgmii_start_d1_reg = 1'b0;

42
src/eth/rtl/taxi_axis_xgmii_tx_32.sv
View File

@@ -98,28 +98,40 @@ if (s_axis_tx.DATA_W != DATA_W)
if (s_axis_tx.USER_W != USER_W)
$fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)");
localparam [7:0]
typedef enum logic [7:0] {
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
ETH_SFD = 8'hD5
} eth_pre_t;
localparam [7:0]
typedef enum logic [7:0] {
XGMII_IDLE = 8'h07,
XGMII_LPI = 8'h06,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe;
XGMII_ERROR = 8'hfe,
XGMII_SEQ_OS = 8'h9c,
XGMII_RES_0 = 8'h1c,
XGMII_RES_1 = 8'h3c,
XGMII_RES_2 = 8'h7c,
XGMII_RES_3 = 8'hbc,
XGMII_RES_4 = 8'hdc,
XGMII_RES_5 = 8'hf7,
XGMII_SIG_OS = 8'h5c
} xgmii_ctrl_t;
localparam [3:0]
STATE_IDLE = 4'd0,
STATE_PREAMBLE = 4'd1,
STATE_PAYLOAD = 4'd2,
STATE_PAD = 4'd3,
STATE_FCS_1 = 4'd4,
STATE_FCS_2 = 4'd5,
STATE_FCS_3 = 4'd6,
STATE_ERR = 4'd7,
STATE_IFG = 4'd8;
typedef enum logic [3:0] {
STATE_IDLE,
STATE_PREAMBLE,
STATE_PAYLOAD,
STATE_PAD,
STATE_FCS_1,
STATE_FCS_2,
STATE_FCS_3,
STATE_ERR,
STATE_IFG
} state_t;
logic [3:0] state_reg = STATE_IDLE, state_next;
state_t state_reg = STATE_IDLE, state_next;
// datapath control signals
logic reset_crc;

38
src/eth/rtl/taxi_axis_xgmii_tx_64.sv
View File

@@ -99,26 +99,38 @@ if (s_axis_tx.DATA_W != DATA_W)
if (s_axis_tx.USER_W != USER_W)
$fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)");
localparam [7:0]
typedef enum logic [7:0] {
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
ETH_SFD = 8'hD5
} eth_pre_t;
localparam [7:0]
typedef enum logic [7:0] {
XGMII_IDLE = 8'h07,
XGMII_LPI = 8'h06,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe;
XGMII_ERROR = 8'hfe,
XGMII_SEQ_OS = 8'h9c,
XGMII_RES_0 = 8'h1c,
XGMII_RES_1 = 8'h3c,
XGMII_RES_2 = 8'h7c,
XGMII_RES_3 = 8'hbc,
XGMII_RES_4 = 8'hdc,
XGMII_RES_5 = 8'hf7,
XGMII_SIG_OS = 8'h5c
} xgmii_ctrl_t;
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_PAYLOAD = 3'd1,
STATE_PAD = 3'd2,
STATE_FCS_1 = 3'd3,
STATE_FCS_2 = 3'd4,
STATE_ERR = 3'd5,
STATE_IFG = 3'd6;
typedef enum logic [2:0] {
STATE_IDLE,
STATE_PAYLOAD,
STATE_PAD,
STATE_FCS_1,
STATE_FCS_2,
STATE_ERR,
STATE_IFG
} state_t;
logic [2:0] state_reg = STATE_IDLE, state_next;
state_t state_reg = STATE_IDLE, state_next;
// datapath control signals
logic reset_crc;

25
src/eth/rtl/taxi_xgmii_baser_dec.sv
View File

@@ -63,7 +63,7 @@ if (CTRL_W * 8 != DATA_W)
if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
localparam [7:0]
typedef enum logic [7:0] {
XGMII_IDLE = 8'h07,
XGMII_LPI = 8'h06,
XGMII_START = 8'hfb,
@@ -76,9 +76,10 @@ localparam [7:0]
XGMII_RES_3 = 8'hbc,
XGMII_RES_4 = 8'hdc,
XGMII_RES_5 = 8'hf7,
XGMII_SIG_OS = 8'h5c;
XGMII_SIG_OS = 8'h5c
} xgmii_ctrl_t;
localparam [6:0]
typedef enum logic [6:0] {
CTRL_IDLE = 7'h00,
CTRL_LPI = 7'h06,
CTRL_ERROR = 7'h1e,
@@ -87,17 +88,20 @@ localparam [6:0]
CTRL_RES_2 = 7'h4b,
CTRL_RES_3 = 7'h55,
CTRL_RES_4 = 7'h66,
CTRL_RES_5 = 7'h78;
CTRL_RES_5 = 7'h78
} baser_ctrl_t;
localparam [3:0]
typedef enum logic [3:0] {
O_SEQ_OS = 4'h0,
O_SIG_OS = 4'hf;
O_SIG_OS = 4'hf
} baser_o_t;
localparam [1:0]
typedef enum logic [1:0] {
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
SYNC_CTRL = 2'b01
} baser_sync_t;
localparam [7:0]
typedef enum logic [7:0] {
BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
@@ -112,7 +116,8 @@ localparam [7:0]
BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff // D6 D5 D4 D3 D2 D1 D0 BT
} baser_block_type_t;
wire [DATA_W_INT-1:0] encoded_rx_data_int;
wire encoded_rx_data_valid_int;

25
src/eth/rtl/taxi_xgmii_baser_enc.sv
View File

@@ -67,7 +67,7 @@ if (CTRL_W * 8 != DATA_W)
if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
localparam [7:0]
typedef enum logic [7:0] {
XGMII_IDLE = 8'h07,
XGMII_LPI = 8'h06,
XGMII_START = 8'hfb,
@@ -80,9 +80,10 @@ localparam [7:0]
XGMII_RES_3 = 8'hbc,
XGMII_RES_4 = 8'hdc,
XGMII_RES_5 = 8'hf7,
XGMII_SIG_OS = 8'h5c;
XGMII_SIG_OS = 8'h5c
} xgmii_ctrl_t;
localparam [6:0]
typedef enum logic [6:0] {
CTRL_IDLE = 7'h00,
CTRL_LPI = 7'h06,
CTRL_ERROR = 7'h1e,
@@ -91,17 +92,20 @@ localparam [6:0]
CTRL_RES_2 = 7'h4b,
CTRL_RES_3 = 7'h55,
CTRL_RES_4 = 7'h66,
CTRL_RES_5 = 7'h78;
CTRL_RES_5 = 7'h78
} baser_ctrl_t;
localparam [3:0]
typedef enum logic [3:0] {
O_SEQ_OS = 4'h0,
O_SIG_OS = 4'hf;
O_SIG_OS = 4'hf
} baser_o_t;
localparam [1:0]
typedef enum logic [1:0] {
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
SYNC_CTRL = 2'b01
} baser_sync_t;
localparam [7:0]
typedef enum logic [7:0] {
BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
@@ -116,7 +120,8 @@ localparam [7:0]
BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff // D6 D5 D4 D3 D2 D1 D0 BT
} baser_block_type_t;
wire [DATA_W_INT-1:0] xgmii_txd_int;
wire [CTRL_W_INT-1:0] xgmii_txc_int;