diff --git a/src/eth/rtl/us/taxi_eth_mac_25g_us.f b/src/eth/rtl/us/taxi_eth_mac_25g_us.f index bfb7612..02eebd3 100644 --- a/src/eth/rtl/us/taxi_eth_mac_25g_us.f +++ b/src/eth/rtl/us/taxi_eth_mac_25g_us.f @@ -8,3 +8,4 @@ taxi_eth_phy_10g_7_gt.f ../taxi_eth_mac_phy_10g.f ../taxi_eth_mac_10g.f ../taxi_eth_phy_10g.f +../../lib/taxi/src/apb/rtl/taxi_apb_interconnect.sv diff --git a/src/eth/rtl/us/taxi_eth_mac_25g_us.sv b/src/eth/rtl/us/taxi_eth_mac_25g_us.sv index f14c011..5925336 100644 --- a/src/eth/rtl/us/taxi_eth_mac_25g_us.sv +++ b/src/eth/rtl/us/taxi_eth_mac_25g_us.sv @@ -80,6 +80,11 @@ module taxi_eth_mac_25g_us # input wire logic xcvr_ctrl_clk, input wire logic xcvr_ctrl_rst, + /* + * Transceiver control + */ + taxi_apb_if.slv s_apb_ctrl, + /* * Common */ @@ -279,6 +284,35 @@ reset_sync_inst ( .out(xcvr_ctrl_rst_sync) ); +// transceiver control +taxi_apb_if #( + .ADDR_W(16), + .DATA_W(16) +) +ch_apb_ctrl[CNT](); + +taxi_apb_interconnect #( + .M_CNT(CNT), + .ADDR_W(s_apb_ctrl.ADDR_W), + .M_REGIONS(1), + .M_BASE_ADDR('0), + .M_ADDR_W({CNT{{1{32'd16}}}}) +) +ctrl_intercon_inst ( + .clk(xcvr_ctrl_clk), + .rst(xcvr_ctrl_rst_sync), + + /* + * APB slave interface + */ + .s_apb(s_apb_ctrl), + + /* + * APB master interface + */ + .m_apb(ch_apb_ctrl) +); + // statistics localparam STAT_TX_CNT = STAT_TX_LEVEL == 0 ? 8 : (STAT_TX_LEVEL == 1 ? 16: 32); localparam STAT_RX_CNT = STAT_RX_LEVEL == 0 ? 8 : (STAT_RX_LEVEL == 1 ? 16: 32); @@ -408,6 +442,11 @@ for (genvar n = 0; n < CNT; n = n + 1) begin : ch .xcvr_ctrl_clk(xcvr_ctrl_clk), .xcvr_ctrl_rst(xcvr_ctrl_rst_sync), + /* + * Transceiver control + */ + .s_apb_ctrl(ch_apb_ctrl[n]), + /* * Common */ diff --git a/src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv b/src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv index 6670043..c20933a 100644 --- a/src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv +++ b/src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv @@ -79,6 +79,11 @@ module taxi_eth_mac_25g_us_ch # input wire logic xcvr_ctrl_clk, input wire logic xcvr_ctrl_rst, + /* + * Transceiver control + */ + taxi_apb_if.slv s_apb_ctrl, + /* * Common */ @@ -336,6 +341,11 @@ if (GT_7) begin : gt .xcvr_ctrl_clk(xcvr_ctrl_clk), .xcvr_ctrl_rst(xcvr_ctrl_rst), + /* + * Transceiver control + */ + .s_apb_ctrl(s_apb_ctrl), + /* * PLL out */ @@ -436,6 +446,11 @@ end else if (DATA_W == 64 && CFG_LOW_LATENCY) begin : gt .xcvr_ctrl_clk(xcvr_ctrl_clk), .xcvr_ctrl_rst(xcvr_ctrl_rst), + /* + * Transceiver control + */ + .s_apb_ctrl(s_apb_ctrl), + /* * Common */ @@ -545,6 +560,11 @@ end else if (DATA_W == 64 && !CFG_LOW_LATENCY) begin : gt .xcvr_ctrl_clk(xcvr_ctrl_clk), .xcvr_ctrl_rst(xcvr_ctrl_rst), + /* + * Transceiver control + */ + .s_apb_ctrl(s_apb_ctrl), + /* * Common */ @@ -654,6 +674,11 @@ end else if (DATA_W == 32 && CFG_LOW_LATENCY) begin : gt .xcvr_ctrl_clk(xcvr_ctrl_clk), .xcvr_ctrl_rst(xcvr_ctrl_rst), + /* + * Transceiver control + */ + .s_apb_ctrl(s_apb_ctrl), + /* * Common */ @@ -763,6 +788,11 @@ end else if (DATA_W == 32 && !CFG_LOW_LATENCY) begin : gt .xcvr_ctrl_clk(xcvr_ctrl_clk), .xcvr_ctrl_rst(xcvr_ctrl_rst), + /* + * Transceiver control + */ + .s_apb_ctrl(s_apb_ctrl), + /* * Common */ diff --git a/src/eth/rtl/us/taxi_eth_phy_10g_7_gt.f b/src/eth/rtl/us/taxi_eth_phy_10g_7_gt.f index aa68bb5..762291d 100644 --- a/src/eth/rtl/us/taxi_eth_phy_10g_7_gt.f +++ b/src/eth/rtl/us/taxi_eth_phy_10g_7_gt.f @@ -1,6 +1,8 @@ taxi_eth_phy_10g_7_gt.sv +taxi_eth_phy_25g_us_gt_apb.sv ../../lib/taxi/src/sync/rtl/taxi_sync_reset.sv ../../lib/taxi/src/sync/rtl/taxi_sync_signal.sv ../../lib/taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv ../../lib/taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv ../../lib/taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv +../../lib/taxi/src/apb/rtl/taxi_apb_if.sv diff --git a/src/eth/rtl/us/taxi_eth_phy_10g_7_gt.sv b/src/eth/rtl/us/taxi_eth_phy_10g_7_gt.sv index f40d1c1..99becd1 100644 --- a/src/eth/rtl/us/taxi_eth_phy_10g_7_gt.sv +++ b/src/eth/rtl/us/taxi_eth_phy_10g_7_gt.sv @@ -51,6 +51,11 @@ module taxi_eth_phy_10g_7_gt # input wire logic xcvr_ctrl_clk, input wire logic xcvr_ctrl_rst, + /* + * Transceiver control + */ + taxi_apb_if.slv s_apb_ctrl, + /* * PLL out */ @@ -111,10 +116,185 @@ if (DATA_W != 32) if (HDR_W != 2) $fatal(0, "Error: HDR_W must be 2"); +// status +wire qpll_lock; + +wire tx_reset_done; +wire tx_pma_reset_done; +wire tx_prgdiv_reset_done; + +wire rx_reset_done; +wire rx_pma_reset_done; +wire rx_prgdiv_reset_done; + +// control registers +wire [10:0] gt_drp_addr; +wire [15:0] gt_drp_di; +wire gt_drp_en; +wire gt_drp_we; +wire [15:0] gt_drp_do; +wire gt_drp_rdy; + +wire [10:0] com_drp_addr; +wire [15:0] com_drp_di; +wire com_drp_en; +wire com_drp_we; +wire [15:0] com_drp_do; +wire com_drp_rdy; + +wire ctrl_qpll_reset; +wire ctrl_qpll_pd; + +wire [2:0] ctrl_loopback; + +wire ctrl_tx_reset; +wire ctrl_tx_pma_reset; +wire ctrl_tx_pcs_reset; +wire ctrl_tx_pd; +wire ctrl_tx_qpll_sel; +wire ctrl_rx_reset; +wire ctrl_rx_pma_reset; +wire ctrl_rx_pcs_reset; +wire ctrl_rx_dfe_lpm_reset; +wire ctrl_eyescan_reset; +wire ctrl_rx_pd; +wire ctrl_rx_qpll_sel; + +wire ctrl_rxcdrhold; +wire ctrl_rxlpmen; + +wire [3:0] ctrl_txprbssel; +wire ctrl_txprbsforceerr; +wire ctrl_txpolarity; +wire ctrl_txelecidle; +wire ctrl_txinhibit; +wire [4:0] ctrl_txdiffctrl; +wire [6:0] ctrl_txmaincursor; +wire [4:0] ctrl_txpostcursor; +wire [4:0] ctrl_txprecursor; + +wire ctrl_rxpolarity; +wire ctrl_rxprbscntreset; +wire [3:0] ctrl_rxprbssel; + +wire ctrl_rxprbserr; + +wire [15:0] ctrl_dmonitorout; + +wire ctrl_phy_rx_reset_req_en; + +taxi_eth_phy_25g_us_gt_apb #( + .HAS_COMMON(HAS_COMMON), + + // PLL parameters + .QPLL0_PD(QPLL_PD), + + // GT parameters + .GT_TX_PD(GT_TX_PD), + .GT_TX_POLARITY(GT_TX_POLARITY), + .GT_TX_ELECIDLE(GT_TX_ELECIDLE), + .GT_TX_INHIBIT(GT_TX_INHIBIT), + .GT_TX_DIFFCTRL(GT_TX_DIFFCTRL), + .GT_TX_MAINCURSOR(GT_TX_MAINCURSOR), + .GT_TX_POSTCURSOR(GT_TX_POSTCURSOR), + .GT_TX_PRECURSOR(GT_TX_PRECURSOR), + .GT_RX_PD(GT_RX_PD), + .GT_RX_LPM_EN(GT_RX_LPM_EN), + .GT_RX_POLARITY(GT_RX_POLARITY) +) +ctrl_regs_inst ( + .clk(xcvr_ctrl_clk), + .rst(xcvr_ctrl_rst), + + /* + * Transceiver clocks + */ + .gt_txusrclk2(tx_clk), + .gt_rxusrclk2(rx_clk), + + /* + * Transceiver control + */ + .s_apb_ctrl(s_apb_ctrl), + + /* + * DRP (channel) + */ + .gt_drp_addr(gt_drp_addr), + .gt_drp_di(gt_drp_di), + .gt_drp_en(gt_drp_en), + .gt_drp_we(gt_drp_we), + .gt_drp_do(gt_drp_do), + .gt_drp_rdy(gt_drp_rdy), + + /* + * DRP (common) + */ + .com_drp_addr(com_drp_addr), + .com_drp_di(com_drp_di), + .com_drp_en(com_drp_en), + .com_drp_we(com_drp_we), + .com_drp_do(com_drp_do), + .com_drp_rdy(com_drp_rdy), + + /* + * Control and status signals + */ + .qpll0_reset(ctrl_qpll_reset), + .qpll0_pd(ctrl_qpll_pd), + .qpll0_lock(qpll_lock), + .qpll1_reset(), + .qpll1_pd(), + .qpll1_lock(1'b0), + + .gt_loopback(ctrl_loopback), + + .gt_tx_reset(ctrl_tx_reset), + .gt_tx_pma_reset(ctrl_tx_pma_reset), + .gt_tx_pcs_reset(ctrl_tx_pcs_reset), + .gt_tx_reset_done(tx_reset_done), + .gt_tx_pma_reset_done(tx_pma_reset_done), + .gt_tx_prgdiv_reset_done(tx_prgdiv_reset_done), + .gt_tx_pd(ctrl_tx_pd), + .gt_tx_qpll_sel(ctrl_tx_qpll_sel), + .gt_rx_reset(ctrl_rx_reset), + .gt_rx_pma_reset(ctrl_rx_pma_reset), + .gt_rx_pcs_reset(ctrl_rx_pcs_reset), + .gt_rx_dfe_lpm_reset(ctrl_rx_dfe_lpm_reset), + .gt_eyescan_reset(ctrl_eyescan_reset), + .gt_rx_reset_done(rx_reset_done), + .gt_rx_pma_reset_done(rx_pma_reset_done), + .gt_rx_prgdiv_reset_done(rx_prgdiv_reset_done), + .gt_rx_pd(ctrl_rx_pd), + .gt_rx_qpll_sel(ctrl_rx_qpll_sel), + + .gt_rxcdrhold(ctrl_rxcdrhold), + .gt_rxlpmen(ctrl_rxlpmen), + + .gt_txprbssel(ctrl_txprbssel), + .gt_txprbsforceerr(ctrl_txprbsforceerr), + .gt_txpolarity(ctrl_txpolarity), + .gt_txelecidle(ctrl_txelecidle), + .gt_txinhibit(ctrl_txinhibit), + .gt_txdiffctrl(ctrl_txdiffctrl), + .gt_txmaincursor(ctrl_txmaincursor), + .gt_txpostcursor(ctrl_txpostcursor), + .gt_txprecursor(ctrl_txprecursor), + + .gt_rxpolarity(ctrl_rxpolarity), + .gt_rxprbscntreset(ctrl_rxprbscntreset), + .gt_rxprbssel(ctrl_rxprbssel), + + .gt_rxprbserr(ctrl_rxprbserr), + + .gt_dmonitorout(ctrl_dmonitorout), + + .phy_rx_reset_req_en(ctrl_phy_rx_reset_req_en) +); + wire gt_qpll_pd; wire gt_qpll_reset; -wire qpll_lock; wire qpll_refclk_lost; if (HAS_COMMON) begin : common_ctrl @@ -137,8 +317,8 @@ if (HAS_COMMON) begin : common_ctrl /* * Control/status */ - .qpll_reset_in(1'b0), - .qpll_pd_in(QPLL_PD), + .qpll_reset_in(ctrl_qpll_reset), + .qpll_pd_in(ctrl_qpll_pd), .qpll_lock_out(qpll_lock) ); @@ -202,8 +382,6 @@ wire gt_tx_pcs_reset; wire gt_tx_pma_reset_done; wire gt_tx_userrdy; -wire tx_reset_done; - taxi_sync_reset #( .N(4) ) @@ -224,6 +402,7 @@ gt_tx_reset_inst ( /* * GT */ + .gt_txusrclk2(tx_clk), .gt_tx_pd_out(gt_tx_pd), .gt_tx_reset_out(gt_tx_reset), .gt_tx_reset_done_in(gt_tx_reset_done), @@ -241,13 +420,13 @@ gt_tx_reset_inst ( */ .qpll0_lock_in(qpll_lock), .qpll1_lock_in(1'b1), - .tx_reset_in(tx_rst_in), + .tx_reset_in(tx_rst_in || ctrl_tx_reset), .tx_reset_done_out(tx_reset_done), - .tx_pma_reset_in(1'b0), - .tx_pma_reset_done_out(), - .tx_prgdiv_reset_done_out(), - .tx_pcs_reset_in(1'b0), - .tx_pd_in(GT_TX_PD), + .tx_pma_reset_in(ctrl_tx_pma_reset), + .tx_pma_reset_done_out(tx_pma_reset_done), + .tx_prgdiv_reset_done_out(tx_prgdiv_reset_done), + .tx_pcs_reset_in(ctrl_tx_pcs_reset), + .tx_pd_in(ctrl_tx_pd), .tx_qpll_sel_in(1'b0) ); @@ -264,8 +443,6 @@ wire gt_rx_userrdy; wire gt_rx_cdr_lock; wire gt_rx_lpm_en; -wire rx_reset_done; - taxi_sync_reset #( .N(4) ) @@ -288,6 +465,7 @@ gt_rx_reset_inst ( /* * GT */ + .gt_rxusrclk2(rx_clk), .gt_rx_pd_out(gt_rx_pd), .gt_rx_reset_out(gt_rx_reset), .gt_rx_reset_done_in(gt_rx_reset_done), @@ -309,17 +487,17 @@ gt_rx_reset_inst ( */ .qpll0_lock_in(qpll_lock), .qpll1_lock_in(1'b1), - .rx_reset_in(rx_rst_in), + .rx_reset_in(rx_rst_in || ctrl_rx_reset), .rx_reset_done_out(rx_reset_done), - .rx_pma_reset_in(1'b0), - .rx_pma_reset_done_out(), - .rx_prgdiv_reset_done_out(), - .rx_pcs_reset_in(1'b0), - .rx_dfe_lpm_reset_in(1'b0), - .eyescan_reset_in(1'b0), - .rx_pd_in(GT_RX_PD), + .rx_pma_reset_in(ctrl_rx_pma_reset), + .rx_pma_reset_done_out(rx_pma_reset_done), + .rx_prgdiv_reset_done_out(rx_prgdiv_reset_done), + .rx_pcs_reset_in(ctrl_rx_pcs_reset), + .rx_dfe_lpm_reset_in(ctrl_rx_dfe_lpm_reset), + .eyescan_reset_in(ctrl_eyescan_reset), + .rx_pd_in(ctrl_rx_pd), .rx_qpll_sel_in(1'b0), - .rx_lpm_en_in(GT_RX_LPM_EN) + .rx_lpm_en_in(ctrl_rxlpmen) ); wire [6:0] gt_txsequence; @@ -399,6 +577,12 @@ if (SIM) begin : xcvr assign gt_rx_pma_reset_done = gt_rx_reset_done; assign gt_rx_cdr_lock = gt_rx_reset_done; + assign com_drp_do = 16'hCC00; + assign com_drp_rdy = 1'b1; + + assign gt_drp_do = 16'hDA00; + assign gt_drp_rdy = 1'b1; + end else if (GT_TYPE == "GTH") begin : xcvr // 7-series GTH @@ -462,13 +646,13 @@ end else if (GT_TYPE == "GTH") begin : xcvr gt_common_inst ( //----------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- - .DRPADDR (8'd0), - .DRPCLK (1'b0), - .DRPDI (16'd0), - .DRPDO (), - .DRPEN (1'b0), - .DRPRDY (), - .DRPWE (1'b0), + .DRPADDR (com_drp_addr), + .DRPCLK (xcvr_ctrl_clk), + .DRPDI (com_drp_di), + .DRPDO (com_drp_do), + .DRPEN (com_drp_en), + .DRPRDY (com_drp_rdy), + .DRPWE (com_drp_we), //-------------------- Common Block - Ref Clock Ports --------------------- .GTGREFCLK (1'b0), .GTNORTHREFCLK0 (1'b0), @@ -512,6 +696,9 @@ end else if (GT_TYPE == "GTH") begin : xcvr assign xcvr_qpllclk_out = 1'b0; assign xcvr_qpllrefclk_out = 1'b0; + assign com_drp_do = '0; + assign com_drp_rdy = 1'b1; + end GTHE2_CHANNEL # @@ -848,13 +1035,13 @@ end else if (GT_TYPE == "GTH") begin : xcvr .GTSOUTHREFCLK0 (1'b0), .GTSOUTHREFCLK1 (1'b0), //-------------------------- Channel - DRP Ports -------------------------- - .DRPADDR ('0), - .DRPCLK ('0), - .DRPDI ('0), - .DRPDO (), - .DRPEN ('0), - .DRPRDY (), - .DRPWE ('0), + .DRPADDR (gt_drp_addr), + .DRPCLK (xcvr_ctrl_clk), + .DRPDI (gt_drp_di), + .DRPDO (gt_drp_do), + .DRPEN (gt_drp_en), + .DRPRDY (gt_drp_rdy), + .DRPWE (gt_drp_we), //----------------------------- Clocking Ports ----------------------------- .GTREFCLKMONITOR (), .QPLLCLK (xcvr_qpllclk_in), @@ -1052,7 +1239,7 @@ end else if (GT_TYPE == "GTH") begin : xcvr .RXELECIDLE (), .RXELECIDLEMODE (2'b11), //--------------- Receive Ports - RX Polarity Control Ports ---------------- - .RXPOLARITY (GT_RX_POLARITY), + .RXPOLARITY (ctrl_rxpolarity), //----------------- Receive Ports - RX8B/10B Decoder Ports ----------------- .RXCHARISCOMMA (), .RXCHARISK (), @@ -1087,7 +1274,7 @@ end else if (GT_TYPE == "GTH") begin : xcvr .TXUSRCLK (gt_txusrclk), .TXUSRCLK2 (gt_txusrclk2), //------------------- Transmit Ports - PCI Express Ports ------------------- - .TXELECIDLE (GT_TX_ELECIDLE), + .TXELECIDLE (ctrl_txelecidle), .TXMARGIN (3'd0), .TXRATE (3'd0), .TXSWING (1'b0), @@ -1119,14 +1306,14 @@ end else if (GT_TYPE == "GTH") begin : xcvr //------------- Transmit Ports - TX Configurable Driver Ports -------------- .TXBUFDIFFCTRL (3'b100), .TXDEEMPH (1'b0), - .TXDIFFCTRL (GT_TX_DIFFCTRL), + .TXDIFFCTRL (ctrl_txdiffctrl[4:0]), .TXDIFFPD (1'b0), - .TXINHIBIT (GT_TX_INHIBIT), - .TXMAINCURSOR (GT_TX_MAINCURSOR), + .TXINHIBIT (ctrl_txinhibit), + .TXMAINCURSOR (ctrl_txmaincursor), .TXPISOPD (1'b0), - .TXPOSTCURSOR (GT_TX_POSTCURSOR), + .TXPOSTCURSOR (ctrl_txpostcursor), .TXPOSTCURSORINV (1'b0), - .TXPRECURSOR (GT_TX_PRECURSOR), + .TXPRECURSOR (ctrl_txprecursor), .TXPRECURSORINV (1'b0), .TXQPIBIASEN (1'b0), .TXQPISTRONGPDOWN (1'b0), @@ -1162,7 +1349,7 @@ end else if (GT_TYPE == "GTH") begin : xcvr .TXCOMWAKE (1'b0), .TXPDELECIDLEMODE (1'b1), //--------------- Transmit Ports - TX Polarity Control Ports --------------- - .TXPOLARITY (GT_TX_POLARITY), + .TXPOLARITY (ctrl_txpolarity), //------------- Transmit Ports - TX Receiver Detection Ports -------------- .TXDETECTRX (1'b0), //---------------- Transmit Ports - TX8b/10b Encoder Ports ----------------- @@ -1231,13 +1418,13 @@ end else if (GT_TYPE == "GTX") begin : xcvr gt_common_inst ( //----------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- - .DRPADDR (8'd0), - .DRPCLK (1'b0), - .DRPDI (16'd0), - .DRPDO (), - .DRPEN (1'b0), - .DRPRDY (), - .DRPWE (1'b0), + .DRPADDR (com_drp_addr), + .DRPCLK (xcvr_ctrl_clk), + .DRPDI (com_drp_di), + .DRPDO (com_drp_do), + .DRPEN (com_drp_en), + .DRPRDY (com_drp_rdy), + .DRPWE (com_drp_we), //-------------------- Common Block - Ref Clock Ports --------------------- .GTGREFCLK (1'b0), .GTNORTHREFCLK0 (1'b0), @@ -1279,6 +1466,9 @@ end else if (GT_TYPE == "GTX") begin : xcvr assign xcvr_qpllclk_out = 1'b0; assign xcvr_qpllrefclk_out = 1'b0; + assign com_drp_do = '0; + assign com_drp_rdy = 1'b1; + end GTXE2_CHANNEL # @@ -1554,13 +1744,13 @@ end else if (GT_TYPE == "GTX") begin : xcvr .GTSOUTHREFCLK0 (1'b0), .GTSOUTHREFCLK1 (1'b0), //-------------------------- Channel - DRP Ports -------------------------- - .DRPADDR ('0), - .DRPCLK ('0), - .DRPDI ('0), - .DRPDO (), - .DRPEN ('0), - .DRPRDY (), - .DRPWE ('0), + .DRPADDR (gt_drp_addr), + .DRPCLK (xcvr_ctrl_clk), + .DRPDI (gt_drp_di), + .DRPDO (gt_drp_do), + .DRPEN (gt_drp_en), + .DRPRDY (gt_drp_rdy), + .DRPWE (gt_drp_we), //----------------------------- Clocking Ports ----------------------------- .GTREFCLKMONITOR (), .QPLLCLK (xcvr_qpllclk_in), @@ -1715,7 +1905,7 @@ end else if (GT_TYPE == "GTX") begin : xcvr .RXELECIDLE (), .RXELECIDLEMODE (2'b11), //--------------- Receive Ports - RX Polarity Control Ports ---------------- - .RXPOLARITY (GT_RX_POLARITY), + .RXPOLARITY (ctrl_rxpolarity), //-------------------- Receive Ports - RX gearbox ports -------------------- .RXSLIDE (1'b0), //----------------- Receive Ports - RX8B/10B Decoder Ports ----------------- @@ -1730,9 +1920,9 @@ end else if (GT_TYPE == "GTX") begin : xcvr //------------------------- TX Buffer Bypass Ports ------------------------- .TXPHDLYTSTCLK (1'b0), //---------------------- TX Configurable Driver Ports ---------------------- - .TXPOSTCURSOR (GT_TX_POSTCURSOR), + .TXPOSTCURSOR (ctrl_txpostcursor), .TXPOSTCURSORINV (1'b0), - .TXPRECURSOR (GT_TX_PRECURSOR), + .TXPRECURSOR (ctrl_txprecursor), .TXPRECURSORINV (1'b0), .TXQPIBIASEN (1'b0), .TXQPISTRONGPDOWN (1'b0), @@ -1752,7 +1942,7 @@ end else if (GT_TYPE == "GTX") begin : xcvr .TXUSRCLK (gt_txusrclk), .TXUSRCLK2 (gt_txusrclk2), //------------------- Transmit Ports - PCI Express Ports ------------------- - .TXELECIDLE (GT_TX_ELECIDLE), + .TXELECIDLE (ctrl_txelecidle), .TXMARGIN (3'd0), .TXRATE (3'd0), .TXSWING (1'b0), @@ -1779,10 +1969,10 @@ end else if (GT_TYPE == "GTX") begin : xcvr //------------- Transmit Ports - TX Configurable Driver Ports -------------- .TXBUFDIFFCTRL (3'b100), .TXDEEMPH (1'b0), - .TXDIFFCTRL (GT_TX_DIFFCTRL), + .TXDIFFCTRL (ctrl_txdiffctrl[4:0]), .TXDIFFPD (1'b0), - .TXINHIBIT (GT_TX_INHIBIT), - .TXMAINCURSOR (GT_TX_MAINCURSOR), + .TXINHIBIT (ctrl_txinhibit), + .TXMAINCURSOR (ctrl_txmaincursor), .TXPISOPD (1'b0), //---------------- Transmit Ports - TX Data Path interface ----------------- .TXDATA (gt_txdata), @@ -1812,7 +2002,7 @@ end else if (GT_TYPE == "GTX") begin : xcvr .TXCOMWAKE (1'b0), .TXPDELECIDLEMODE (1'b0), //--------------- Transmit Ports - TX Polarity Control Ports --------------- - .TXPOLARITY (GT_TX_POLARITY), + .TXPOLARITY (ctrl_txpolarity), //------------- Transmit Ports - TX Receiver Detection Ports -------------- .TXDETECTRX (1'b0), //---------------- Transmit Ports - TX8b/10b Encoder Ports ----------------- diff --git a/src/eth/rtl/us/taxi_eth_phy_10g_us_gt.f b/src/eth/rtl/us/taxi_eth_phy_10g_us_gt.f index 6be9982..6d13dba 100644 --- a/src/eth/rtl/us/taxi_eth_phy_10g_us_gt.f +++ b/src/eth/rtl/us/taxi_eth_phy_10g_us_gt.f @@ -1,6 +1,8 @@ taxi_eth_phy_10g_us_gt.sv +taxi_eth_phy_25g_us_gt_apb.sv ../../lib/taxi/src/sync/rtl/taxi_sync_reset.sv ../../lib/taxi/src/sync/rtl/taxi_sync_signal.sv ../../lib/taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv ../../lib/taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv ../../lib/taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv +../../lib/taxi/src/apb/rtl/taxi_apb_if.sv diff --git a/src/eth/rtl/us/taxi_eth_phy_10g_us_gt.sv b/src/eth/rtl/us/taxi_eth_phy_10g_us_gt.sv index 67aa5e6..2597929 100644 --- a/src/eth/rtl/us/taxi_eth_phy_10g_us_gt.sv +++ b/src/eth/rtl/us/taxi_eth_phy_10g_us_gt.sv @@ -55,6 +55,11 @@ module taxi_eth_phy_10g_us_gt # input wire logic xcvr_ctrl_clk, input wire logic xcvr_ctrl_rst, + /* + * Transceiver control + */ + taxi_apb_if.slv s_apb_ctrl, + /* * Common */ @@ -133,14 +138,193 @@ if (DATA_W != 32) if (HDR_W != 2) $fatal(0, "Error: HDR_W must be 2"); +// status +wire qpll0_lock; +wire qpll1_lock; + +wire tx_reset_done; +wire tx_pma_reset_done; +wire tx_prgdiv_reset_done; + +wire rx_reset_done; +wire rx_pma_reset_done; +wire rx_prgdiv_reset_done; + +// control registers +wire [10:0] gt_drp_addr; +wire [15:0] gt_drp_di; +wire gt_drp_en; +wire gt_drp_we; +wire [15:0] gt_drp_do; +wire gt_drp_rdy; + +wire [10:0] com_drp_addr; +wire [15:0] com_drp_di; +wire com_drp_en; +wire com_drp_we; +wire [15:0] com_drp_do; +wire com_drp_rdy; + +wire ctrl_qpll0_reset; +wire ctrl_qpll0_pd; +wire ctrl_qpll1_reset; +wire ctrl_qpll1_pd; + +wire [2:0] ctrl_loopback; + +wire ctrl_tx_reset; +wire ctrl_tx_pma_reset; +wire ctrl_tx_pcs_reset; +wire ctrl_tx_pd; +wire ctrl_tx_qpll_sel; +wire ctrl_rx_reset; +wire ctrl_rx_pma_reset; +wire ctrl_rx_pcs_reset; +wire ctrl_rx_dfe_lpm_reset; +wire ctrl_eyescan_reset; +wire ctrl_rx_pd; +wire ctrl_rx_qpll_sel; + +wire ctrl_rxcdrhold; +wire ctrl_rxlpmen; + +wire [3:0] ctrl_txprbssel; +wire ctrl_txprbsforceerr; +wire ctrl_txpolarity; +wire ctrl_txelecidle; +wire ctrl_txinhibit; +wire [4:0] ctrl_txdiffctrl; +wire [6:0] ctrl_txmaincursor; +wire [4:0] ctrl_txpostcursor; +wire [4:0] ctrl_txprecursor; + +wire ctrl_rxpolarity; +wire ctrl_rxprbscntreset; +wire [3:0] ctrl_rxprbssel; + +wire ctrl_rxprbserr; + +wire [15:0] ctrl_dmonitorout; + +wire ctrl_phy_rx_reset_req_en; + +taxi_eth_phy_25g_us_gt_apb #( + .HAS_COMMON(HAS_COMMON), + + // PLL parameters + .QPLL0_PD(QPLL0_PD), + .QPLL1_PD(QPLL1_PD), + + // GT parameters + .GT_TX_PD(GT_TX_PD), + .GT_TX_QPLL_SEL(GT_TX_QPLL_SEL), + .GT_TX_POLARITY(GT_TX_POLARITY), + .GT_TX_ELECIDLE(GT_TX_ELECIDLE), + .GT_TX_INHIBIT(GT_TX_INHIBIT), + .GT_TX_DIFFCTRL(GT_TX_DIFFCTRL), + .GT_TX_MAINCURSOR(GT_TX_MAINCURSOR), + .GT_TX_POSTCURSOR(GT_TX_POSTCURSOR), + .GT_TX_PRECURSOR(GT_TX_PRECURSOR), + .GT_RX_PD(GT_RX_PD), + .GT_RX_QPLL_SEL(GT_RX_QPLL_SEL), + .GT_RX_LPM_EN(GT_RX_LPM_EN), + .GT_RX_POLARITY(GT_RX_POLARITY) +) +ctrl_regs_inst ( + .clk(xcvr_ctrl_clk), + .rst(xcvr_ctrl_rst), + + /* + * Transceiver clocks + */ + .gt_txusrclk2(tx_clk), + .gt_rxusrclk2(rx_clk), + + /* + * Transceiver control + */ + .s_apb_ctrl(s_apb_ctrl), + + /* + * DRP (channel) + */ + .gt_drp_addr(gt_drp_addr), + .gt_drp_di(gt_drp_di), + .gt_drp_en(gt_drp_en), + .gt_drp_we(gt_drp_we), + .gt_drp_do(gt_drp_do), + .gt_drp_rdy(gt_drp_rdy), + + /* + * DRP (common) + */ + .com_drp_addr(com_drp_addr), + .com_drp_di(com_drp_di), + .com_drp_en(com_drp_en), + .com_drp_we(com_drp_we), + .com_drp_do(com_drp_do), + .com_drp_rdy(com_drp_rdy), + + /* + * Control and status signals + */ + .qpll0_reset(ctrl_qpll0_reset), + .qpll0_pd(ctrl_qpll0_pd), + .qpll0_lock(qpll0_lock), + .qpll1_reset(ctrl_qpll1_reset), + .qpll1_pd(ctrl_qpll1_pd), + .qpll1_lock(qpll1_lock), + + .gt_loopback(ctrl_loopback), + + .gt_tx_reset(ctrl_tx_reset), + .gt_tx_pma_reset(ctrl_tx_pma_reset), + .gt_tx_pcs_reset(ctrl_tx_pcs_reset), + .gt_tx_reset_done(tx_reset_done), + .gt_tx_pma_reset_done(tx_pma_reset_done), + .gt_tx_prgdiv_reset_done(tx_prgdiv_reset_done), + .gt_tx_pd(ctrl_tx_pd), + .gt_tx_qpll_sel(ctrl_tx_qpll_sel), + .gt_rx_reset(ctrl_rx_reset), + .gt_rx_pma_reset(ctrl_rx_pma_reset), + .gt_rx_pcs_reset(ctrl_rx_pcs_reset), + .gt_rx_dfe_lpm_reset(ctrl_rx_dfe_lpm_reset), + .gt_eyescan_reset(ctrl_eyescan_reset), + .gt_rx_reset_done(rx_reset_done), + .gt_rx_pma_reset_done(rx_pma_reset_done), + .gt_rx_prgdiv_reset_done(rx_prgdiv_reset_done), + .gt_rx_pd(ctrl_rx_pd), + .gt_rx_qpll_sel(ctrl_rx_qpll_sel), + + .gt_rxcdrhold(ctrl_rxcdrhold), + .gt_rxlpmen(ctrl_rxlpmen), + + .gt_txprbssel(ctrl_txprbssel), + .gt_txprbsforceerr(ctrl_txprbsforceerr), + .gt_txpolarity(ctrl_txpolarity), + .gt_txelecidle(ctrl_txelecidle), + .gt_txinhibit(ctrl_txinhibit), + .gt_txdiffctrl(ctrl_txdiffctrl), + .gt_txmaincursor(ctrl_txmaincursor), + .gt_txpostcursor(ctrl_txpostcursor), + .gt_txprecursor(ctrl_txprecursor), + + .gt_rxpolarity(ctrl_rxpolarity), + .gt_rxprbscntreset(ctrl_rxprbscntreset), + .gt_rxprbssel(ctrl_rxprbssel), + + .gt_rxprbserr(ctrl_rxprbserr), + + .gt_dmonitorout(ctrl_dmonitorout), + + .phy_rx_reset_req_en(ctrl_phy_rx_reset_req_en) +); + wire gt_qpll0_pd; wire gt_qpll0_reset; wire gt_qpll1_pd; wire gt_qpll1_reset; -wire qpll0_lock; -wire qpll1_lock; - if (HAS_COMMON) begin : common_ctrl taxi_gt_qpll_reset #( @@ -161,8 +345,8 @@ if (HAS_COMMON) begin : common_ctrl /* * Control/status */ - .qpll_reset_in(1'b0), - .qpll_pd_in(QPLL0_PD), + .qpll_reset_in(ctrl_qpll0_reset), + .qpll_pd_in(ctrl_qpll0_pd), .qpll_lock_out(qpll0_lock) ); @@ -184,8 +368,8 @@ if (HAS_COMMON) begin : common_ctrl /* * Control/status */ - .qpll_reset_in(1'b0), - .qpll_pd_in(QPLL1_PD), + .qpll_reset_in(ctrl_qpll1_reset), + .qpll_pd_in(ctrl_qpll1_pd), .qpll_lock_out(qpll1_lock) ); @@ -220,8 +404,6 @@ wire gt_tx_prgdiv_reset_done; wire gt_tx_qpll_sel; wire gt_tx_userrdy; -wire tx_reset_done; - taxi_sync_reset #( .N(4) ) @@ -243,6 +425,7 @@ gt_tx_reset_inst ( /* * GT */ + .gt_txusrclk2(tx_clk), .gt_tx_pd_out(gt_tx_pd), .gt_tx_reset_out(gt_tx_reset), .gt_tx_reset_done_in(gt_tx_reset_done), @@ -260,14 +443,14 @@ gt_tx_reset_inst ( */ .qpll0_lock_in(qpll0_lock), .qpll1_lock_in(qpll1_lock), - .tx_reset_in(tx_rst_in), + .tx_reset_in(tx_rst_in || ctrl_tx_reset), .tx_reset_done_out(tx_reset_done), - .tx_pma_reset_in(1'b0), - .tx_pma_reset_done_out(), - .tx_prgdiv_reset_done_out(), - .tx_pcs_reset_in(1'b0), - .tx_pd_in(GT_TX_PD), - .tx_qpll_sel_in(GT_TX_QPLL_SEL) + .tx_pma_reset_in(ctrl_tx_pma_reset), + .tx_pma_reset_done_out(tx_pma_reset_done), + .tx_prgdiv_reset_done_out(tx_prgdiv_reset_done), + .tx_pcs_reset_in(ctrl_tx_pcs_reset), + .tx_pd_in(ctrl_tx_pd), + .tx_qpll_sel_in(ctrl_tx_qpll_sel) ); wire gt_rx_pd; @@ -286,8 +469,6 @@ wire gt_rx_userrdy; wire gt_rx_cdr_lock; wire gt_rx_lpm_en; -wire rx_reset_done; - taxi_sync_reset #( .N(4) ) @@ -311,6 +492,7 @@ gt_rx_reset_inst ( /* * GT */ + .gt_rxusrclk2(rx_clk), .gt_rx_pd_out(gt_rx_pd), .gt_rx_reset_out(gt_rx_reset), .gt_rx_reset_done_in(gt_rx_reset_done), @@ -332,17 +514,17 @@ gt_rx_reset_inst ( */ .qpll0_lock_in(qpll0_lock), .qpll1_lock_in(qpll1_lock), - .rx_reset_in(rx_rst_in), + .rx_reset_in(rx_rst_in || ctrl_rx_reset), .rx_reset_done_out(rx_reset_done), - .rx_pma_reset_in(1'b0), - .rx_pma_reset_done_out(), - .rx_prgdiv_reset_done_out(), - .rx_pcs_reset_in(1'b0), - .rx_dfe_lpm_reset_in(1'b0), - .eyescan_reset_in(1'b0), - .rx_pd_in(GT_RX_PD), - .rx_qpll_sel_in(GT_RX_QPLL_SEL), - .rx_lpm_en_in(GT_RX_LPM_EN) + .rx_pma_reset_in(ctrl_rx_pma_reset), + .rx_pma_reset_done_out(rx_pma_reset_done), + .rx_prgdiv_reset_done_out(rx_prgdiv_reset_done), + .rx_pcs_reset_in(ctrl_rx_pcs_reset), + .rx_dfe_lpm_reset_in(ctrl_rx_dfe_lpm_reset), + .eyescan_reset_in(ctrl_eyescan_reset), + .rx_pd_in(ctrl_rx_pd), + .rx_qpll_sel_in(ctrl_rx_qpll_sel), + .rx_lpm_en_in(ctrl_rxlpmen) ); wire [6:0] gt_txsequence; @@ -394,6 +576,12 @@ if (SIM) begin : xcvr assign gt_rx_prgdiv_reset_done = gt_rx_reset_done; assign gt_rx_cdr_lock = gt_rx_reset_done; + assign com_drp_do = 16'hCC00; + assign com_drp_rdy = 1'b1; + + assign gt_drp_do = 16'hDA00; + assign gt_drp_rdy = 1'b1; + end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr // UltraScale+ GTY (with common) @@ -402,6 +590,23 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -446,13 +651,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -485,7 +690,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -498,11 +703,28 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr // UltraScale+ GTH (with common) - taxi_eth_phy_10g_us_gth_full - taxi_eth_phy_10g_us_gth_full_inst ( + taxi_eth_phy_10g_us_gth_ll_full + taxi_eth_phy_10g_us_gth_ll_full_inst ( // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -547,13 +769,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -586,7 +808,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -604,6 +826,23 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -648,13 +887,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -687,7 +926,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -705,6 +944,23 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -749,13 +1005,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -788,7 +1044,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -806,6 +1062,15 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .qpll0clk_in(xcvr_qpll0clk_in), .qpll0refclk_in(xcvr_qpll0refclk_in), @@ -838,13 +1103,13 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -877,7 +1142,7 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -895,6 +1160,9 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr assign xcvr_qpll1clk_out = 1'b0; assign xcvr_qpll1refclk_out = 1'b0; + assign com_drp_do = '0; + assign com_drp_rdy = 1'b1; + end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr // UltraScale/UltraScale+ GTH (channel only) @@ -903,6 +1171,15 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .qpll0clk_in(xcvr_qpll0clk_in), .qpll0refclk_in(xcvr_qpll0refclk_in), @@ -935,13 +1212,13 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -974,7 +1251,7 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -992,6 +1269,9 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr assign xcvr_qpll1clk_out = 1'b0; assign xcvr_qpll1refclk_out = 1'b0; + assign com_drp_do = '0; + assign com_drp_rdy = 1'b1; + end else begin $fatal(0, "Error: invalid configuration (%m)"); diff --git a/src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.f b/src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.f index e0687e9..25f4536 100644 --- a/src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.f +++ b/src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.f @@ -1,6 +1,8 @@ taxi_eth_phy_10g_us_gt_ll.sv +taxi_eth_phy_25g_us_gt_apb.sv ../../lib/taxi/src/sync/rtl/taxi_sync_reset.sv ../../lib/taxi/src/sync/rtl/taxi_sync_signal.sv ../../lib/taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv ../../lib/taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv ../../lib/taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv +../../lib/taxi/src/apb/rtl/taxi_apb_if.sv diff --git a/src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.sv b/src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.sv index 0c757b1..d3c95c3 100644 --- a/src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.sv +++ b/src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.sv @@ -55,6 +55,11 @@ module taxi_eth_phy_10g_us_gt_ll # input wire logic xcvr_ctrl_clk, input wire logic xcvr_ctrl_rst, + /* + * Transceiver control + */ + taxi_apb_if.slv s_apb_ctrl, + /* * Common */ @@ -133,14 +138,193 @@ if (DATA_W != 32) if (HDR_W != 2) $fatal(0, "Error: HDR_W must be 2"); +// status +wire qpll0_lock; +wire qpll1_lock; + +wire tx_reset_done; +wire tx_pma_reset_done; +wire tx_prgdiv_reset_done; + +wire rx_reset_done; +wire rx_pma_reset_done; +wire rx_prgdiv_reset_done; + +// control registers +wire [10:0] gt_drp_addr; +wire [15:0] gt_drp_di; +wire gt_drp_en; +wire gt_drp_we; +wire [15:0] gt_drp_do; +wire gt_drp_rdy; + +wire [10:0] com_drp_addr; +wire [15:0] com_drp_di; +wire com_drp_en; +wire com_drp_we; +wire [15:0] com_drp_do; +wire com_drp_rdy; + +wire ctrl_qpll0_reset; +wire ctrl_qpll0_pd; +wire ctrl_qpll1_reset; +wire ctrl_qpll1_pd; + +wire [2:0] ctrl_loopback; + +wire ctrl_tx_reset; +wire ctrl_tx_pma_reset; +wire ctrl_tx_pcs_reset; +wire ctrl_tx_pd; +wire ctrl_tx_qpll_sel; +wire ctrl_rx_reset; +wire ctrl_rx_pma_reset; +wire ctrl_rx_pcs_reset; +wire ctrl_rx_dfe_lpm_reset; +wire ctrl_eyescan_reset; +wire ctrl_rx_pd; +wire ctrl_rx_qpll_sel; + +wire ctrl_rxcdrhold; +wire ctrl_rxlpmen; + +wire [3:0] ctrl_txprbssel; +wire ctrl_txprbsforceerr; +wire ctrl_txpolarity; +wire ctrl_txelecidle; +wire ctrl_txinhibit; +wire [4:0] ctrl_txdiffctrl; +wire [6:0] ctrl_txmaincursor; +wire [4:0] ctrl_txpostcursor; +wire [4:0] ctrl_txprecursor; + +wire ctrl_rxpolarity; +wire ctrl_rxprbscntreset; +wire [3:0] ctrl_rxprbssel; + +wire ctrl_rxprbserr; + +wire [15:0] ctrl_dmonitorout; + +wire ctrl_phy_rx_reset_req_en; + +taxi_eth_phy_25g_us_gt_apb #( + .HAS_COMMON(HAS_COMMON), + + // PLL parameters + .QPLL0_PD(QPLL0_PD), + .QPLL1_PD(QPLL1_PD), + + // GT parameters + .GT_TX_PD(GT_TX_PD), + .GT_TX_QPLL_SEL(GT_TX_QPLL_SEL), + .GT_TX_POLARITY(GT_TX_POLARITY), + .GT_TX_ELECIDLE(GT_TX_ELECIDLE), + .GT_TX_INHIBIT(GT_TX_INHIBIT), + .GT_TX_DIFFCTRL(GT_TX_DIFFCTRL), + .GT_TX_MAINCURSOR(GT_TX_MAINCURSOR), + .GT_TX_POSTCURSOR(GT_TX_POSTCURSOR), + .GT_TX_PRECURSOR(GT_TX_PRECURSOR), + .GT_RX_PD(GT_RX_PD), + .GT_RX_QPLL_SEL(GT_RX_QPLL_SEL), + .GT_RX_LPM_EN(GT_RX_LPM_EN), + .GT_RX_POLARITY(GT_RX_POLARITY) +) +ctrl_regs_inst ( + .clk(xcvr_ctrl_clk), + .rst(xcvr_ctrl_rst), + + /* + * Transceiver clocks + */ + .gt_txusrclk2(tx_clk), + .gt_rxusrclk2(rx_clk), + + /* + * Transceiver control + */ + .s_apb_ctrl(s_apb_ctrl), + + /* + * DRP (channel) + */ + .gt_drp_addr(gt_drp_addr), + .gt_drp_di(gt_drp_di), + .gt_drp_en(gt_drp_en), + .gt_drp_we(gt_drp_we), + .gt_drp_do(gt_drp_do), + .gt_drp_rdy(gt_drp_rdy), + + /* + * DRP (common) + */ + .com_drp_addr(com_drp_addr), + .com_drp_di(com_drp_di), + .com_drp_en(com_drp_en), + .com_drp_we(com_drp_we), + .com_drp_do(com_drp_do), + .com_drp_rdy(com_drp_rdy), + + /* + * Control and status signals + */ + .qpll0_reset(ctrl_qpll0_reset), + .qpll0_pd(ctrl_qpll0_pd), + .qpll0_lock(qpll0_lock), + .qpll1_reset(ctrl_qpll1_reset), + .qpll1_pd(ctrl_qpll1_pd), + .qpll1_lock(qpll1_lock), + + .gt_loopback(ctrl_loopback), + + .gt_tx_reset(ctrl_tx_reset), + .gt_tx_pma_reset(ctrl_tx_pma_reset), + .gt_tx_pcs_reset(ctrl_tx_pcs_reset), + .gt_tx_reset_done(tx_reset_done), + .gt_tx_pma_reset_done(tx_pma_reset_done), + .gt_tx_prgdiv_reset_done(tx_prgdiv_reset_done), + .gt_tx_pd(ctrl_tx_pd), + .gt_tx_qpll_sel(ctrl_tx_qpll_sel), + .gt_rx_reset(ctrl_rx_reset), + .gt_rx_pma_reset(ctrl_rx_pma_reset), + .gt_rx_pcs_reset(ctrl_rx_pcs_reset), + .gt_rx_dfe_lpm_reset(ctrl_rx_dfe_lpm_reset), + .gt_eyescan_reset(ctrl_eyescan_reset), + .gt_rx_reset_done(rx_reset_done), + .gt_rx_pma_reset_done(rx_pma_reset_done), + .gt_rx_prgdiv_reset_done(rx_prgdiv_reset_done), + .gt_rx_pd(ctrl_rx_pd), + .gt_rx_qpll_sel(ctrl_rx_qpll_sel), + + .gt_rxcdrhold(ctrl_rxcdrhold), + .gt_rxlpmen(ctrl_rxlpmen), + + .gt_txprbssel(ctrl_txprbssel), + .gt_txprbsforceerr(ctrl_txprbsforceerr), + .gt_txpolarity(ctrl_txpolarity), + .gt_txelecidle(ctrl_txelecidle), + .gt_txinhibit(ctrl_txinhibit), + .gt_txdiffctrl(ctrl_txdiffctrl), + .gt_txmaincursor(ctrl_txmaincursor), + .gt_txpostcursor(ctrl_txpostcursor), + .gt_txprecursor(ctrl_txprecursor), + + .gt_rxpolarity(ctrl_rxpolarity), + .gt_rxprbscntreset(ctrl_rxprbscntreset), + .gt_rxprbssel(ctrl_rxprbssel), + + .gt_rxprbserr(ctrl_rxprbserr), + + .gt_dmonitorout(ctrl_dmonitorout), + + .phy_rx_reset_req_en(ctrl_phy_rx_reset_req_en) +); + wire gt_qpll0_pd; wire gt_qpll0_reset; wire gt_qpll1_pd; wire gt_qpll1_reset; -wire qpll0_lock; -wire qpll1_lock; - if (HAS_COMMON) begin : common_ctrl taxi_gt_qpll_reset #( @@ -161,8 +345,8 @@ if (HAS_COMMON) begin : common_ctrl /* * Control/status */ - .qpll_reset_in(1'b0), - .qpll_pd_in(QPLL0_PD), + .qpll_reset_in(ctrl_qpll0_reset), + .qpll_pd_in(ctrl_qpll0_pd), .qpll_lock_out(qpll0_lock) ); @@ -184,8 +368,8 @@ if (HAS_COMMON) begin : common_ctrl /* * Control/status */ - .qpll_reset_in(1'b0), - .qpll_pd_in(QPLL1_PD), + .qpll_reset_in(ctrl_qpll1_reset), + .qpll_pd_in(ctrl_qpll1_pd), .qpll_lock_out(qpll1_lock) ); @@ -220,8 +404,6 @@ wire gt_tx_prgdiv_reset_done; wire gt_tx_qpll_sel; wire gt_tx_userrdy; -wire tx_reset_done; - taxi_sync_reset #( .N(4) ) @@ -243,6 +425,7 @@ gt_tx_reset_inst ( /* * GT */ + .gt_txusrclk2(tx_clk), .gt_tx_pd_out(gt_tx_pd), .gt_tx_reset_out(gt_tx_reset), .gt_tx_reset_done_in(gt_tx_reset_done), @@ -260,14 +443,14 @@ gt_tx_reset_inst ( */ .qpll0_lock_in(qpll0_lock), .qpll1_lock_in(qpll1_lock), - .tx_reset_in(tx_rst_in), + .tx_reset_in(tx_rst_in || ctrl_tx_reset), .tx_reset_done_out(tx_reset_done), - .tx_pma_reset_in(1'b0), - .tx_pma_reset_done_out(), - .tx_prgdiv_reset_done_out(), - .tx_pcs_reset_in(1'b0), - .tx_pd_in(GT_TX_PD), - .tx_qpll_sel_in(GT_TX_QPLL_SEL) + .tx_pma_reset_in(ctrl_tx_pma_reset), + .tx_pma_reset_done_out(tx_pma_reset_done), + .tx_prgdiv_reset_done_out(tx_prgdiv_reset_done), + .tx_pcs_reset_in(ctrl_tx_pcs_reset), + .tx_pd_in(ctrl_tx_pd), + .tx_qpll_sel_in(ctrl_tx_qpll_sel) ); wire gt_rx_pd; @@ -286,8 +469,6 @@ wire gt_rx_userrdy; wire gt_rx_cdr_lock; wire gt_rx_lpm_en; -wire rx_reset_done; - taxi_sync_reset #( .N(4) ) @@ -311,6 +492,7 @@ gt_rx_reset_inst ( /* * GT */ + .gt_rxusrclk2(rx_clk), .gt_rx_pd_out(gt_rx_pd), .gt_rx_reset_out(gt_rx_reset), .gt_rx_reset_done_in(gt_rx_reset_done), @@ -332,17 +514,17 @@ gt_rx_reset_inst ( */ .qpll0_lock_in(qpll0_lock), .qpll1_lock_in(qpll1_lock), - .rx_reset_in(rx_rst_in), + .rx_reset_in(rx_rst_in || ctrl_rx_reset), .rx_reset_done_out(rx_reset_done), - .rx_pma_reset_in(1'b0), - .rx_pma_reset_done_out(), - .rx_prgdiv_reset_done_out(), - .rx_pcs_reset_in(1'b0), - .rx_dfe_lpm_reset_in(1'b0), - .eyescan_reset_in(1'b0), - .rx_pd_in(GT_RX_PD), - .rx_qpll_sel_in(GT_RX_QPLL_SEL), - .rx_lpm_en_in(GT_RX_LPM_EN) + .rx_pma_reset_in(ctrl_rx_pma_reset), + .rx_pma_reset_done_out(rx_pma_reset_done), + .rx_prgdiv_reset_done_out(rx_prgdiv_reset_done), + .rx_pcs_reset_in(ctrl_rx_pcs_reset), + .rx_dfe_lpm_reset_in(ctrl_rx_dfe_lpm_reset), + .eyescan_reset_in(ctrl_eyescan_reset), + .rx_pd_in(ctrl_rx_pd), + .rx_qpll_sel_in(ctrl_rx_qpll_sel), + .rx_lpm_en_in(ctrl_rxlpmen) ); wire [6:0] gt_txsequence; @@ -430,6 +612,12 @@ if (SIM) begin : xcvr assign gt_rx_prgdiv_reset_done = gt_rx_reset_done; assign gt_rx_cdr_lock = gt_rx_reset_done; + assign com_drp_do = 16'hCC00; + assign com_drp_rdy = 1'b1; + + assign gt_drp_do = 16'hDA00; + assign gt_drp_rdy = 1'b1; + end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr // UltraScale+ GTY (with common) @@ -438,6 +626,23 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -486,13 +691,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -529,7 +734,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -547,6 +752,23 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -595,13 +817,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -638,7 +860,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -656,6 +878,23 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -704,13 +943,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -747,7 +986,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -765,6 +1004,23 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -813,13 +1069,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -856,7 +1112,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -874,6 +1130,15 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .qpll0clk_in(xcvr_qpll0clk_in), .qpll0refclk_in(xcvr_qpll0refclk_in), @@ -910,13 +1175,13 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -953,7 +1218,7 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -971,6 +1236,9 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr assign xcvr_qpll1clk_out = 1'b0; assign xcvr_qpll1refclk_out = 1'b0; + assign com_drp_do = '0; + assign com_drp_rdy = 1'b1; + end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr // UltraScale/UltraScale+ GTH (channel only) @@ -979,6 +1247,15 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .qpll0clk_in(xcvr_qpll0clk_in), .qpll0refclk_in(xcvr_qpll0refclk_in), @@ -1015,13 +1292,13 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -1058,7 +1335,7 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -1076,6 +1353,9 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr assign xcvr_qpll1clk_out = 1'b0; assign xcvr_qpll1refclk_out = 1'b0; + assign com_drp_do = '0; + assign com_drp_rdy = 1'b1; + end else begin $fatal(0, "Error: invalid configuration (%m)"); diff --git a/src/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl b/src/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl index 9b4613a..52e6126 100644 --- a/src/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl @@ -22,6 +22,9 @@ set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out # PLL reset and power down lappend extra_pll_ports qpll0reset_in qpll1reset_in lappend extra_pll_ports qpll0pd_in qpll1pd_in diff --git a/src/eth/rtl/us/taxi_eth_phy_10g_us_gth_161.tcl b/src/eth/rtl/us/taxi_eth_phy_10g_us_gth_161.tcl index 88095d1..a9fc3b8 100644 --- a/src/eth/rtl/us/taxi_eth_phy_10g_us_gth_161.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_10g_us_gth_161.tcl @@ -22,6 +22,9 @@ set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out # PLL reset and power down lappend extra_pll_ports qpll0reset_in qpll1reset_in lappend extra_pll_ports qpll0pd_in qpll1pd_in diff --git a/src/eth/rtl/us/taxi_eth_phy_10g_us_gth_322.tcl b/src/eth/rtl/us/taxi_eth_phy_10g_us_gth_322.tcl index 9ea5a4e..e3c54c7 100644 --- a/src/eth/rtl/us/taxi_eth_phy_10g_us_gth_322.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_10g_us_gth_322.tcl @@ -22,6 +22,9 @@ set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out # PLL reset and power down lappend extra_pll_ports qpll0reset_in qpll1reset_in lappend extra_pll_ports qpll0pd_in qpll1pd_in diff --git a/src/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl b/src/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl index 8360cb1..7c84196 100644 --- a/src/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl @@ -22,6 +22,9 @@ set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out # PLL reset and power down lappend extra_pll_ports qpll0reset_in qpll1reset_in lappend extra_pll_ports qpll0pd_in qpll1pd_in diff --git a/src/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl b/src/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl index a7061d2..0d3e3a0 100644 --- a/src/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl @@ -22,6 +22,9 @@ set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out # PLL reset and power down lappend extra_pll_ports qpll0reset_in qpll1reset_in lappend extra_pll_ports qpll0pd_in qpll1pd_in diff --git a/src/eth/rtl/us/taxi_eth_phy_10g_us_gty_322.tcl b/src/eth/rtl/us/taxi_eth_phy_10g_us_gty_322.tcl index 1eb040c..86b1dc9 100644 --- a/src/eth/rtl/us/taxi_eth_phy_10g_us_gty_322.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_10g_us_gty_322.tcl @@ -22,6 +22,9 @@ set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out # PLL reset and power down lappend extra_pll_ports qpll0reset_in qpll1reset_in lappend extra_pll_ports qpll0pd_in qpll1pd_in diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.f b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.f index 3549bae..472f2d4 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.f +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.f @@ -1,6 +1,8 @@ taxi_eth_phy_25g_us_gt.sv +taxi_eth_phy_25g_us_gt_apb.sv ../../lib/taxi/src/sync/rtl/taxi_sync_reset.sv ../../lib/taxi/src/sync/rtl/taxi_sync_signal.sv ../../lib/taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv ../../lib/taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv ../../lib/taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv +../../lib/taxi/src/apb/rtl/taxi_apb_if.sv diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv index 8e1a553..d0c3147 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv @@ -55,6 +55,11 @@ module taxi_eth_phy_25g_us_gt # input wire logic xcvr_ctrl_clk, input wire logic xcvr_ctrl_rst, + /* + * Transceiver control + */ + taxi_apb_if.slv s_apb_ctrl, + /* * Common */ @@ -133,14 +138,193 @@ if (DATA_W != 64) if (HDR_W != 2) $fatal(0, "Error: HDR_W must be 2"); +// status +wire qpll0_lock; +wire qpll1_lock; + +wire tx_reset_done; +wire tx_pma_reset_done; +wire tx_prgdiv_reset_done; + +wire rx_reset_done; +wire rx_pma_reset_done; +wire rx_prgdiv_reset_done; + +// control registers +wire [10:0] gt_drp_addr; +wire [15:0] gt_drp_di; +wire gt_drp_en; +wire gt_drp_we; +wire [15:0] gt_drp_do; +wire gt_drp_rdy; + +wire [10:0] com_drp_addr; +wire [15:0] com_drp_di; +wire com_drp_en; +wire com_drp_we; +wire [15:0] com_drp_do; +wire com_drp_rdy; + +wire ctrl_qpll0_reset; +wire ctrl_qpll0_pd; +wire ctrl_qpll1_reset; +wire ctrl_qpll1_pd; + +wire [2:0] ctrl_loopback; + +wire ctrl_tx_reset; +wire ctrl_tx_pma_reset; +wire ctrl_tx_pcs_reset; +wire ctrl_tx_pd; +wire ctrl_tx_qpll_sel; +wire ctrl_rx_reset; +wire ctrl_rx_pma_reset; +wire ctrl_rx_pcs_reset; +wire ctrl_rx_dfe_lpm_reset; +wire ctrl_eyescan_reset; +wire ctrl_rx_pd; +wire ctrl_rx_qpll_sel; + +wire ctrl_rxcdrhold; +wire ctrl_rxlpmen; + +wire [3:0] ctrl_txprbssel; +wire ctrl_txprbsforceerr; +wire ctrl_txpolarity; +wire ctrl_txelecidle; +wire ctrl_txinhibit; +wire [4:0] ctrl_txdiffctrl; +wire [6:0] ctrl_txmaincursor; +wire [4:0] ctrl_txpostcursor; +wire [4:0] ctrl_txprecursor; + +wire ctrl_rxpolarity; +wire ctrl_rxprbscntreset; +wire [3:0] ctrl_rxprbssel; + +wire ctrl_rxprbserr; + +wire [15:0] ctrl_dmonitorout; + +wire ctrl_phy_rx_reset_req_en; + +taxi_eth_phy_25g_us_gt_apb #( + .HAS_COMMON(HAS_COMMON), + + // PLL parameters + .QPLL0_PD(QPLL0_PD), + .QPLL1_PD(QPLL1_PD), + + // GT parameters + .GT_TX_PD(GT_TX_PD), + .GT_TX_QPLL_SEL(GT_TX_QPLL_SEL), + .GT_TX_POLARITY(GT_TX_POLARITY), + .GT_TX_ELECIDLE(GT_TX_ELECIDLE), + .GT_TX_INHIBIT(GT_TX_INHIBIT), + .GT_TX_DIFFCTRL(GT_TX_DIFFCTRL), + .GT_TX_MAINCURSOR(GT_TX_MAINCURSOR), + .GT_TX_POSTCURSOR(GT_TX_POSTCURSOR), + .GT_TX_PRECURSOR(GT_TX_PRECURSOR), + .GT_RX_PD(GT_RX_PD), + .GT_RX_QPLL_SEL(GT_RX_QPLL_SEL), + .GT_RX_LPM_EN(GT_RX_LPM_EN), + .GT_RX_POLARITY(GT_RX_POLARITY) +) +ctrl_regs_inst ( + .clk(xcvr_ctrl_clk), + .rst(xcvr_ctrl_rst), + + /* + * Transceiver clocks + */ + .gt_txusrclk2(tx_clk), + .gt_rxusrclk2(rx_clk), + + /* + * Transceiver control + */ + .s_apb_ctrl(s_apb_ctrl), + + /* + * DRP (channel) + */ + .gt_drp_addr(gt_drp_addr), + .gt_drp_di(gt_drp_di), + .gt_drp_en(gt_drp_en), + .gt_drp_we(gt_drp_we), + .gt_drp_do(gt_drp_do), + .gt_drp_rdy(gt_drp_rdy), + + /* + * DRP (common) + */ + .com_drp_addr(com_drp_addr), + .com_drp_di(com_drp_di), + .com_drp_en(com_drp_en), + .com_drp_we(com_drp_we), + .com_drp_do(com_drp_do), + .com_drp_rdy(com_drp_rdy), + + /* + * Control and status signals + */ + .qpll0_reset(ctrl_qpll0_reset), + .qpll0_pd(ctrl_qpll0_pd), + .qpll0_lock(qpll0_lock), + .qpll1_reset(ctrl_qpll1_reset), + .qpll1_pd(ctrl_qpll1_pd), + .qpll1_lock(qpll1_lock), + + .gt_loopback(ctrl_loopback), + + .gt_tx_reset(ctrl_tx_reset), + .gt_tx_pma_reset(ctrl_tx_pma_reset), + .gt_tx_pcs_reset(ctrl_tx_pcs_reset), + .gt_tx_reset_done(tx_reset_done), + .gt_tx_pma_reset_done(tx_pma_reset_done), + .gt_tx_prgdiv_reset_done(tx_prgdiv_reset_done), + .gt_tx_pd(ctrl_tx_pd), + .gt_tx_qpll_sel(ctrl_tx_qpll_sel), + .gt_rx_reset(ctrl_rx_reset), + .gt_rx_pma_reset(ctrl_rx_pma_reset), + .gt_rx_pcs_reset(ctrl_rx_pcs_reset), + .gt_rx_dfe_lpm_reset(ctrl_rx_dfe_lpm_reset), + .gt_eyescan_reset(ctrl_eyescan_reset), + .gt_rx_reset_done(rx_reset_done), + .gt_rx_pma_reset_done(rx_pma_reset_done), + .gt_rx_prgdiv_reset_done(rx_prgdiv_reset_done), + .gt_rx_pd(ctrl_rx_pd), + .gt_rx_qpll_sel(ctrl_rx_qpll_sel), + + .gt_rxcdrhold(ctrl_rxcdrhold), + .gt_rxlpmen(ctrl_rxlpmen), + + .gt_txprbssel(ctrl_txprbssel), + .gt_txprbsforceerr(ctrl_txprbsforceerr), + .gt_txpolarity(ctrl_txpolarity), + .gt_txelecidle(ctrl_txelecidle), + .gt_txinhibit(ctrl_txinhibit), + .gt_txdiffctrl(ctrl_txdiffctrl), + .gt_txmaincursor(ctrl_txmaincursor), + .gt_txpostcursor(ctrl_txpostcursor), + .gt_txprecursor(ctrl_txprecursor), + + .gt_rxpolarity(ctrl_rxpolarity), + .gt_rxprbscntreset(ctrl_rxprbscntreset), + .gt_rxprbssel(ctrl_rxprbssel), + + .gt_rxprbserr(ctrl_rxprbserr), + + .gt_dmonitorout(ctrl_dmonitorout), + + .phy_rx_reset_req_en(ctrl_phy_rx_reset_req_en) +); + wire gt_qpll0_pd; wire gt_qpll0_reset; wire gt_qpll1_pd; wire gt_qpll1_reset; -wire qpll0_lock; -wire qpll1_lock; - if (HAS_COMMON) begin : common_ctrl taxi_gt_qpll_reset #( @@ -161,8 +345,8 @@ if (HAS_COMMON) begin : common_ctrl /* * Control/status */ - .qpll_reset_in(1'b0), - .qpll_pd_in(QPLL0_PD), + .qpll_reset_in(ctrl_qpll0_reset), + .qpll_pd_in(ctrl_qpll0_pd), .qpll_lock_out(qpll0_lock) ); @@ -184,8 +368,8 @@ if (HAS_COMMON) begin : common_ctrl /* * Control/status */ - .qpll_reset_in(1'b0), - .qpll_pd_in(QPLL1_PD), + .qpll_reset_in(ctrl_qpll1_reset), + .qpll_pd_in(ctrl_qpll1_pd), .qpll_lock_out(qpll1_lock) ); @@ -220,8 +404,6 @@ wire gt_tx_prgdiv_reset_done; wire gt_tx_qpll_sel; wire gt_tx_userrdy; -wire tx_reset_done; - taxi_sync_reset #( .N(4) ) @@ -243,6 +425,7 @@ gt_tx_reset_inst ( /* * GT */ + .gt_txusrclk2(tx_clk), .gt_tx_pd_out(gt_tx_pd), .gt_tx_reset_out(gt_tx_reset), .gt_tx_reset_done_in(gt_tx_reset_done), @@ -260,14 +443,14 @@ gt_tx_reset_inst ( */ .qpll0_lock_in(qpll0_lock), .qpll1_lock_in(qpll1_lock), - .tx_reset_in(tx_rst_in), + .tx_reset_in(tx_rst_in || ctrl_tx_reset), .tx_reset_done_out(tx_reset_done), - .tx_pma_reset_in(1'b0), - .tx_pma_reset_done_out(), - .tx_prgdiv_reset_done_out(), - .tx_pcs_reset_in(1'b0), - .tx_pd_in(GT_TX_PD), - .tx_qpll_sel_in(GT_TX_QPLL_SEL) + .tx_pma_reset_in(ctrl_tx_pma_reset), + .tx_pma_reset_done_out(tx_pma_reset_done), + .tx_prgdiv_reset_done_out(tx_prgdiv_reset_done), + .tx_pcs_reset_in(ctrl_tx_pcs_reset), + .tx_pd_in(ctrl_tx_pd), + .tx_qpll_sel_in(ctrl_tx_qpll_sel) ); wire gt_rx_pd; @@ -286,8 +469,6 @@ wire gt_rx_userrdy; wire gt_rx_cdr_lock; wire gt_rx_lpm_en; -wire rx_reset_done; - taxi_sync_reset #( .N(4) ) @@ -311,6 +492,7 @@ gt_rx_reset_inst ( /* * GT */ + .gt_rxusrclk2(rx_clk), .gt_rx_pd_out(gt_rx_pd), .gt_rx_reset_out(gt_rx_reset), .gt_rx_reset_done_in(gt_rx_reset_done), @@ -332,17 +514,17 @@ gt_rx_reset_inst ( */ .qpll0_lock_in(qpll0_lock), .qpll1_lock_in(qpll1_lock), - .rx_reset_in(rx_rst_in), + .rx_reset_in(rx_rst_in || ctrl_rx_reset), .rx_reset_done_out(rx_reset_done), - .rx_pma_reset_in(1'b0), - .rx_pma_reset_done_out(), - .rx_prgdiv_reset_done_out(), - .rx_pcs_reset_in(1'b0), - .rx_dfe_lpm_reset_in(1'b0), - .eyescan_reset_in(1'b0), - .rx_pd_in(GT_RX_PD), - .rx_qpll_sel_in(GT_RX_QPLL_SEL), - .rx_lpm_en_in(GT_RX_LPM_EN) + .rx_pma_reset_in(ctrl_rx_pma_reset), + .rx_pma_reset_done_out(rx_pma_reset_done), + .rx_prgdiv_reset_done_out(rx_prgdiv_reset_done), + .rx_pcs_reset_in(ctrl_rx_pcs_reset), + .rx_dfe_lpm_reset_in(ctrl_rx_dfe_lpm_reset), + .eyescan_reset_in(ctrl_eyescan_reset), + .rx_pd_in(ctrl_rx_pd), + .rx_qpll_sel_in(ctrl_rx_qpll_sel), + .rx_lpm_en_in(ctrl_rxlpmen) ); wire [6:0] gt_txsequence; @@ -394,6 +576,12 @@ if (SIM) begin : xcvr assign gt_rx_prgdiv_reset_done = gt_rx_reset_done; assign gt_rx_cdr_lock = gt_rx_reset_done; + assign com_drp_do = 16'hCC00; + assign com_drp_rdy = 1'b1; + + assign gt_drp_do = 16'hDA00; + assign gt_drp_rdy = 1'b1; + end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr // UltraScale+ GTY (with common) @@ -402,6 +590,23 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -446,13 +651,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -485,7 +690,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -503,6 +708,23 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -547,13 +769,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -586,7 +808,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -604,6 +826,23 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -648,13 +887,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -687,7 +926,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -705,6 +944,23 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -749,13 +1005,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -788,7 +1044,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -806,6 +1062,15 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .qpll0clk_in(xcvr_qpll0clk_in), .qpll0refclk_in(xcvr_qpll0refclk_in), @@ -838,13 +1103,13 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -877,7 +1142,7 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -895,6 +1160,9 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr assign xcvr_qpll1clk_out = 1'b0; assign xcvr_qpll1refclk_out = 1'b0; + assign com_drp_do = '0; + assign com_drp_rdy = 1'b1; + end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr // UltraScale/UltraScale+ GTH (channel only) @@ -903,6 +1171,15 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .qpll0clk_in(xcvr_qpll0clk_in), .qpll0refclk_in(xcvr_qpll0refclk_in), @@ -935,13 +1212,13 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -974,7 +1251,7 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -992,6 +1269,9 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr assign xcvr_qpll1clk_out = 1'b0; assign xcvr_qpll1refclk_out = 1'b0; + assign com_drp_do = '0; + assign com_drp_rdy = 1'b1; + end else begin $fatal(0, "Error: invalid configuration (%m)"); diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_apb.sv b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_apb.sv new file mode 100644 index 0000000..c1b6762 --- /dev/null +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_apb.sv @@ -0,0 +1,567 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver wrapper APB interface for UltraScale/UltraScale+ + */ +module taxi_eth_phy_25g_us_gt_apb # +( + // parameter logic SIM = 1'b0, + // parameter string VENDOR = "XILINX", + // parameter string FAMILY = "virtexuplus", + + parameter logic HAS_COMMON = 1'b1, + + // // GT type + // parameter string GT_TYPE = "GTY", + + // PLL parameters + parameter logic QPLL0_PD = 1'b0, + parameter logic QPLL1_PD = 1'b1, + // parameter logic QPLL0_EXT_CTRL = 1'b0, + // parameter logic QPLL1_EXT_CTRL = 1'b0, + + // GT parameters + parameter logic GT_TX_PD = 1'b0, + parameter logic GT_TX_QPLL_SEL = 1'b0, + parameter logic GT_TX_POLARITY = 1'b0, + parameter logic GT_TX_ELECIDLE = 1'b0, + parameter logic GT_TX_INHIBIT = 1'b0, + parameter logic [4:0] GT_TX_DIFFCTRL = 5'd16, + parameter logic [6:0] GT_TX_MAINCURSOR = 7'd64, + parameter logic [4:0] GT_TX_POSTCURSOR = 5'd0, + parameter logic [4:0] GT_TX_PRECURSOR = 5'd0, + parameter logic GT_RX_PD = 1'b0, + parameter logic GT_RX_QPLL_SEL = 1'b0, + parameter logic GT_RX_LPM_EN = 1'b0, + parameter logic GT_RX_POLARITY = 1'b0 + + // // MAC/PHY parameters + // parameter DATA_W = 64 +) +( + input wire logic clk, + input wire logic rst, + + /* + * Transceiver clocks + */ + input wire logic gt_txusrclk2, + input wire logic gt_rxusrclk2, + + /* + * Transceiver control + */ + taxi_apb_if.slv s_apb_ctrl, + + /* + * DRP (channel) + */ + output wire logic [10:0] gt_drp_addr, + output wire logic [15:0] gt_drp_di, + output wire logic gt_drp_en, + output wire logic gt_drp_we, + input wire logic [15:0] gt_drp_do = '0, + input wire logic gt_drp_rdy = 1'b1, + + /* + * DRP (common) + */ + output wire logic [10:0] com_drp_addr, + output wire logic [15:0] com_drp_di, + output wire logic com_drp_en, + output wire logic com_drp_we, + input wire logic [15:0] com_drp_do = '0, + input wire logic com_drp_rdy = 1'b1, + + /* + * Control and status signals + */ + output wire logic qpll0_reset, + output wire logic qpll0_pd, + input wire logic qpll0_lock, + output wire logic qpll1_reset, + output wire logic qpll1_pd, + input wire logic qpll1_lock, + + output wire logic [2:0] gt_loopback, + + output wire logic gt_tx_reset, + output wire logic gt_tx_pma_reset, + output wire logic gt_tx_pcs_reset, + input wire logic gt_tx_reset_done, + input wire logic gt_tx_pma_reset_done, + input wire logic gt_tx_prgdiv_reset_done, + output wire logic gt_tx_pd, + output wire logic gt_tx_qpll_sel, + output wire logic gt_rx_reset, + output wire logic gt_rx_pma_reset, + output wire logic gt_rx_pcs_reset, + output wire logic gt_rx_dfe_lpm_reset, + output wire logic gt_eyescan_reset, + input wire logic gt_rx_reset_done, + input wire logic gt_rx_pma_reset_done, + input wire logic gt_rx_prgdiv_reset_done, + output wire logic gt_rx_pd, + output wire logic gt_rx_qpll_sel, + + output wire logic gt_rxcdrhold, + output wire logic gt_rxlpmen, + + output wire logic [3:0] gt_txprbssel, + output wire logic gt_txprbsforceerr, + output wire logic gt_txpolarity, + output wire logic gt_txelecidle, + output wire logic gt_txinhibit, + output wire logic [4:0] gt_txdiffctrl, + output wire logic [6:0] gt_txmaincursor, + output wire logic [4:0] gt_txpostcursor, + output wire logic [4:0] gt_txprecursor, + + output wire logic gt_rxpolarity, + output wire logic gt_rxprbscntreset, + output wire logic [3:0] gt_rxprbssel, + + input wire logic gt_rxprbserr, + + input wire logic [15:0] gt_dmonitorout, + + output wire logic phy_rx_reset_req_en +); + +// check configuration +if (s_apb_ctrl.DATA_W != 16) + $fatal(0, "Error: APB interface DATA_W must be 16 (instance %m)"); + +if (s_apb_ctrl.ADDR_W < 16) + $fatal(0, "Error: APB interface ADDR_W must be at least 16 (instance %m)"); + +logic act_reg = 1'b0; + +logic s_apb_ctrl_pready_reg = 1'b0; +logic [15:0] s_apb_ctrl_prdata_reg = '0; +logic s_apb_ctrl_pslverr_reg = 1'b0; + +logic [10:0] drp_addr_reg = '0; +logic [15:0] drp_di_reg = '0; +logic gt_drp_en_reg = 1'b0; +logic gt_drp_we_reg = 1'b0; +logic com_drp_en_reg = 1'b0; +logic com_drp_we_reg = 1'b0; + +logic qpll0_reset_reg = 1'b0; +logic qpll0_pd_reg = QPLL0_PD; +logic qpll1_reset_reg = 1'b0; +logic qpll1_pd_reg = QPLL1_PD; + +logic [2:0] gt_loopback_reg = 3'b000; + +logic gt_tx_reset_reg = 1'b0; +logic gt_tx_pma_reset_reg = 1'b0; +logic gt_tx_pcs_reset_reg = 1'b0; +logic gt_tx_pd_reg = GT_TX_PD; +logic gt_tx_qpll_sel_reg = GT_TX_QPLL_SEL; +logic gt_rx_reset_reg = 1'b0; +logic gt_rx_pma_reset_reg = 1'b0; +logic gt_rx_pcs_reset_reg = 1'b0; +logic gt_rx_dfe_lpm_reset_reg = 1'b0; +logic gt_eyescan_reset_reg = 1'b0; +logic gt_rx_pd_reg = GT_RX_PD; +logic gt_rx_qpll_sel_reg = GT_RX_QPLL_SEL; + +logic gt_rxcdrhold_reg = 1'b0; +logic gt_rxlpmen_reg = GT_RX_LPM_EN; + +logic [3:0] gt_txprbssel_reg = 4'd0; +logic gt_txprbsforceerr_reg = 1'b0; +logic gt_txpolarity_reg = GT_TX_POLARITY; +logic gt_txelecidle_reg = GT_TX_ELECIDLE; +logic gt_txinhibit_reg = GT_TX_INHIBIT; +logic [4:0] gt_txdiffctrl_reg = GT_TX_DIFFCTRL; +logic [6:0] gt_txmaincursor_reg = GT_TX_MAINCURSOR; +logic [4:0] gt_txpostcursor_reg = GT_TX_POSTCURSOR; +logic [4:0] gt_txprecursor_reg = GT_TX_PRECURSOR; + +logic gt_rxpolarity_reg = GT_RX_POLARITY; +logic gt_rxprbscntreset_reg = 1'b0; +logic [3:0] gt_rxprbssel_reg = 4'd0; + +logic gt_rxprbserr_reg = 1'b0; + +logic phy_rx_reset_req_en_reg = 1'b1; + +assign s_apb_ctrl.pready = s_apb_ctrl_pready_reg; +assign s_apb_ctrl.prdata = s_apb_ctrl_prdata_reg; +assign s_apb_ctrl.pslverr = s_apb_ctrl_pslverr_reg; +assign s_apb_ctrl.pruser = '0; +assign s_apb_ctrl.pbuser = '0; + +assign gt_drp_addr = drp_addr_reg; +assign gt_drp_di = drp_di_reg; +assign gt_drp_en = gt_drp_en_reg; +assign gt_drp_we = gt_drp_we_reg; + +assign com_drp_addr = drp_addr_reg; +assign com_drp_di = drp_di_reg; +assign com_drp_en = com_drp_en_reg; +assign com_drp_we = com_drp_we_reg; + +assign qpll0_reset = qpll0_reset_reg; +assign qpll0_pd = qpll0_pd_reg; +assign qpll1_reset = qpll1_reset_reg; +assign qpll1_pd = qpll1_pd_reg; + +assign gt_loopback = gt_loopback_reg; + +assign gt_tx_reset = gt_tx_reset_reg; +assign gt_tx_pma_reset = gt_tx_pma_reset_reg; +assign gt_tx_pcs_reset = gt_tx_pcs_reset_reg; +assign gt_tx_pd = gt_tx_pd_reg; +assign gt_tx_qpll_sel = gt_tx_qpll_sel_reg; +assign gt_rx_reset = gt_rx_reset_reg; +assign gt_rx_pma_reset = gt_rx_pma_reset_reg; +assign gt_rx_pcs_reset = gt_rx_pcs_reset_reg; +assign gt_rx_dfe_lpm_reset = gt_rx_dfe_lpm_reset_reg; +assign gt_eyescan_reset = gt_eyescan_reset_reg; +assign gt_rx_pd = gt_rx_pd_reg; +assign gt_rx_qpll_sel = gt_rx_qpll_sel_reg; + +assign gt_rxcdrhold = gt_rxcdrhold_reg; +assign gt_rxlpmen = gt_rxlpmen_reg; + +assign gt_txprbsforceerr = gt_txprbsforceerr_reg; +assign gt_txdiffctrl = gt_txdiffctrl_reg; +assign gt_txmaincursor = gt_txmaincursor_reg; +assign gt_txpostcursor = gt_txpostcursor_reg; +assign gt_txprecursor = gt_txprecursor_reg; + +taxi_sync_signal #( + .WIDTH(3+4), + .N(2) +) +tx_ctrl_sync_inst ( + .clk(gt_txusrclk2), + .in({gt_txpolarity_reg, gt_txelecidle_reg, gt_txinhibit_reg, gt_txprbssel_reg}), + .out({gt_txpolarity, gt_txelecidle, gt_txinhibit, gt_txprbssel}) +); + +taxi_sync_signal #( + .WIDTH(1+4), + .N(2) +) +rx_ctrl_sync_inst ( + .clk(gt_rxusrclk2), + .in({gt_rxpolarity_reg, gt_rxprbssel_reg}), + .out({gt_rxpolarity, gt_rxprbssel}) +); + +assign gt_rxprbscntreset = gt_rxprbscntreset_reg; + +assign phy_rx_reset_req_en = phy_rx_reset_req_en_reg; + +always_ff @(posedge clk) begin + act_reg <= 1'b0; + + s_apb_ctrl_pready_reg <= 1'b0; + s_apb_ctrl_prdata_reg <= '0; + s_apb_ctrl_pslverr_reg <= 1'b0; + + drp_addr_reg <= s_apb_ctrl.paddr[1 +: 11]; + drp_di_reg <= s_apb_ctrl.pwdata; + + gt_drp_en_reg <= 1'b0; + gt_drp_we_reg <= 1'b0; + com_drp_en_reg <= 1'b0; + com_drp_we_reg <= 1'b0; + + if (s_apb_ctrl.psel && s_apb_ctrl.penable && !s_apb_ctrl_pready_reg) begin + act_reg <= 1'b1; + + case (s_apb_ctrl.paddr[15:14]) + 2'b00: begin + // registers + s_apb_ctrl_pready_reg <= 1'b1; + + if (HAS_COMMON) begin + case ({s_apb_ctrl.paddr[13:1], 1'b0}) + 14'd3000: begin + // QPLL0 + s_apb_ctrl_prdata_reg[0] <= qpll0_pd_reg; + s_apb_ctrl_prdata_reg[1] <= qpll0_reset_reg; + s_apb_ctrl_prdata_reg[8] <= qpll0_lock; + if (s_apb_ctrl.pwrite) begin + qpll0_pd_reg <= s_apb_ctrl.pwdata[0]; + qpll0_reset_reg <= s_apb_ctrl.pwdata[1]; + end + end + 14'd3100: begin + // QPLL1 + s_apb_ctrl_prdata_reg[0] <= qpll1_pd_reg; + s_apb_ctrl_prdata_reg[1] <= qpll1_reset_reg; + s_apb_ctrl_prdata_reg[8] <= qpll1_lock; + if (s_apb_ctrl.pwrite) begin + qpll1_pd_reg <= s_apb_ctrl.pwdata[0]; + qpll1_reset_reg <= s_apb_ctrl.pwdata[1]; + end + end + default: begin + // no op + end + endcase + end + + case ({s_apb_ctrl.paddr[13:1], 1'b0}) + 14'h1000: begin + s_apb_ctrl_prdata_reg[0] <= gt_tx_reset_reg; + s_apb_ctrl_prdata_reg[1] <= gt_tx_pma_reset_reg; + s_apb_ctrl_prdata_reg[2] <= gt_tx_pcs_reset_reg; + // s_apb_ctrl_prdata_reg[8] <= tx_reset_done_reg; + s_apb_ctrl_prdata_reg[9] <= gt_tx_reset_done; + s_apb_ctrl_prdata_reg[10] <= gt_tx_pma_reset_done; + s_apb_ctrl_prdata_reg[11] <= gt_tx_prgdiv_reset_done; + // s_apb_ctrl_prdata_reg[12] <= gt_userclk_tx_active; + if (s_apb_ctrl.pwrite) begin + gt_tx_reset_reg <= s_apb_ctrl.pwdata[0]; + gt_tx_pma_reset_reg <= s_apb_ctrl.pwdata[1]; + gt_tx_pcs_reset_reg <= s_apb_ctrl.pwdata[2]; + end + end + 14'h1002: begin + s_apb_ctrl_prdata_reg[0] <= gt_tx_pd_reg; + s_apb_ctrl_prdata_reg[1] <= gt_tx_qpll_sel_reg; + if (s_apb_ctrl.pwrite) begin + gt_tx_pd_reg <= s_apb_ctrl.pwdata[0]; + gt_tx_qpll_sel_reg <= s_apb_ctrl.pwdata[1]; + end + end + 14'h1010: begin + s_apb_ctrl_prdata_reg[0] <= gt_txpolarity_reg; + s_apb_ctrl_prdata_reg[1] <= gt_txelecidle_reg; + s_apb_ctrl_prdata_reg[2] <= gt_txinhibit_reg; + if (s_apb_ctrl.pwrite) begin + gt_txpolarity_reg <= s_apb_ctrl.pwdata[0]; + gt_txelecidle_reg <= s_apb_ctrl.pwdata[1]; + gt_txinhibit_reg <= s_apb_ctrl.pwdata[2]; + end + end + 14'h1012: begin + s_apb_ctrl_prdata_reg[4:0] <= gt_txdiffctrl_reg; + if (s_apb_ctrl.pwrite) begin + gt_txdiffctrl_reg <= s_apb_ctrl.pwdata[4:0]; + end + end + 14'h1014: begin + s_apb_ctrl_prdata_reg[6:0] <= gt_txmaincursor_reg; + if (s_apb_ctrl.pwrite) begin + gt_txmaincursor_reg <= s_apb_ctrl.pwdata[6:0]; + end + end + 14'h1016: begin + s_apb_ctrl_prdata_reg[4:0] <= gt_txprecursor_reg; + if (s_apb_ctrl.pwrite) begin + gt_txprecursor_reg <= s_apb_ctrl.pwdata[4:0]; + end + end + 14'h1018: begin + s_apb_ctrl_prdata_reg[4:0] <= gt_txpostcursor_reg; + if (s_apb_ctrl.pwrite) begin + gt_txpostcursor_reg <= s_apb_ctrl.pwdata[4:0]; + end + end + 14'h1040: begin + s_apb_ctrl_prdata_reg[3:0] <= gt_txprbssel_reg; + if (s_apb_ctrl.pwrite) begin + gt_txprbssel_reg <= s_apb_ctrl.pwdata[3:0]; + end + end + 14'h1042: begin + if (s_apb_ctrl.pwrite) begin + // gt_txprbsforceerr_reg <= gt_txprbsforceerr_reg ^ s_apb_ctrl.pwdata[0]; + end + end + // RX + 14'h2000: begin + s_apb_ctrl_prdata_reg[0] <= gt_rx_reset_reg; + s_apb_ctrl_prdata_reg[1] <= gt_rx_pma_reset_reg; + s_apb_ctrl_prdata_reg[2] <= gt_rx_pcs_reset_reg; + s_apb_ctrl_prdata_reg[3] <= gt_rx_dfe_lpm_reset_reg; + s_apb_ctrl_prdata_reg[4] <= gt_eyescan_reset_reg; + // s_apb_ctrl_prdata_reg[8] <= rx_reset_done_reg; + s_apb_ctrl_prdata_reg[9] <= gt_rx_reset_done; + s_apb_ctrl_prdata_reg[10] <= gt_rx_pma_reset_done; + s_apb_ctrl_prdata_reg[11] <= gt_rx_prgdiv_reset_done; + // s_apb_ctrl_prdata_reg[12] <= gt_userclk_rx_active; + if (s_apb_ctrl.pwrite) begin + gt_rx_reset_reg <= s_apb_ctrl.pwdata[0]; + gt_rx_pma_reset_reg <= s_apb_ctrl.pwdata[1]; + gt_rx_pcs_reset_reg <= s_apb_ctrl.pwdata[2]; + gt_rx_dfe_lpm_reset_reg <= s_apb_ctrl.pwdata[3]; + gt_eyescan_reset_reg <= s_apb_ctrl.pwdata[4]; + end + end + 14'h2002: begin + s_apb_ctrl_prdata_reg[0] <= gt_rx_pd_reg; + s_apb_ctrl_prdata_reg[1] <= gt_rx_qpll_sel_reg; + if (s_apb_ctrl.pwrite) begin + gt_rx_pd_reg <= s_apb_ctrl.pwdata[0]; + gt_rx_qpll_sel_reg <= s_apb_ctrl.pwdata[1]; + end + end + 14'h2004: begin + s_apb_ctrl_prdata_reg[2:0] <= gt_loopback_reg; + if (s_apb_ctrl.pwrite) begin + gt_loopback_reg <= s_apb_ctrl.pwdata[2:0]; + end + end + 14'h2010: begin + s_apb_ctrl_prdata_reg[0] <= gt_rxpolarity_reg; + if (s_apb_ctrl.pwrite) begin + gt_rxpolarity_reg <= s_apb_ctrl.pwdata[0]; + end + end + 14'h2020: begin + s_apb_ctrl_prdata_reg[0] <= gt_rxcdrhold_reg; + // s_apb_ctrl_prdata_reg[8] <= gt_rxcdrlock; + if (s_apb_ctrl.pwrite) begin + gt_rxcdrhold_reg <= s_apb_ctrl.pwdata[0]; + end + end + 14'h2024: begin + s_apb_ctrl_prdata_reg[0] <= gt_rxlpmen_reg; + if (s_apb_ctrl.pwrite) begin + gt_rxlpmen_reg <= s_apb_ctrl.pwdata[0]; + end + end + // 14'h2028: s_apb_ctrl_prdata_reg <= gt_dmonitorout_reg; + 14'h2040: begin + s_apb_ctrl_prdata_reg[3:0] <= gt_rxprbssel_reg; + if (s_apb_ctrl.pwrite) begin + gt_rxprbssel_reg <= s_apb_ctrl.pwdata[3:0]; + end + end + 14'h2042: begin + // s_apb_ctrl_prdata_reg[8] <= gt_rxprbslocked; + s_apb_ctrl_prdata_reg[9] <= gt_rxprbserr_reg; + + if (s_apb_ctrl.pwrite) begin + // gt_rxprbscntreset_reg <= gt_rxprbscntreset_reg ^ s_apb_ctrl.pwdata[0]; + end else begin + // gt_rxprbserr_reg <= gt_rxprbserr; + end + end + default: begin + // no op + end + endcase + +// // PHY +// 16'h8000: begin +// drp_do_reg[0] <= tx_reset_done_reg; +// end +// 16'h8100: begin +// drp_do_reg[0] <= rx_reset_done_reg; +// drp_do_reg[8] <= phy_rx_block_lock_sync_2_reg; +// drp_do_reg[9] <= phy_rx_high_ber_sync_2_reg; +// drp_do_reg[10] <= phy_rx_status_sync_2_reg; +// end +// 16'h8101: begin +// drp_do_reg[0] <= phy_rx_reset_req_en_drp_reg; +// drp_do_reg[8] <= phy_rx_reset_req_drp_reg; + +// phy_rx_reset_req_drp_reg <= phy_rx_reset_req_sync_3_reg ^ phy_rx_reset_req_sync_4_reg; +// end + end + 2'b01: begin + // reserved + s_apb_ctrl_pready_reg <= 1'b1; + end + 2'b10: begin + // GT DRP + gt_drp_en_reg <= !act_reg; + gt_drp_we_reg <= s_apb_ctrl.pwrite && !act_reg; + + if (gt_drp_rdy) begin + s_apb_ctrl_prdata_reg <= gt_drp_do; + s_apb_ctrl_pready_reg <= 1'b1; + end + end + 2'b11: begin + // common DRP + com_drp_en_reg <= !act_reg; + com_drp_we_reg <= s_apb_ctrl.pwrite && !act_reg; + + if (com_drp_rdy) begin + s_apb_ctrl_prdata_reg <= com_drp_do; + s_apb_ctrl_pready_reg <= 1'b1; + end + end + endcase + end + + if (rst) begin + act_reg <= 1'b0; + + s_apb_ctrl_pready_reg <= 1'b0; + + gt_drp_en_reg <= 1'b0; + gt_drp_we_reg <= 1'b0; + com_drp_en_reg <= 1'b0; + com_drp_we_reg <= 1'b0; + + qpll0_reset_reg <= 1'b0; + qpll0_pd_reg <= QPLL0_PD; + qpll1_reset_reg <= 1'b0; + qpll1_pd_reg <= QPLL1_PD; + + gt_loopback_reg <= 3'b000; + + gt_tx_reset_reg <= 1'b0; + gt_tx_pma_reset_reg <= 1'b0; + gt_tx_pcs_reset_reg <= 1'b0; + gt_tx_pd_reg <= GT_TX_PD; + gt_tx_qpll_sel_reg <= GT_TX_QPLL_SEL; + gt_rx_reset_reg <= 1'b0; + gt_rx_pma_reset_reg <= 1'b0; + gt_rx_pcs_reset_reg <= 1'b0; + gt_rx_dfe_lpm_reset_reg <= 1'b0; + gt_eyescan_reset_reg <= 1'b0; + gt_rx_pd_reg <= GT_RX_PD; + gt_rx_qpll_sel_reg <= GT_RX_QPLL_SEL; + + gt_rxcdrhold_reg <= 1'b0; + gt_rxlpmen_reg <= GT_RX_LPM_EN; + + gt_txprbssel_reg <= 4'd0; + gt_txprbsforceerr_reg <= 1'b0; + gt_txpolarity_reg <= GT_TX_POLARITY; + gt_txelecidle_reg <= GT_TX_ELECIDLE; + gt_txinhibit_reg <= GT_TX_INHIBIT; + gt_txdiffctrl_reg <= GT_TX_DIFFCTRL; + gt_txmaincursor_reg <= GT_TX_MAINCURSOR; + gt_txpostcursor_reg <= GT_TX_POSTCURSOR; + gt_txprecursor_reg <= GT_TX_PRECURSOR; + + gt_rxpolarity_reg <= GT_RX_POLARITY; + gt_rxprbscntreset_reg <= 1'b0; + gt_rxprbssel_reg <= 4'd0; + + gt_rxprbserr_reg <= 1'b0; + + phy_rx_reset_req_en_reg <= 1'b1; + end +end + +endmodule + +`resetall diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.f b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.f index e4c0305..290646c 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.f +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.f @@ -1,6 +1,8 @@ taxi_eth_phy_25g_us_gt_ll.sv +taxi_eth_phy_25g_us_gt_apb.sv ../../lib/taxi/src/sync/rtl/taxi_sync_reset.sv ../../lib/taxi/src/sync/rtl/taxi_sync_signal.sv ../../lib/taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv ../../lib/taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv ../../lib/taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv +../../lib/taxi/src/apb/rtl/taxi_apb_if.sv diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv index 1517daf..be74d7b 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv @@ -55,6 +55,11 @@ module taxi_eth_phy_25g_us_gt_ll # input wire logic xcvr_ctrl_clk, input wire logic xcvr_ctrl_rst, + /* + * Transceiver control + */ + taxi_apb_if.slv s_apb_ctrl, + /* * Common */ @@ -133,14 +138,193 @@ if (DATA_W != 64) if (HDR_W != 2) $fatal(0, "Error: HDR_W must be 2"); +// status +wire qpll0_lock; +wire qpll1_lock; + +wire tx_reset_done; +wire tx_pma_reset_done; +wire tx_prgdiv_reset_done; + +wire rx_reset_done; +wire rx_pma_reset_done; +wire rx_prgdiv_reset_done; + +// control registers +wire [10:0] gt_drp_addr; +wire [15:0] gt_drp_di; +wire gt_drp_en; +wire gt_drp_we; +wire [15:0] gt_drp_do; +wire gt_drp_rdy; + +wire [10:0] com_drp_addr; +wire [15:0] com_drp_di; +wire com_drp_en; +wire com_drp_we; +wire [15:0] com_drp_do; +wire com_drp_rdy; + +wire ctrl_qpll0_reset; +wire ctrl_qpll0_pd; +wire ctrl_qpll1_reset; +wire ctrl_qpll1_pd; + +wire [2:0] ctrl_loopback; + +wire ctrl_tx_reset; +wire ctrl_tx_pma_reset; +wire ctrl_tx_pcs_reset; +wire ctrl_tx_pd; +wire ctrl_tx_qpll_sel; +wire ctrl_rx_reset; +wire ctrl_rx_pma_reset; +wire ctrl_rx_pcs_reset; +wire ctrl_rx_dfe_lpm_reset; +wire ctrl_eyescan_reset; +wire ctrl_rx_pd; +wire ctrl_rx_qpll_sel; + +wire ctrl_rxcdrhold; +wire ctrl_rxlpmen; + +wire [3:0] ctrl_txprbssel; +wire ctrl_txprbsforceerr; +wire ctrl_txpolarity; +wire ctrl_txelecidle; +wire ctrl_txinhibit; +wire [4:0] ctrl_txdiffctrl; +wire [6:0] ctrl_txmaincursor; +wire [4:0] ctrl_txpostcursor; +wire [4:0] ctrl_txprecursor; + +wire ctrl_rxpolarity; +wire ctrl_rxprbscntreset; +wire [3:0] ctrl_rxprbssel; + +wire ctrl_rxprbserr; + +wire [15:0] ctrl_dmonitorout; + +wire ctrl_phy_rx_reset_req_en; + +taxi_eth_phy_25g_us_gt_apb #( + .HAS_COMMON(HAS_COMMON), + + // PLL parameters + .QPLL0_PD(QPLL0_PD), + .QPLL1_PD(QPLL1_PD), + + // GT parameters + .GT_TX_PD(GT_TX_PD), + .GT_TX_QPLL_SEL(GT_TX_QPLL_SEL), + .GT_TX_POLARITY(GT_TX_POLARITY), + .GT_TX_ELECIDLE(GT_TX_ELECIDLE), + .GT_TX_INHIBIT(GT_TX_INHIBIT), + .GT_TX_DIFFCTRL(GT_TX_DIFFCTRL), + .GT_TX_MAINCURSOR(GT_TX_MAINCURSOR), + .GT_TX_POSTCURSOR(GT_TX_POSTCURSOR), + .GT_TX_PRECURSOR(GT_TX_PRECURSOR), + .GT_RX_PD(GT_RX_PD), + .GT_RX_QPLL_SEL(GT_RX_QPLL_SEL), + .GT_RX_LPM_EN(GT_RX_LPM_EN), + .GT_RX_POLARITY(GT_RX_POLARITY) +) +ctrl_regs_inst ( + .clk(xcvr_ctrl_clk), + .rst(xcvr_ctrl_rst), + + /* + * Transceiver clocks + */ + .gt_txusrclk2(tx_clk), + .gt_rxusrclk2(rx_clk), + + /* + * Transceiver control + */ + .s_apb_ctrl(s_apb_ctrl), + + /* + * DRP (channel) + */ + .gt_drp_addr(gt_drp_addr), + .gt_drp_di(gt_drp_di), + .gt_drp_en(gt_drp_en), + .gt_drp_we(gt_drp_we), + .gt_drp_do(gt_drp_do), + .gt_drp_rdy(gt_drp_rdy), + + /* + * DRP (common) + */ + .com_drp_addr(com_drp_addr), + .com_drp_di(com_drp_di), + .com_drp_en(com_drp_en), + .com_drp_we(com_drp_we), + .com_drp_do(com_drp_do), + .com_drp_rdy(com_drp_rdy), + + /* + * Control and status signals + */ + .qpll0_reset(ctrl_qpll0_reset), + .qpll0_pd(ctrl_qpll0_pd), + .qpll0_lock(qpll0_lock), + .qpll1_reset(ctrl_qpll1_reset), + .qpll1_pd(ctrl_qpll1_pd), + .qpll1_lock(qpll1_lock), + + .gt_loopback(ctrl_loopback), + + .gt_tx_reset(ctrl_tx_reset), + .gt_tx_pma_reset(ctrl_tx_pma_reset), + .gt_tx_pcs_reset(ctrl_tx_pcs_reset), + .gt_tx_reset_done(tx_reset_done), + .gt_tx_pma_reset_done(tx_pma_reset_done), + .gt_tx_prgdiv_reset_done(tx_prgdiv_reset_done), + .gt_tx_pd(ctrl_tx_pd), + .gt_tx_qpll_sel(ctrl_tx_qpll_sel), + .gt_rx_reset(ctrl_rx_reset), + .gt_rx_pma_reset(ctrl_rx_pma_reset), + .gt_rx_pcs_reset(ctrl_rx_pcs_reset), + .gt_rx_dfe_lpm_reset(ctrl_rx_dfe_lpm_reset), + .gt_eyescan_reset(ctrl_eyescan_reset), + .gt_rx_reset_done(rx_reset_done), + .gt_rx_pma_reset_done(rx_pma_reset_done), + .gt_rx_prgdiv_reset_done(rx_prgdiv_reset_done), + .gt_rx_pd(ctrl_rx_pd), + .gt_rx_qpll_sel(ctrl_rx_qpll_sel), + + .gt_rxcdrhold(ctrl_rxcdrhold), + .gt_rxlpmen(ctrl_rxlpmen), + + .gt_txprbssel(ctrl_txprbssel), + .gt_txprbsforceerr(ctrl_txprbsforceerr), + .gt_txpolarity(ctrl_txpolarity), + .gt_txelecidle(ctrl_txelecidle), + .gt_txinhibit(ctrl_txinhibit), + .gt_txdiffctrl(ctrl_txdiffctrl), + .gt_txmaincursor(ctrl_txmaincursor), + .gt_txpostcursor(ctrl_txpostcursor), + .gt_txprecursor(ctrl_txprecursor), + + .gt_rxpolarity(ctrl_rxpolarity), + .gt_rxprbscntreset(ctrl_rxprbscntreset), + .gt_rxprbssel(ctrl_rxprbssel), + + .gt_rxprbserr(ctrl_rxprbserr), + + .gt_dmonitorout(ctrl_dmonitorout), + + .phy_rx_reset_req_en(ctrl_phy_rx_reset_req_en) +); + wire gt_qpll0_pd; wire gt_qpll0_reset; wire gt_qpll1_pd; wire gt_qpll1_reset; -wire qpll0_lock; -wire qpll1_lock; - if (HAS_COMMON) begin : common_ctrl taxi_gt_qpll_reset #( @@ -161,8 +345,8 @@ if (HAS_COMMON) begin : common_ctrl /* * Control/status */ - .qpll_reset_in(1'b0), - .qpll_pd_in(QPLL0_PD), + .qpll_reset_in(ctrl_qpll0_reset), + .qpll_pd_in(ctrl_qpll0_pd), .qpll_lock_out(qpll0_lock) ); @@ -184,8 +368,8 @@ if (HAS_COMMON) begin : common_ctrl /* * Control/status */ - .qpll_reset_in(1'b0), - .qpll_pd_in(QPLL1_PD), + .qpll_reset_in(ctrl_qpll1_reset), + .qpll_pd_in(ctrl_qpll1_pd), .qpll_lock_out(qpll1_lock) ); @@ -220,8 +404,6 @@ wire gt_tx_prgdiv_reset_done; wire gt_tx_qpll_sel; wire gt_tx_userrdy; -wire tx_reset_done; - taxi_sync_reset #( .N(4) ) @@ -243,6 +425,7 @@ gt_tx_reset_inst ( /* * GT */ + .gt_txusrclk2(tx_clk), .gt_tx_pd_out(gt_tx_pd), .gt_tx_reset_out(gt_tx_reset), .gt_tx_reset_done_in(gt_tx_reset_done), @@ -260,14 +443,14 @@ gt_tx_reset_inst ( */ .qpll0_lock_in(qpll0_lock), .qpll1_lock_in(qpll1_lock), - .tx_reset_in(tx_rst_in), + .tx_reset_in(tx_rst_in || ctrl_tx_reset), .tx_reset_done_out(tx_reset_done), - .tx_pma_reset_in(1'b0), - .tx_pma_reset_done_out(), - .tx_prgdiv_reset_done_out(), - .tx_pcs_reset_in(1'b0), - .tx_pd_in(GT_TX_PD), - .tx_qpll_sel_in(GT_TX_QPLL_SEL) + .tx_pma_reset_in(ctrl_tx_pma_reset), + .tx_pma_reset_done_out(tx_pma_reset_done), + .tx_prgdiv_reset_done_out(tx_prgdiv_reset_done), + .tx_pcs_reset_in(ctrl_tx_pcs_reset), + .tx_pd_in(ctrl_tx_pd), + .tx_qpll_sel_in(ctrl_tx_qpll_sel) ); wire gt_rx_pd; @@ -286,8 +469,6 @@ wire gt_rx_userrdy; wire gt_rx_cdr_lock; wire gt_rx_lpm_en; -wire rx_reset_done; - taxi_sync_reset #( .N(4) ) @@ -311,6 +492,7 @@ gt_rx_reset_inst ( /* * GT */ + .gt_rxusrclk2(rx_clk), .gt_rx_pd_out(gt_rx_pd), .gt_rx_reset_out(gt_rx_reset), .gt_rx_reset_done_in(gt_rx_reset_done), @@ -332,17 +514,17 @@ gt_rx_reset_inst ( */ .qpll0_lock_in(qpll0_lock), .qpll1_lock_in(qpll1_lock), - .rx_reset_in(rx_rst_in), + .rx_reset_in(rx_rst_in || ctrl_rx_reset), .rx_reset_done_out(rx_reset_done), - .rx_pma_reset_in(1'b0), - .rx_pma_reset_done_out(), - .rx_prgdiv_reset_done_out(), - .rx_pcs_reset_in(1'b0), - .rx_dfe_lpm_reset_in(1'b0), - .eyescan_reset_in(1'b0), - .rx_pd_in(GT_RX_PD), - .rx_qpll_sel_in(GT_RX_QPLL_SEL), - .rx_lpm_en_in(GT_RX_LPM_EN) + .rx_pma_reset_in(ctrl_rx_pma_reset), + .rx_pma_reset_done_out(rx_pma_reset_done), + .rx_prgdiv_reset_done_out(rx_prgdiv_reset_done), + .rx_pcs_reset_in(ctrl_rx_pcs_reset), + .rx_dfe_lpm_reset_in(ctrl_rx_dfe_lpm_reset), + .eyescan_reset_in(ctrl_eyescan_reset), + .rx_pd_in(ctrl_rx_pd), + .rx_qpll_sel_in(ctrl_rx_qpll_sel), + .rx_lpm_en_in(ctrl_rxlpmen) ); wire [6:0] gt_txsequence; @@ -474,6 +656,12 @@ if (SIM) begin : xcvr assign gt_rx_prgdiv_reset_done = gt_rx_reset_done; assign gt_rx_cdr_lock = gt_rx_reset_done; + assign com_drp_do = 16'hCC00; + assign com_drp_rdy = 1'b1; + + assign gt_drp_do = 16'hDA00; + assign gt_drp_rdy = 1'b1; + end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr // UltraScale+ GTY (with common) @@ -482,6 +670,23 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -530,13 +735,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -573,7 +778,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -591,6 +796,23 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -639,13 +861,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -682,7 +904,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -700,6 +922,23 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -748,13 +987,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -791,7 +1030,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -809,6 +1048,23 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_common_in(xcvr_ctrl_clk), + .drpaddr_common_in(com_drp_addr), + .drpdi_common_in(com_drp_di), + .drpen_common_in(com_drp_en), + .drpwe_common_in(com_drp_we), + .drpdo_common_out(com_drp_do), + .drprdy_common_out(com_drp_rdy), + + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), @@ -857,13 +1113,13 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -900,7 +1156,7 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -918,6 +1174,15 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .qpll0clk_in(xcvr_qpll0clk_in), .qpll0refclk_in(xcvr_qpll0refclk_in), @@ -954,13 +1219,13 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -997,7 +1262,7 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -1015,6 +1280,9 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr assign xcvr_qpll1clk_out = 1'b0; assign xcvr_qpll1refclk_out = 1'b0; + assign com_drp_do = '0; + assign com_drp_rdy = 1'b1; + end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr // UltraScale/UltraScale+ GTH (channel only) @@ -1023,6 +1291,15 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr // Common .gtpowergood_out(xcvr_gtpowergood_out), + // DRP + .drpclk_in(xcvr_ctrl_clk), + .drpaddr_in(gt_drp_addr), + .drpdi_in(gt_drp_di), + .drpen_in(gt_drp_en), + .drpwe_in(gt_drp_we), + .drpdo_out(gt_drp_do), + .drprdy_out(gt_drp_rdy), + // PLL .qpll0clk_in(xcvr_qpll0clk_in), .qpll0refclk_in(xcvr_qpll0refclk_in), @@ -1059,13 +1336,13 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr .txsysclksel_in(gt_tx_qpll_sel ? 2'b11 : 2'b10), .txuserrdy_in(gt_tx_userrdy), - .txpolarity_in(GT_TX_POLARITY), - .txelecidle_in(GT_TX_ELECIDLE), - .txinhibit_in(GT_TX_INHIBIT), - .txdiffctrl_in(GT_TX_DIFFCTRL), - .txmaincursor_in(GT_TX_MAINCURSOR), - .txprecursor_in(GT_TX_PRECURSOR), - .txpostcursor_in(GT_TX_POSTCURSOR), + .txpolarity_in(ctrl_txpolarity), + .txelecidle_in(ctrl_txelecidle), + .txinhibit_in(ctrl_txinhibit), + .txdiffctrl_in(ctrl_txdiffctrl), + .txmaincursor_in(ctrl_txmaincursor), + .txprecursor_in(ctrl_txpostcursor), + .txpostcursor_in(ctrl_txprecursor), .gtwiz_userdata_tx_in(gt_txdata), .txheader_in(gt_txheader), @@ -1102,7 +1379,7 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr .rxlpmen_in(gt_rx_lpm_en), - .rxpolarity_in(GT_RX_POLARITY), + .rxpolarity_in(ctrl_rxpolarity), .rxgearboxslip_in(gt_rxgearboxslip), .gtwiz_userdata_rx_out(gt_rxdata), @@ -1120,6 +1397,9 @@ end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr assign xcvr_qpll1clk_out = 1'b0; assign xcvr_qpll1refclk_out = 1'b0; + assign com_drp_do = '0; + assign com_drp_rdy = 1'b1; + end else begin $fatal(0, "Error: invalid configuration (%m)"); diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl index 2f13481..edde548 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl @@ -22,6 +22,9 @@ set int_data_width {32} set rx_eq_mode {DFE} set extra_ports [list] set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out # PLL reset and power down lappend extra_pll_ports qpll0reset_in qpll1reset_in lappend extra_pll_ports qpll0pd_in qpll1pd_in diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_161.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_161.tcl index 011edc2..8d31291 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_161.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_161.tcl @@ -22,6 +22,9 @@ set int_data_width {32} set rx_eq_mode {DFE} set extra_ports [list] set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out # PLL reset and power down lappend extra_pll_ports qpll0reset_in qpll1reset_in lappend extra_pll_ports qpll0pd_in qpll1pd_in diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_322.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_322.tcl index bd98dbb..dd7b11a 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_322.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_322.tcl @@ -22,6 +22,9 @@ set int_data_width {32} set rx_eq_mode {DFE} set extra_ports [list] set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out # PLL reset and power down lappend extra_pll_ports qpll0reset_in qpll1reset_in lappend extra_pll_ports qpll0pd_in qpll1pd_in diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl index 277c77a..84aa521 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl @@ -22,6 +22,9 @@ set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out # PLL reset and power down lappend extra_pll_ports qpll0reset_in qpll1reset_in lappend extra_pll_ports qpll0pd_in qpll1pd_in diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl index b5319fb..91f5d89 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl @@ -22,6 +22,9 @@ set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out # PLL reset and power down lappend extra_pll_ports qpll0reset_in qpll1reset_in lappend extra_pll_ports qpll0pd_in qpll1pd_in diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl index f71bbc9..ccc4fcc 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl @@ -22,6 +22,9 @@ set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out # PLL reset and power down lappend extra_pll_ports qpll0reset_in qpll1reset_in lappend extra_pll_ports qpll0pd_in qpll1pd_in diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl index 6014181..aafd1ac 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl @@ -22,6 +22,9 @@ set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out # PLL reset and power down lappend extra_pll_ports qpll0reset_in qpll1reset_in lappend extra_pll_ports qpll0pd_in qpll1pd_in diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl index 4cec58a..6d3c353 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl @@ -22,6 +22,9 @@ set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out # PLL reset and power down lappend extra_pll_ports qpll0reset_in qpll1reset_in lappend extra_pll_ports qpll0pd_in qpll1pd_in diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl index a423d9d..6318786 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl @@ -22,6 +22,9 @@ set int_data_width $user_data_width set rx_eq_mode {DFE} set extra_ports [list] set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out # PLL reset and power down lappend extra_pll_ports qpll0reset_in qpll1reset_in lappend extra_pll_ports qpll0pd_in qpll1pd_in diff --git a/src/eth/tb/taxi_eth_mac_25g_us/test_taxi_eth_mac_25g_us.py b/src/eth/tb/taxi_eth_mac_25g_us/test_taxi_eth_mac_25g_us.py index 0ff425b..90d3314 100644 --- a/src/eth/tb/taxi_eth_mac_25g_us/test_taxi_eth_mac_25g_us.py +++ b/src/eth/tb/taxi_eth_mac_25g_us/test_taxi_eth_mac_25g_us.py @@ -28,6 +28,7 @@ from cocotb.regression import TestFactory from cocotbext.eth import XgmiiFrame, PtpClockSimTime from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame +from cocotbext.axi import ApbBus, ApbMaster try: from baser import BaseRSerdesSource, BaseRSerdesSink @@ -51,6 +52,8 @@ class TB: cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start()) cocotb.start_soon(Clock(dut.xcvr_gtrefclk00_in, 6.206, units="ns").start()) + self.apb_ctrl = ApbMaster(ApbBus.from_entity(dut.s_apb_ctrl), dut.xcvr_ctrl_clk, dut.xcvr_ctrl_rst) + self.serdes_sources = [] self.serdes_sinks = [] @@ -179,6 +182,24 @@ class TB: await RisingEdge(self.dut.xcvr_ctrl_clk) +async def run_test_regs(dut): + tb = TB(dut) + await tb.reset() + + data = await tb.apb_ctrl.read(0x00000, 2) + data = await tb.apb_ctrl.read(0x04000, 2) + data = await tb.apb_ctrl.read(0x08000, 2) + data = await tb.apb_ctrl.read(0x0C000, 2) + + data = await tb.apb_ctrl.read(0x10000, 2) + data = await tb.apb_ctrl.read(0x14000, 2) + data = await tb.apb_ctrl.read(0x18000, 2) + data = await tb.apb_ctrl.read(0x1C000, 2) + + for k in range(10): + await RisingEdge(dut.xcvr_ctrl_clk) + + async def run_test_rx(dut, port=0, payload_lengths=None, payload_data=None, ifg=12): if dut.DATA_W.value == 64: @@ -915,6 +936,9 @@ def cycle_en(): if getattr(cocotb, 'top', None) is not None: + factory = TestFactory(run_test_regs) + factory.generate_tests() + for test in [run_test_rx, run_test_tx]: factory = TestFactory(test) diff --git a/src/eth/tb/taxi_eth_mac_25g_us/test_taxi_eth_mac_25g_us.sv b/src/eth/tb/taxi_eth_mac_25g_us/test_taxi_eth_mac_25g_us.sv index b7bc168..0a05e3d 100644 --- a/src/eth/tb/taxi_eth_mac_25g_us/test_taxi_eth_mac_25g_us.sv +++ b/src/eth/tb/taxi_eth_mac_25g_us/test_taxi_eth_mac_25g_us.sv @@ -75,6 +75,12 @@ localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1; logic xcvr_ctrl_clk; logic xcvr_ctrl_rst; +// transceiver control +taxi_apb_if #( + .ADDR_W(24), + .DATA_W(16) +) s_apb_ctrl(); + logic xcvr_gtpowergood_out; logic xcvr_gtrefclk00_in; logic xcvr_qpll0pd_in; @@ -276,6 +282,11 @@ uut ( .xcvr_ctrl_clk(xcvr_ctrl_clk), .xcvr_ctrl_rst(xcvr_ctrl_rst), + /* + * Transceiver control + */ + .s_apb_ctrl(s_apb_ctrl), + /* * Common */ diff --git a/src/hip/rtl/us/taxi_gt_rx_reset.sv b/src/hip/rtl/us/taxi_gt_rx_reset.sv index a307377..10ea6ec 100644 --- a/src/hip/rtl/us/taxi_gt_rx_reset.sv +++ b/src/hip/rtl/us/taxi_gt_rx_reset.sv @@ -30,6 +30,7 @@ module taxi_gt_rx_reset # /* * GT */ + input wire logic gt_rxusrclk2, output wire logic gt_rx_pd_out, output wire logic gt_rx_reset_out, input wire logic gt_rx_reset_done_in, @@ -94,6 +95,16 @@ gt_status_sync_inst ( .out({gt_rx_reset_done_sync, gt_rx_pma_reset_done_sync, gt_rx_prgdiv_reset_done_sync, gt_userclk_rx_active_sync, gt_rx_cdr_lock_sync}) ); +taxi_sync_signal #( + .WIDTH(1), + .N(2) +) +gt_ctrl_sync_inst ( + .clk(gt_rxusrclk2), + .in({gt_rx_pd_reg}), + .out({gt_rx_pd_out}) +); + wire rx_reset_sync; taxi_sync_reset #( @@ -119,7 +130,6 @@ logic rx_reset_done_reg = 1'b0; assign rx_reset_done_out = rx_reset_done_reg; -assign gt_rx_pd_out = gt_rx_pd_reg; assign gt_rx_reset_out = gt_rx_reset_reg; assign gt_rx_pma_reset_out = gt_rx_pma_reset_reg; assign gt_rx_dfe_lpm_reset_out = gt_rx_dfe_lpm_reset_reg; diff --git a/src/hip/rtl/us/taxi_gt_tx_reset.sv b/src/hip/rtl/us/taxi_gt_tx_reset.sv index 598d5c3..6ba3dae 100644 --- a/src/hip/rtl/us/taxi_gt_tx_reset.sv +++ b/src/hip/rtl/us/taxi_gt_tx_reset.sv @@ -28,6 +28,7 @@ module taxi_gt_tx_reset # /* * GT */ + input wire logic gt_txusrclk2, output wire logic gt_tx_pd_out, output wire logic gt_tx_reset_out, input wire logic gt_tx_reset_done_in, @@ -81,6 +82,16 @@ gt_status_sync_inst ( .out({gt_tx_reset_done_sync, gt_tx_pma_reset_done_sync, gt_tx_prgdiv_reset_done_sync, gt_userclk_tx_active_sync}) ); +taxi_sync_signal #( + .WIDTH(1), + .N(2) +) +gt_ctrl_sync_inst ( + .clk(gt_txusrclk2), + .in({gt_tx_pd_reg}), + .out({gt_tx_pd_out}) +); + wire tx_reset_sync; taxi_sync_reset #( @@ -102,7 +113,6 @@ logic [1:0] state_reg = STATE_RESET; logic [CNT_W-1:0] tx_reset_cnt_reg = '0; logic tx_reset_done_reg = 1'b0; -assign gt_tx_pd_out = gt_tx_pd_reg; assign gt_tx_reset_out = gt_tx_reset_reg; assign gt_tx_pma_reset_out = gt_tx_pma_reset_reg; assign gt_tx_pcs_reset_out = gt_tx_pcs_reset_reg;